Beruflich Dokumente
Kultur Dokumente
APPLICATIONS
ACSHIELD VCC
8
GND
BIAS
10
11
POWER-ON
RESET LOGIC
CIN0 19
CIN1 20
CIN2 21
EXCITATION
SOURCE
CIN3 22
CIN4 23
CIN5 24
CIN6 1
CIN7 2
CIN8 3
CIN9
CALIBRATION
RAM
AD7147/
AD7147-1
16-BIT
-
CDC
CALIBRATION
ENGINE
CIN10 5
CIN11 6
CONTROL
AND DATA
REGISTERS
CIN12 7
VDRIVE 12
INTERRUPT
AND GPIO
LOGIC
SERIAL INTERFACE
AND CONTROL LOGIC
13
14
15
16
18
GPIO
17
INT
06663-001
SWITCH
MATRIX
Data Sheet
Figure 1.
Cell phones
Personal music and multimedia players
Smart handheld devices
Television, A/V, and remote controls
Gaming consoles
Digital still cameras
GENERAL DESCRIPTION
The AD7147 CapTouch controller is designed for use with
capacitance sensors implementing functions such as buttons,
scroll bars, and wheels. The sensors need only one PCB layer,
enabling ultrathin applications.
The AD7147 is an integrated CDC with on-chip environmental
calibration. The CDC has 13 inputs channeled through a switch
matrix to a 16-bit, 250 kHz sigma-delta (-) converter. The CDC
is capable of sensing changes in the capacitance of the external
sensors and uses this information to register a sensor activation.
By programming the registers, the user has full control over the
CDC setup.
Document Feedback
Comparable Parts
Reference Materials
Technical Articles
MS-2210: Designing Power Supplies for High Speed ADC
Evaluation Kits
EVAL-AD7147 & EVAL-AD7147-1 Evaluation Boards
Documentation
Application Notes
AN-925: Sensors for the AD7147 and AD7148 CapTouch
Controllers
AN-929: Tuning the AD714x for CapTouch Applications
AN-957: Layout Guidelines for the AD7147 and AD7148
CapTouch Controllers
Data Sheet
AD7147: CapTouch Programmable Controller for SingleElectrode Capacitance Sensors Data Sheet
Product Highlight
Leading Inside Advertorials: Providing an Edge in
Capacitive Sensor Applications
Design Resources
Discussions
View all AD7147 EngineerZone Discussions
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
AD7147
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
SLOW_FILTER_UPDATE_LVL .............................................. 26
Specifications..................................................................................... 4
Outputs ............................................................................................ 33
Capacitiance-to-Digital Converter............................................... 15
Recalibration ............................................................................... 19
FF_SKIP_CNT ............................................................................ 22
Rev. E | Page 2 of 70
Data Sheet
AD7147
REVISION HISTORY
1/15Rev. D to Rev. E
Updated Outline Dimensions ........................................................70
Changes to Ordering Guide ...........................................................70
7/09Rev. A to Rev. B
Changes to BIAS Pin Description ................................................... 8
Changes to BIAS Pin Section ......................................................... 12
9/11Rev. C to Rev. D
Changes to Ordering Guide ...........................................................70
8/08Rev. 0 to Rev. A
Changes to Table 3 ............................................................................ 4
Added Figure 3, Renumbered Sequentially ................................... 6
Changes to Low Power Mode Section .......................................... 13
Added Latency from Touch to Response Section ....................... 13
Added Low Latency from Touch to Response Section .............. 13
Changes to Figure 60 and Figure 61 ............................................. 40
Changes to Figure 62 ...................................................................... 41
Added Exposed Pad Notation to Outline Dimensions .............. 68
5/11Rev. B to Rev. C
Changes to Features Section ............................................................ 1
Changes to Ordering Guide ...........................................................70
Added Automotive Products Section ...........................................70
Rev. E | Page 3 of 70
AD7147
Data Sheet
SPECIFICATIONS
VCC = 2.6 V to 3.6 V, TA = 40oC to +85C, unless otherwise noted.
Table 1.
Parameter
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
Resolution
CINx Input Range
No Missing Codes
Min
Typ
Max
Unit
Test Conditions/Comments
8.73
17.46
34.9
9
18
36
16
8
9.27
18.54
37.1
ms
ms
ms
Bits
pF
Bits
16
25
20
20
12
7
3
1.1
0.8
0.5
20
0.32
250
0
VCC
10
10
150
0.7 VDRIVE
0.4
1
1
150
kHz
V
mA
mA
pF
V
V
A
A
mV
Oscillating
VIN = VDRIVE
VIN = GND
0.4
1
V
A
ISINK = 1 mA
VOUT = VDRIVE
0.4
1
V
V
A
0.9
15.5
3.6
3.6
1
21.5
V
V
mA
A
2.3
7.5
0.1
VDRIVE 0.6
2.6
1.65
nA
pF
%
Codes
Codes
Codes
Codes
Codes
Codes
pF
pF
%
3.3
Rev. E | Page 4 of 70
Data Sheet
AD7147
400 ms
600 ms
800 ms
Decimation
Rate
64
128
256
64
128
256
64
128
256
64
128
256
1
20.83
25.3
34.11
18.17
20.43
24.9
17.28
18.79
21.79
16.84
17.97
20.23
2
24.18
31.92
46.99
19.86
23.79
31.53
18.41
21.04
26.25
17.69
19.66
23.59
3
27.52
38.45
59.51
21.55
27.12
38.06
19.54
23.28
30.67
18.53
21.35
26.93
10
50.16
81.52
137.81
33.17
49.78
81.17
27.36
38.65
60.39
24.43
32.98
49.6
11
53.3
87.33
147.82
34.81
52.93
86.98
28.47
40.81
64.47
25.26
34.62
52.74
12
56.41
93.05
157.58
36.44
56.05
92.71
29.57
42.95
68.51
26.09
36.25
55.86
10
63.69
101.74
169.61
43.04
63.26
101.34
35.96
49.72
76.15
32.38
42.81
63.04
11
67.51
108.77
181.63
45.03
67.08
108.37
37.31
52.34
81.1
33.4
44.81
66.86
12
71.29
115.69
193.33
47.02
70.87
115.3
38.66
54.95
86.01
34.42
46.79
70.66
4
30.82
44.87
71.66
23.23
30.43
44.5
20.67
25.51
35.04
19.38
23.03
30.24
400 ms
600 ms
800 ms
Decimation
Rate
64
128
256
64
128
256
64
128
256
64
128
256
1
27.96
33.41
44.16
24.74
27.49
32.95
23.66
25.5
29.17
23.12
24.5
27.26
2
32.06
41.49
59.85
26.8
31.59
41.04
25.04
28.25
34.61
24.16
26.57
31.36
3
36.12
49.44
75.05
28.86
35.66
49
26.42
30.99
40
25.19
28.63
35.44
4
40.15
57.26
89.79
30.91
39.7
56.83
27.79
33.71
45.33
26.23
30.68
39.47
Rev. E | Page 5 of 70
AD7147
Data Sheet
Limit
5
5
20
20
15
15
20
16
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
Description
SCLK frequency
CS falling edge to first SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SDI setup time
SDI hold time
SDO access time after SCLK falling edge
CS rising edge to SDO high impedance
SCLK rising edge to CS high
t1
t2
1
SCLK
t8
t3
2
15
16
15
16
t4
t5
LSB
t6
SDO
MSB
Rev. E | Page 6 of 70
t7
LSB
06663-002
SDI
MSB
Data Sheet
AD7147
Limit
400
0.6
1.3
0.6
100
300
0.6
0.6
1.3
300
300
Unit
kHz max
s min
s min
s min
ns min
ns min
s min
s min
s min
ns max
ns max
Description
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus-free time between stop and start conditions, tBUF
Clock/data rise time
Clock/data fall time
t2
tF
t1
SCLK
t3
t1
t5
t7
t6
t4
SDA
STOP START
START
STOP
200A
1.6V
CL
50pF
200A
IOH
06663-004
TO OUTPUT
PIN
IOL
Rev. E | Page 7 of 70
06663-003
t8
AD7147
Data Sheet
Rating
0.3 V to +3.6 V
0.3 V to VCC + 0.3 V
0.3 V to VDRIVE + 0.3 V
0.3 V to VDRIVE + 0.3 V
10 mA
2.5 kV
40C to +105C
65C to +150C
150C
ESD CAUTION
450 mW
135.7C/W
260C (0.5C)
300C
Rev. E | Page 8 of 70
Data Sheet
AD7147
PIN 1
INDICATOR
AD7147
TOP VIEW
(Not to Scale)
18
17
16
15
14
13
GPIO
INT
CS
SCLK
SDI
SDO
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
PIN 1
INDICATOR
AD7147-1
18
17
16
15
14
13
GPIO
INT
ADD1
SCLK
ADD0
SDA
7
8
9
10
11
12
TOP VIEW
(Not to Scale)
CIN12
ACSHIELD
BIAS
GND
VCC
VDRIVE
06663-005
CIN12
ACSHIELD
BIAS
GND
VCC
VDRIVE
1
2
3
4
5
6
06663-006
1
2
3
4
5
6
7
8
9
10
11
12
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
24
23
22
21
20
19
24
23
22
21
20
19
CIN5
CIN4
CIN3
CIN2
CIN1
CIN0
CIN5
CIN4
CIN3
CIN2
CIN1
CIN0
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY
IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED
RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY
IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
Pin No.
AD7147-1
1
2
3
4
5
6
7
8
9
10
11
12
N/A
13
N/A
14
15
N/A
16
17
18
19
20
21
22
23
24
Mnemonic
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
ACSHIELD
BIAS
GND
VCC
VDRIVE
SDO
SDA
SDI
ADD0
SCLK
CS
ADD1
INT
GPIO
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
Description
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
CDC Active Shield Output. Connect to external shield or plane.
Bias Node for Internal Circuitry. Requires 100 nF capacitor to ground.
Ground Reference Point for All Circuitry.
Supply Voltage.
Serial Interface Operating Voltage Supply.
SPI Serial Data Output.
I2C Serial Data Input/Output. SDA requires pull-up resistor.
SPI Serial Data Input.
I2C Address Bit 0.
Clock Input for Serial Interface.
SPI Chip Select Signal.
I2C Address Bit 1.
General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
Programmable GPIO.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Rev. E | Page 9 of 70
AD7147
Data Sheet
70
915
60
895
200ms
50
875
ICC (A)
ICC (A)
DECIMATION = 64
DECIMATION = 128
DECIMATION = 256
855
40
400ms
600ms
30
815
10
795
2.6
06663-007
20
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
06663-060
800ms
835
0
2.5
3.7
3.3
3.1
2.9
2.7
VCC (V)
3.5
3.7
VCC (V)
180
2.5
200ms
160
2.0
140
100
ICC (A)
ICC (A)
120
400ms
80
600ms
1.5
1.0
60
800ms
40
0
2.5
2.7
2.9
3.1
3.3
3.5
0
2.7
3.7
06663-010
06663-061
0.5
20
2.8
2.9
3.0
VCC (V)
3.1
3.2
3.3
3.4
3.5
3.6
VCC (V)
0.12
1150
0.10
200ms
1100
ICC (A)
0.06
400ms
600ms
1050
1000
0.04
800ms
0
2.5
2.7
2.9
3.1
3.3
3.5
3.7
06663-062
950
0.02
06663-009
ICC (mA)
0.08
900
0
VCC (V)
100
200
300
400
500
Rev. E | Page 10 of 70
Data Sheet
AD7147
160
58000
56000
140
54000
75mV
100mV
125mV
150mV
175mV
200mV
120
52000
50000
48000
46000
100
80
60
40
44000
1640000
409600
819200
102400
204800
25600
51200
6400
12800
1600
500
3200
400
400
300
800
200
200
100
25
50
40000
06663-064
20
06663-063
42000
100
25mV
50mV
960
120
25mV
50mV
940
3.6V
75mV
100mV
125mV
150mV
175mV
200mV
100
CDC NOISE p-p (LSB)
920
900
ICC (A)
3.3V
880
860
840
820
80
60
40
2.6V
10
30
INPUT CAPACITANCE (pF)
12
6
3.6V
3.3V
2.6V
2
25
15
35
55
75
95
115
20
15
10
06663-016
0
45
25
06663-014
ICC (A)
1640000
819200
409600
204800
102400
51200
25600
TEMPERATURE (C)
6400
120
12800
100
3200
80
1600
60
800
40
400
20
200
100
20
50
40
25
780
60
06663-065
06663-013
20
800
135
TEMPERATURE (C)
10000
20000
30000
40000
50000
Rev. E | Page 11 of 70
60000
AD7147
Data Sheet
THEORY OF OPERATION
PLASTIC COVER
SENSOR PCB
MUX
The AD7147 has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
affect the operation of capacitance sensors. Transparent to the
user, the AD7147 performs continuous calibration to compensate for these effects, allowing the AD7147 to consistently
provide error-free results.
AD7147
-
ADC
16-BIT
DATA
EXCITATION
SIGNAL
250kHz
06663-017
The AD7147 and AD7147-1 are CDCs with on-chip environmental compensation. They are intended for use in portable
systems requiring high resolution user input. The internal
circuitry consists of a 16-bit, - converter that can change a
capacitive input signal into a digital value. There are 13 input
pins, CIN0 to CIN12, on the AD7147 or AD7147-1. A switch
matrix routes the input signals to the CDC. The result of each
capacitance-to-digital conversion is stored in on-chip registers.
The host subsequently reads the results over the serial interface.
The AD7147 has an SPI interface, and the AD7147-1 has an I2C
interface, ensuring that the parts are compatible with a wide
range of host processors. AD7147 refers to both the AD7147 and
AD7147-1, unless otherwise noted, from this point forward in
this data sheet.
Rev. E | Page 12 of 70
Data Sheet
AD7147
AD7147
STAGEx_HIGH_THRESHOLD
SPI OR I2C
HOST PROCESSOR
1 MIPS
10kB ROM
600 BYTES RAM
CDC_RESULT_Sx
AMBIENT OR
NO-TOUCH VALUE
STAGEx_LOW_THRESHOLD
06663-018
06663-019
BIAS PIN
OPERATING MODES
The AD7147 has three operating modes. Full power mode, where
the device is always fully powered, is suited for applications where
power is not a concern (for example, game consoles that have an
ac power supply). Low power mode, where the part automatically
powers down when no sensor is active, is tailored to provide
significant power savings compared with full power mode and
is suited for mobile applications, where power must be
conserved. In shutdown mode, the part shuts down completely.
The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7147. The control
register is at Address 0x000. Table 8 shows the POWER_MODE
settings for each operating mode. To put the AD7147 into
shutdown mode, set the POWER_MODE bits to either 01 or 11.
Table 8. POWER_MODE Settings
POWER_MODE Bits
00
01
10
11
Operating Mode
Full power mode
Shutdown mode
Low power mode
Shutdown mode
Rev. E | Page 13 of 70
AD7147
Data Sheet
AD7147P SETUP
AND INITIALIZATION
POWER_MODE = 10
AD7147 SETUP
AND INITIALIZATION
POWER_MODE = 10
ANY
SENSOR
TOUCHED?
CONVERSION SEQUENCE
EVERY LP_CONV_DELAY
UPDATE COMPENSATION
LOGIC DATA PATH
NO
YES
CONVERSION SEQUENCE
EVERY 9/18/36ms FOR
SENSOR READBACK
YES
USER IN
PROXIMITY
TO SENSOR?
CONVERSION SEQUENCE
EVERY LP_CONV_DELAY
UPDATE COMPENSATION
LOGIC DATA PATH
YES
CONVERSION SEQUENCE
EVERY 9/18/36ms FOR
SENSOR READBACK
YES
ANY SENSOR
TOUCHED?
NO
06663-020
NO
PROXIMITY TIMER TIMEOUT
COUNTDOWN
USER IN
PROXIMITY
TO SENSOR?
Rev. E | Page 14 of 70
06663-066
NO
Data Sheet
AD7147
CAPACITIANCE-TO-DIGITAL CONVERTER
from midscale, decrease the POS_AFE_OFFSET or
NEG_AFE_OFFSET value by 1.
+DAC
(20pF RANGE)
2.
3.
POS_AFE_OFFSET
POS_AFE_OFFSET_SWAP BIT
CINx
16-BIT
_ CDC
16
NEG_AFE_OFFSET_SWAP BIT
DAC
(20pF RANGE)
NEG_AFE_OFFSET
CINx_CONNECTION_SETUP
06663-021
Decimation Bits
00
01
10
11
CONVERSION SEQUENCER
The AD7147 has an on-chip sequencer to implement conversion
control for the input channels. Up to 12 conversion stages can be
performed in one sequence. Each of the 12 conversions stages can
measure the input from a different sensor. By using the Bank 2
registers, each stage can be uniquely configured to support multiple
capacitance sensor interface requirements. For example, a slider
sensor can be assigned to STAGE1 through STAGE8, with a
button sensor assigned to STAGE0. For each conversion stage,
the input mux that connects the CINx inputs to the converter
can have a unique setting.
The AD7147 on-chip sequence controller provides conversion
control, beginning with STAGE0. Figure 25 shows a block diagram
of the CDC conversion stages and CINx inputs. A conversion
sequence is defined as a sequence of CDC conversions starting
at STAGE0 and ending at the stage determined by the value
programmed in the SEQUENCE_STAGE_NUM bits. Depending
on the number and type of capacitance sensors that are used, not all
conversion stages are required. Use the SEQUENCE_STAGE_NUM
bits to set the number of conversions in one sequence. This number
depends on the sensor interface requirements. For example, the
register should be set to 5 if the CINx inputs are mapped to only six
conversion stages. In addition, the STAGE_CAL_EN register
should be set according to the number of stages that are used.
The number of required conversion stages depends solely on
the number of sensors attached to the AD7147. Figure 26 shows
how many conversion stages are required for each sensor and
how many inputs to the AD7147 each sensor requires.
Rev. E | Page 15 of 70
AD7147
Data Sheet
A wheel sensor requires eight stages, whereas a slider requires two
stages. The result from each stage is used by the host software to
determine the users position on the slider or wheel. The algorithms
that perform this process are available from Analog Devices and are
free of charge, but require signing a software license.
STAGE11
STAGE10
STAGE9
STAGE8
STAGE7
STAGE6
STAGE5
STAGE4
STAGE3
STAGE2
STAGE1
STAGE0
CIN0
CIN1
CIN6
CIN7
CIN8
CIN9
SEQ
UEN
CE
CIN5
-
16-BIT
ADC
I ON
CIN4
CO
NVE
RS
CIN3
SWITCH MATRIX
CIN2
CIN10
06663-022
CIN11
CIN12
AD7147
SEQUENCER
STAGE0
+
CDC
STAGE1
+
CDC
STAGE2
+ CDC
SEQUENCER
B1
STAGE8
+ CDC
B2
STAGE9
+ CDC
B3
STAGE3
+ CDC
STAGE4
+ CDC
SEQUENCER
STAGE5
+
CDC
STAGE10
+ CDC
AD7147
SLIDER
STAGE6
+ CDC
STAGE7
+ CDC
Rev. E | Page 16 of 70
STAGE11
+ CDC
06663-023
SCROLL
WHEEL
AD7147
BUTTONS
Data Sheet
AD7147
Decimation = 64
0.768
1.536
2.304
3.072
3.84
4.608
5.376
6.144
6.912
7.68
8.448
9.216
tCONV_LP
tCONV_FP
CDC
CONVERSION
CONVERSION
SEQUENCE N
LP_CONV_DELAY
CONVERSION
SEQUENCE N + 1
06663-024
CONVERSION
SEQUENCE N
tCONV_FP
CDC
CONVERSION
Decimation = 256
3.072
6.144
9.216
12.288
15.36
18.432
21.504
24.576
27.648
30.72
33.792
36.864
06663-025
SEQUENCE_STAGE_NUM
0
1
2
3
4
5
6
7
8
9
10
11
Rev. E | Page 17 of 70
AD7147
Data Sheet
Examples
To connect CIN3 to the positive CDC input on Stage 0 use the
following setting:
STAGE0_CONNECTION[6:0] = 0xFFBF
STAGE0_CONNECTION[12:7] = 0x2FFF
STAGE5_CONNECTION[6:0] = 0xFFFE
STAGE5_CONNECTION[12:7] = 0x37FF
CIN SETTING
00
CINx FLOATING
01
CINx CONNECTED TO
NEGATIVE CDC INPUT
10
CINx CONNECTED TO
POSITIVE CDC INPUT
11
CINx CONNECTED TO
BIAS
CDC
06663-026
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
Data Sheet
AD7147
RECALIBRATION
PROXIMITY SENSITIVITY
Rev. E | Page 19 of 70
AD7147
Data Sheet
Length
(Bits)
4
4
8
6
8
Register Address
0x002[7:4]
0x002[11:8]
0x004[9:0]
0x004[15:10]
0x003[7:0]
PROXIMITY_DETECTION_RATE
0x003[13:8]
USER APPROACHES
SENSOR
Description
Calibration disable time in full power mode.
Calibration disable time in low power mode.
Full power mode proximity recalibration time.
Low power mode proximity recalibration time.
Proximity recalibration level. This value multiplied by 16 controls the
sensitivity of Comparator 2 (see Figure 34).
Proximity detection rate. This value multiplied by 16 controls the
sensitivity of Comparator 1 (see Figure 34).
USER LEAVES
SENSOR AREA
tCONV_FP
CDC CONVERSION
SEQUENCE
(INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tCALDIS
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
06663-027
PROXIMITY
DETECTION
(INTERNAL)
USER APPROACHES
SENSOR
USER LEAVES
SENSOR AREA
tCONV_LP
CDC CONVERSION
SEQUENCE
(INTERNAL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY.
2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR, AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.
3. tCALDIS = (tCONV_LP LP_PROXIMITY_CNT 4).
Rev. E | Page 20 of 70
06663-028
CALIBRATION
(INTERNAL)
Data Sheet
AD7147
USER APPROACHES
SENSOR
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES
SENSOR AREA
tCONV_FP
16
CDC CONVERSION
SEQUENCE
(INTERNAL)
30
70
tCALDIS
PROXIMITY
DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIMEOUT
CALIBRATION ENABLED
tRECAL_TIMEOUT
RECALIBRATION
COUNTER
(INTERNAL)
06663-029
NOTES
1. SEQUENCE CONVERSION TIME tCONV_FP (SEE TABLE 10).
2. tCALDIS = tCONV_FP FP_PROXIMITY_CNT 16.
3. tRECAL_TIMEOUT = tCONV_FP FP_PROXIMITY_RECAL.
4. tRECAL = 2 tCONV_FP .
Figure 32. Example of Full Power Mode Proximity Detection with Forced Recalibration (FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40)
USER APPROACHES
SENSOR
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES
SENSOR AREA
tCONV_LP
16
30
PROXIMITY
DETECTION
(INTERNAL)
tCALDIS
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
70
RECALIBRATION TIMEOUT
CALIBRATION ENABLED
tRECAL_TIMEOUT
RECALIBRATION
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP = tCONV_FP + LP_CONV_DELAY.
2. tCALDIS = tCONV_LP LP_PROXIMITY_CNT 4.
3. tRECAL_TIMEOUT = tCONV_LP LP_PROXIMITY_RECAL.
4. tRECAL = 2 tCONV_LP .
Figure 33. Example of Low Power Mode Proximity Detection with Forced Recalibration (LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40)
Rev. E | Page 21 of 70
06663-030
CDC CONVERSION
SEQUENCE
(INTERNAL)
AD7147
Data Sheet
FF_SKIP_CNT
The proximity detection fast FIFO is used by the on-chip logic
to determine if proximity is detected. The fast FIFO expects to
receive samples from the converter at a set rate. FF_SKIP_CNT
is used to normalize the frequency of the samples going into the
FIFO, regardless of how many conversion stages are in a sequence.
In Register 0x002, Bits[3:0] are the fast filter skip control,
FF_SKIP_CNT. This value determines which CDC samples
are not used (skipped) by the proximity detection fast FIFO.
Decimation = 64
0.768 (SEQUENCE_STAGE_NUM + 1) ms
1.536 (SEQUENCE_STAGE_NUM + 1) ms
2.3 (SEQUENCE_STAGE_NUM + 1) ms
3.072 (SEQUENCE_STAGE_NUM + 1) ms
3.84 (SEQUENCE_STAGE_NUM + 1) ms
4.6 (SEQUENCE_STAGE_NUM + 1) ms
5.376 (SEQUENCE_STAGE_NUM + 1) ms
6.144 (SEQUENCE_STAGE_NUM + 1) ms
6.912 (SEQUENCE_STAGE_NUM + 1) ms
7.68 (SEQUENCE_STAGE_NUM + 1) ms
8.448 (SEQUENCE_STAGE_NUM + 1) ms
9.216 (SEQUENCE_STAGE_NUM + 1) ms
9.984 (SEQUENCE_STAGE_NUM + 1) ms
10.752 (SEQUENCE_STAGE_NUM + 1) ms
11.52 (SEQUENCE_STAGE_NUM + 1) ms
12.288 (SEQUENCE_STAGE_NUM + 1) ms
Rev. E | Page 22 of 70
Decimation = 256
3.072 (SEQUENCE_STAGE_NUM + 1) ms
6.144 (SEQUENCE_STAGE_NUM + 1) ms
9.216 (SEQUENCE_STAGE_NUM + 1) ms
12.288 (SEQUENCE_STAGE_NUM + 1) ms
15.36 (SEQUENCE_STAGE_NUM + 1) ms
18.432 (SEQUENCE_STAGE_NUM + 1) ms
21.504 (SEQUENCE_STAGE_NUM + 1) ms
24.576 (SEQUENCE_STAGE_NUM + 1) ms
27.648 (SEQUENCE_STAGE_NUM + 1) ms
30.72 (SEQUENCE_STAGE_NUM + 1) ms
33.792 (SEQUENCE_STAGE_NUM + 1) ms
36.864 (SEQUENCE_STAGE_NUM + 1) ms
39.936 (SEQUENCE_STAGE_NUM + 1) ms
43.008 (SEQUENCE_STAGE_NUM + 1) ms
46.08 (SEQUENCE_STAGE_NUM + 1) ms
49.152 (SEQUENCE_STAGE_NUM + 1) ms
Data Sheet
CDC
AD7147
FP_PROXIMITY_CNT
REGISTER 0x002
16
LP_PROXIMITY_CNT
REGISTER 0x002
STAGEx_FF_WORD0
STAGEx_FF_WORD1
STAGEx_FF_WORD2
COMPARATOR 1
|WORD0 WORD3|
PROXIMITY 1
PROXIMITY
STAGEx_FF_WORD3
STAGEx_FF_WORD4
STAGEx_FF_WORD5
STAGEx_FF_WORD6
STAGEx_FF_WORD7
PROXIMITY_DETECTION_RATE
REGISTER 0x003
WORD(N)
N=0
FP_PROXIMITY_RECAL
REGISTER 0x004
LP_PROXIMITY_RECAL
REGISTER 0x004
PROXIMITY 2
BANK 3 REGISTERS
PROXIMITY TIMING
CONTROL LOGIC
STAGEx_FF_AVG
BANK 3 REGISTERS
8
COMPARATOR 2
|AVERAGE AMBIENT|
STAGEx_FF_WORDx
PROXIMITY
SLOW_FILTER_UPDATE_LVL
REGISTER 0x003
STAGEx_SF_WORD0
STAGEx_SF_WORD1
STAGEx_SF_WORD2
STAGEx_SF_WORD3
PROXIMITY_RECAL_LVL
REGISTER 0x003
STAGEx_SF_AMBIENT
BANK 3 REGISTERS
STAGEx_SF_WORD4
STAGEx_SF_WORD5
STAGEx_SF_WORD6
AMBIENT
VALUE
STAGEx_SF_WORDx
SENSOR
CONTACT
STAGEx_SF_WORD7
BANK 3 REGISTERS
NOTES
1. SLOW_FILTER_EN, WHICH IS THE NAME OF THE OUTPUT OF COMPARATOR 3, IS SET AND SW1 IS CLOSED WHEN |STAGEx_SF_WORD0 CDC VALUE|
EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER PROVIDING PROXIMITY IS NOT SET.
2. PROXIMITY 1 IS SET WHEN |STAGEx_FF_WORD0 STAGEx_FF_WORD3| EXCEEDS THE VALUE PROGRAMMED IN THE
PROXIMITY_DETECTION_RATE REGISTER.
3. PROXIMITY 2 IS SET WHEN |AVERAGE AMBIENT| EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.
4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW_FILTER_EN IS SET AND
PROXIMITY IS NOT SET.
Rev. E | Page 23 of 70
06663-031
COMPARATOR 3
WORD0 CDC VALUE
SLOW_FILTER_EN
SW1
AD7147
Data Sheet
ENVIRONMENTAL CALIBRATION
STAGEx_LOW_THRESHOLD
06663-032
SENSOR 2 INT
ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
SENSOR 2 INT
NOT ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Rev. E | Page 24 of 70
06663-033
STAGEx_HIGH_THRESHOLD
SENSOR 1 INT
ASSERTED
Data Sheet
AD7147
THRESHOLD EQUATIONS
On-Chip Logic Stage High Threshold
STAGEx _ OFFSET _ HIGH
4
POS _ THRESHOLD_ SENSITIVITY
16
(1)
4
NEG _ THRESHOLD _ SENSITIVITY
16
SLOW FIFO
STAGEx_HIGH_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
CDC AMBIENT
VALUE DRIFTING
STAGEx_LOW_THRESHOLD
(POSTCALIBRATED
REGISTER VALUE)
4
SENSOR 2 INT
ASSERTED
t
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples from
the converter at a rate between 33 ms and 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many conversion
stages are in a sequence.
6
5
(2)
Figure 37. Typical Sensor Behavior with Calibration Applied on the Data Path
Rev. E | Page 25 of 70
AD7147
Data Sheet
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL controls whether the most
recent CDC measurement goes into the slow FIFO (slow filter).
The slow filter is updated when the difference between the
current CDC value and the last value of the slow FIFO is greater
Rev. E | Page 26 of 70
Data Sheet
AD7147
STAGEx_OFFSET_HIGH
IS UPDATED
AVERAGE MAXIMUM VALUE
62.51% =
POS_THRESHOLD
_SENSITIVITY
STAGEx_OFFSET_HIGH
95.32%
STAGEx_OFFSET_HIGH
IS UPDATED
62.51% =
POS_THRESHOLD
_SENSITIVITY
25%
25%
AMBIENT LEVEL
25%
NEG_THRESHOLD_SENSITIVITY = 39.08%
STAGEx_OFFSET_LOW
IS UPDATED
STAGEx_OFFSET_LOW
25%
NEG_THRESHOLD_SENSITIVITY = 39.08%
95.32%
STAGEx_OFFSET_LOW
IS UPDATED
95.32%
SENSOR CONTACTED
BY LARGE FINGER
SENSOR CONTACTED
BY SMALL FINGER
Rev. E | Page 27 of 70
06663-035
95.32%
AD7147
Data Sheet
STAGEx_MAX_WORD0
STAGEx_MAX_WORD1
STAGEx_MAX_WORD2
BANK 3 REGISTERS
STAGEx_MAX_WORD3
-
16-BIT
CDC
16
MAXIMUM
LEVEL
DETECTION
LOGIC
STAGEx_MAX_AVG
BANK 3 REGISTERS
STAGEx_MAX_TEMP
BANK 3 REGISTERS
STAGEx_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGEx_MIN_WORD0
STAGEx_MIN_WORD1
STAGEx_MIN_WORD2
BANK 3 REGISTERS
STAGEx_MIN_WORD3
MINIMUM
LEVEL
DETECTION
LOGIC
STAGEx_MIN_AVG
BANK 3 REGISTERS
STAGEx_LOW_THRESHOLD
BANK 3 REGISTERS
06663-036
STAGEx_MIN_TEMP
BANK 3 REGISTERS
Figure 39. Tracking the Minimum and Maximum Average Sensor Values
Table 14. Additional Information About Environmental Calibration and Adaptive Threshold Registers
Register/Bit
NEG_THRESHOLD_SENSITIVITY
NEG_PEAK_DETECT
Register
Location
Bank 2
Bank 2
POS_THRESHOLD_SENSITIVITY
POS_PEAK_DETECT
Bank 2
Bank 2
STAGEx_OFFSET_LOW
Bank 2
STAGEx_OFFSET_HIGH
Bank 2
STAGEx_OFFSET_HIGH_CLAMP
Bank 2
STAGEx_OFFSET_LOW_CLAMP
Bank 2
STAGEx_SF_AMBIENT
Bank 3
STAGEx_HIGH_THRESHOLD
STAGEx_LOW_THRESHOLD
Bank 3
Bank 3
Description
Used in Equation 2. This value is programmed once at startup.
Used by internal adaptive threshold logic only.
The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the minimum average CDC value. If the output of the CDC approaches the
NEG_PEAK_DETECT percentage of the minimum average, the minimum average value is updated.
Used in Equation 1. This value is programmed once at startup.
Used by internal adaptive threshold logic only.
The POS_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value and the maximum average CDC value. If the output of the CDC approaches the
POS_PEAK_DETECT percentage of the maximum average, the maximum average value is updated.
Used in Equation 2. An initial value (based on sensor characterization) is programmed into
this register at startup. The AD7147 on-chip calibration algorithm automatically updates this
register based on the amount of sensor drift due to changing ambient conditions. Set this
register to 80% of the STAGEx_OFFSET_LOW_CLAMP value.
Used in Equation 1. An initial value (based on sensor characterization) is programmed into
this register at startup. The AD7147 on-chip calibration algorithm automatically updates this
register based on the amount of sensor drift due to changing ambient conditions. Set this
register to 80% of the STAGEx_OFFSET_HIGH_CLAMP value.
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at startup.
The value in this register prevents a user from causing the output value of a sensor to exceed
the expected nominal value.
Set this register to the maximum expected sensor response or the maximum change in CDC
output code.
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at startup.
The value in this register prevents a user from causing the output value of a sensor to exceed
the expected nominal value.
Set this register to the minimum expected sensor response or the minimum change in CDC
output code.
Used in Equation 1 and Equation 2. This is the ambient sensor output when the sensor is not
touched, as calculated using the slow FIFO.
Equation 1 value.
Equation 2 value.
Rev. E | Page 28 of 70
Data Sheet
AD7147
INTERRUPT OUTPUT
The AD7147 has an interrupt output that triggers an interrupt
service routine on the host processor. The INT signal is on
Pin 17 and is an open-drain output. There are three types of
interrupt events on the AD7147: a CDC conversion-complete
interrupt, a sensor touch interrupt, and a GPIO interrupt. Each
interrupt has enable and status registers. The conversioncomplete and sensor-touch (sensor-activation) interrupts can be
enabled on a per-conversion-stage basis. The status registers
indicate what type of interrupt triggered the INT pin. Status
registers are cleared, and the INT signal is reset high during a
read operation. The signal returns high as soon as the read
address has been set up.
SENSOR-TOUCH INTERRUPT
The sensor-touch interrupt mode is implemented when the host
processor requires an interrupt only when a sensor is contacted.
Configuring the AD7147 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user stops touching the sensor. The second
interrupt is required to alert the host processor that the user is
no longer contacting the sensor.
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
Figure 40 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 while operating in the
sensor-touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor. (Note that
the interrupt output remains low until the host processor reads
back the interrupt status registers located at Address 0x008 and
Address 0x009.)
The interrupt output is asserted when there is a change in the
interrupt status bits. This can indicate that a user is touching the
sensor(s) for the first time, the number of sensors being touched
has changed, or the user is no longer touching the sensor(s).
Reading the status bits in the interrupt status register shows the
current sensor activations.
FINGER ON SENSOR
FINGER OFF SENSOR
CONVERSION
STAGE
STAGE0
STAGE1
SERIAL
READBACK
CLEAR INTERRUPT.
CLEAR INTERRUPT.
Rev. E | Page 29 of 70
06663-037
INT OUTPUT
AD7147
CONVERSIONS
Data Sheet
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
INT
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A CDC CONVERSION-COMPLETE INTERRUPT.
THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR
STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 1
SERIAL READBACK REQUIREMENTS FOR STAGE0, STAGE5, AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.):
1READ THE STAGE0_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
2READ THE STAGE5_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
3READ THE STAGE9_COMPLETE_INT_STATUS (ADDRESS 0x00A) BIT
06663-038
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
Figure 41. Example of Configuring the Registers for Conversion-Complete Interrupt Setup
CONVERSIONS
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
INT
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A SENSOR-TOUCH INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED.
FOR EXAMPLE, THE SENSOR CONNECTED TO STAGE0 AND STAGE9 WERE CONTACTED, AND THE LOW THRESHOLD LEVELS WERE EXCEEDED, RESULTING
IN THE INTERRUPT BEING ASSERTED. THE STAGE6 INTERRUPT WAS NOT ASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTED TO
STAGE6.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE6, AND STAGE9 (x = 0, 6, 9):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 1
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
SERIAL READBACK REQUIREMENTS FOR STAGE0 AND STAGE9 (THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.):
1READ THE STAGE0_LOW_INT_STATUS (ADDRESS 0x008) BIT
2READ THE STAGE5_LOW_INT_STATUS (ADDRESS 0x008) BIT
Figure 42. Example of Configuring the Registers for Sensor-Touch Interrupt Setup
Rev. E | Page 30 of 70
06663-039
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE7, STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11):
STAGEx_LOW_INT_ENABLE (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_ENABLE (ADDRESS 0x006) = 0
STAGEx_COMPLETE_INT_ENABLE (ADDRESS 0x007) = 0
Data Sheet
AD7147
interrupt. This bit is set to 1 when the GPIO has triggered INT.
The bit is cleared upon reading the GPIO_INT_STATUS bit if the
condition that caused the interrupt is no longer present.
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 15 shows
how the settings of the GPIO_INPUT_CONFIG bits in the interrupt enable (STAGE_LOW_INT_ENABLE) register affect the
behavior of INT.
Figure 43 to Figure 46 show how the interrupt output is cleared
upon a read from the GPIO_INT_STATUS bit.
SERIAL
READBACK
SERIAL
READBACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
Rev. E | Page 31 of 70
06663-041
06663-040
INT
OUTPUT
AD7147
Data Sheet
1
SERIAL
READBACK
SERIAL
READBACK
GPIO
INPUT
GPIO
INPUT
INT
OUTPUT
INT
OUTPUT
GPIO
INPUT
06663-042
1READ
NOTES
1READ GPIO_INT_STATUS BIT TO RESET INT OUTPUT.
GPIO Pin
1
0
1
0
1
0
1
0
GPIO_INT_STATUS
0
1
1
0
0
1
1
0
INT
INT Behavior
1
0
0
1
1
0
0
1
Not triggered
Asserted while signal on GPIO pin is low
Pulses low at low-to-high GPIO transition
Not triggered
Pulses low at high-to-low GPIO transition
Not triggered
Asserted while signal on GPIO pin is high
Not triggered
Rev. E | Page 32 of 70
06663-043
INT
OUTPUT
INT
OUTPUT
Data Sheet
AD7147
OUTPUTS
ACSHIELD OUTPUT
The AD7147 measures capacitance between CINx and ground.
Any capacitance to ground on the signal path between the CINx
pins and the sensor is included in the AD7147 conversion result.
To eliminate stray capacitance to ground, the ACSHIELD signal should
be used to shield the connection between the sensor and CINx,
as shown in Figure 47. The plane around the sensors should also
be connected to ACSHIELD.
06663-044
GPIO_INPUT_CONFIG
00
01
10
11
V
KTC3875 CC
OR SIMILAR
AD7147
GPIO Configuration
Triggered on negative level (active low)
Triggered on positive edge (active high)
Triggered on negative edge (active low)
Triggered on positive level (active high)
GPIO
06663-045
SENSOR PCB
CIN0 AD7147
CIN1
CIN2
CIN3
ACSHIELD GND
GPIO Configuration
GPIO disabled
Input
Output low
Output high
Rev. E | Page 33 of 70
AD7147
Data Sheet
SERIAL INTERFACE
The AD7147 is available with an SPI-compatible interface. The
AD7147-1 is available with an I2C-compatible interface. Both
parts are the same, with the exception of the serial interface.
SPI INTERFACE
Writing Data
Data is written to the AD7147 in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7147 clocks the data into the register
addressed in the command word. If there is more than one
word of data to be clocked in, the AD7147 automatically increments the address pointer and clocks the subsequent data-word
into the next register.
14
1
13
1
12
0
11
0
LSB
9:0
Register address
10
R/W
CW
15
CW
14
CW
13
R/W
CW
12
CW
11
t2
SCLK
CW
10
REGISTER ADDRESS
CW
9
CW
8
t4
t1
CW
7
CW
6
CW
5
CW
4
16-BIT DATA
CW
3
CW
2
CW
1
CW
0
D15
D14
D13
D2
D1
D0
t5
6
10
11
12
13
14
15
16
17
18
19
30
31
32
t8
t3
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR THE CONTROL WORD AND 16 BITS FOR THE DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 0 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
Rev. E | Page 34 of 70
06663-046
CS
Data Sheet
AD7147
16-BIT COMMAND WORD
ENABLE WORD
SDI
CW
15
CW
14
CW
13
CW
12
CW
11
SCLK
CW
10
R/W
CW
9
CW
8
CW
7
CW
6
CW
5
CW
4
11
10
CW
3
12
CW
2
13
CW
1
14
CW
0
15
D15 D14
16
17
D1
18
31
32
D15 D14
33
D1
34
D0
47
D15
48
49
CS
06663-047
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 0 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
CW
15
CW
14
CW
13
R/W
CW
12
CW
11
t2
SCLK
CW
10
REGISTER ADDRESS
CW
9
CW
7
CW
8
t4
t1
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
t5
6
10
11
12
13
14
15
16
17
18
30
19
t3
31
32
t8
CS
t6
SDO
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
D15
D14
t7
D13
D2
D1
D0
XXX
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DONT CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 1 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB-JUSTIFIED REGISTER ADDRESS)
06663-048
Reading Data
A read transaction begins when the master writes the command
word to the AD7147 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7147 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of SCLK following the command word, as shown in Figure 51.
The AD7147 continues to clock out data on the SDO line if the
master continues to supply the clock signal on SCLK. The read
transaction finishes when the master takes CS high. If the AD7147
address pointer reaches its maximum value, the AD7147 repeatedly
clocks out data from the addressed register. The address pointer
does not wrap around.
Rev. E | Page 35 of 70
AD7147
Data Sheet
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
SDI
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
8
CW
7
SCLK
CW
6
10
CW
5
11
CW
4
12
CW
3
13
CW
2
14
CW
1
15
CW
0
16
17
18
D15
D14
31
32
33
34
47
48
49
CS
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
D1
D0
D15
D14
D1
D0
D15
NOTES
1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DONT CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:
CW [15:11] = 11100 (ENABLE WORD)
CW [10] = 1 (R/W)
CW [9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB-JUSTIFIED REGISTER ADDRESS)
06663-049
SDO
I2C-COMPATIBLE INTERFACE
The AD7147-1 supports the industry standard 2-wire I2C serial
interface protocol. The two wires associated with the I2C timing
are the SCLK and SDA inputs. The SDA is an I/O pin that allows
both register write and register readback operations. The AD7147-1
is always a slave device on the I2C serial interface bus.
It has a 7-bit device address, Address 0101 1XX. The lower two
bits are set by tying the ADD0 and ADD1 pins high or low. The
AD7147-1 responds when the master device sends its device
address over the bus. The AD7147-1 cannot initiate data transfers on the bus.
Table 18. AD7147-1 I2C Device Address
ADD1
0
0
1
1
I2C Address
0101 100
0101 101
0101 110
0101 111
ADD0
0
1
0
1
Data Transfer
2
Rev. E | Page 36 of 70
Data Sheet
AD7147
START
AD7147-1 DEVICE ADDRESS
SDA
DEV
A6
DEV
A5
DEV
A4
t1
DEV
A0
R/W ACK
A15
A14
A9
A8
ACK
A7
A6
A1
A0
t3
SCLK
1
10
11
16
17
18
19
20
25
26
t2
ACK
D15
D14
D9
D8
D7
D6
t4
27
28
29
34
D1
36
37
D0
ACK
t6
38
43
t8
t5
35
START
44
45
DEV
A6
DEV
A5
DEV
A4
t7
46
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X IS A DONT CARE BIT.
4. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X IS A DONT CARE BIT.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
06663-050
STOP
REGISTER DATA [D15:D8]
Figure 53. Example of I2C Timing for Single Register Write Operation
LSB
6
X
5
X
4
X
3
X
2
X
1
Register
Address
Bit 9
0
Register
Address
Bit 8
The following bit map shows the lower register address bytes.
MSB
7
Reg
Add
Bit 7
6
Reg
Add
Bit 6
5
Reg
Add
Bit 5
4
Reg
Add
Bit 4
3
Reg
Add
Bit 3
2
Reg
Add
Bit 2
1
Reg
Add
Bit 1
LSB
0
Reg
Add
Bit 0
The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth data byte contains
the eight LSBs of data to be written to the internal register.
The AD7147-1 address pointer register automatically increments
after each write. This allows the master to sequentially write to all
registers on the AD7147-1 in the same write transaction. However,
the address pointer register does not wrap around after the last
Rev. E | Page 37 of 70
AD7147
Data Sheet
START
AD7147-1 DEVICE ADDRESS
SDA
DEV
A6
DEV
A5
DEV
A4
t1
DEV
A0
R/W
ACK
A15
A14
A9
A8
A7
ACK
A6
A1
A0
ACK
t3
SCLK
1
10
11
16
17
18
19
20
25
26
27
t2
P
REGISTER DATA [D7:D0]
SR
DEV
A6
DEV
A5
DEV
A1
USING
REPEATED START
DEV
A0
ACK
R/W
D7
D6
t4
28
29
34
30
D1
DEV
A6
DEV
A5
35
36
DEV
A1
37
38
34
30
ACK
t6
44
39
R/W ACK
D7
D6
45
DEV
A5
DEV
A4
t7
46
D1
DEV
A6
P
D0
ACK
t5
t4
29
DEV
A0
D0
t5
t8
36
35
37
38
44
39
45
46
06663-051
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB Xs ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS [A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB Xs ARE DONT CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 54. Example of I2C Timing for Single Register Readback Operation
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
ACK
WRITE DATA
LOW BYTE [7:0]
ACK
ACK
REGISTER ADDR
LOW BYTE
WRITE DATA
HIGH BYTE [15:8]
ACK
REGISTER ADDR
[7:0]
ACK
SR
REGISTER ADDR
[15:8]
ACK
6-BIT DEVICE
W
ADDRESS
ACK
ACK
WRITE
P
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
ACK
REGISTER ADDR
HIGH BYTE
ACK
6-BIT DEVICE
W
ADDRESS
R
ACK
ACK
ACK P
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
ACK
S 6-BIT DEVICE
ADDRESS
ACK
READ DATA
LOW BYTE [7:0]
ACK P
06663-052
REGISTER ADDR
LOW BYTE
R
ACK
REGISTER ADDR
HIGH BYTE
ACK
6-BIT DEVICE
W
ADDRESS
ACK
ACK
VDRIVE INPUT
The supply voltage for the pins (SDO, SDI, SCLK, SDA, CS,
INT, and GPIO) associated with both the I2C and SPI serial
interfaces is supplied from the VDRIVE pin and is separate from the
main VCC supply.
Rev. E | Page 38 of 70
Data Sheet
AD7147
Symbol
D1
D2 = D3 = D4
D5
Min
0.1
0
Typ
Max
1.0
Unit
mm
mm
mm
The distance is dependent on the application and the position of the switches relative to each other and with respect to the users finger position and handling.
Adjacent sensors with no space between them are implemented differentially.
2
The 1.0 mm specification is intended to prevent direct sensor board contact with any conductive material. This specification, however, does not guarantee an absence
of EMI coupling from the controller board to the sensors. To avoid potential EMI-coupling issues, place a grounded metal shield between the capacitive sensor board
and the main controller board, as shown in Figure 58.
METAL OBJECT
CAPACITIVE SENSOR
PRINTED CIRCUIT
8-WAY
SWITCH
06663-055
D4
SLIDER
BUTTONS
D3
D2
06663-053
D1
06663-054
D5
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. To avoid shorting, provide a clearance of at least 0.25 mm between the thermal pad and the inner
edges of the land pattern on the PCB.
Rev. E | Page 39 of 70
AD7147
Data Sheet
POWER-UP SEQUENCE
To power up the AD7147, use the following sequence when
initially developing the AD7147 and microprocessor serial
interface:
1.
2.
Note that the Bank 2 register values are unique for each
application. Register values come from characterization of
the sensor in the application.
3.
4.
5.
POWER
HOST
SERIAL
INTERFACE
10 11
10
11
10
AD7147 INT
FIRST CONVERSION SEQUENCE
SECOND CONVERSION
SEQUENCE
Rev. E | Page 40 of 70
THIRD CONVERSION
SEQUENCE
11
06663-056
CONVERSION
STAGE
Data Sheet
AD7147
19
CIN0
CIN11
SENSOR PCB
SDO
17
16
SS
15
SCK
14
MOSI
13
MISO
VHOST
100nF
PLANE AROUND SENSORS CONNECTED TO AC SHIELD
2.2k
0.1F
1F TO 10F
(OPTIONAL)
1.8V
06663-057
20
CIN1
21
CIN2
22
CIN3
23
SDI
CIN12
BUTTON
SCLK
CIN10
VDRIVE
CIN9
18
12
CS
AD7147
VCC
BUTTON
CIN8
11
GND
INT
BIAS
SCROLL
WHEEL
CIN7
10
BUTTON
GPIO
ACSHIELD
BUTTON
VDRIVE
CIN6
CIN4
CIN5
24
VDRIVE
19
SDA
17
2.2k
16
15
SCK
14
13
SDO
12
VCC
VDRIVE
ADD0
11
CIN11
18
100nF
0.1F
Rev. E | Page 41 of 70
06663-058
20
CIN1
21
CIN2
22
23
CIN3
CIN0
SCLK
CIN10
2-WAY
SWITCH
AD7147-1
CIN9
CIN12
ADD1
GND
CIN8
10
BUTTON
INT
BIAS
CIN7
ACSHIELD
2.2k
GPIO
BUTTON
VDRIVE
2.2k
CIN6
SLIDER
BUTTON
CIN4
CIN5
24
VDRIVE
AD7147
Data Sheet
REGISTER MAP
The AD7147 address space is divided into three register banks,
referred to as Bank 1, Bank 2, and Bank 3. Figure 62 illustrates
the division of these banks.
Bank 1 registers contain control registers, CDC conversion
control registers, interrupt enable registers, interrupt status
registers, CDC 16-bit conversion data registers, device ID
registers, and proximity status registers.
Bank 2 registers contain the configuration registers used to
configure the individual CINx inputs for each conversion stage.
Initialize the Bank 2 configuration registers immediately after
power-up to obtain valid CDC conversion result data.
BANK 2 REGISTERS
ADDR 0x080
SETUP CONTROL
(1 REGISTER)
ADDR 0x088
ADDR 0x001
INTERRUPT ENABLE
(3 REGISTERS)
ADDR 0x0A0
ADDR 0x008
ADDR 0x017
96 REGISTERS
26 REGISTERS
ADDR 0x098
ADDR 0x088
STAGE2 CONFIGURATION
(8 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
ADDR 0x0B0
STAGE6 CONFIGURATION
(8 REGISTERS)
DEVICE ID REGISTER
(1 REGISTER)
ADDR 0x098
STAGE3 CONFIGURATION
(8 REGISTERS)
ADDR 0x0A8
ADDR 0x0B8
ADDR 0x090
STAGE7 CONFIGURATION
(8 REGISTERS)
ADDR 0x018
STAGE5 RESULTS
(36 REGISTERS)
ADDR 0x0B0
ADDR 0x0B8
STAGE6 RESULTS
(36 REGISTERS)
STAGE7 RESULTS
(36 REGISTERS)
STAGE8 RESULTS
(36 REGISTERS)
STAGE9 RESULTS
(36 REGISTERS)
STAGE9 CONFIGURATION
(8 REGISTERS)
ADDR 0x0D0
STAGE10 RESULTS
(36 REGISTERS)
STAGE10 CONFIGURATION
(8 REGISTERS)
INVALID DO NOT ACCESS
STAGE4 RESULTS
(36 REGISTERS)
ADDR 0x0C8
ADDR 0x0C8
ADDR 0x0D0
ADDR 0x043
STAGE2 RESULTS
(36 REGISTERS)
ADDR 0x0A8
STAGE8 CONFIGURATION
(8 REGISTERS)
STAGE1 RESULTS
(36 REGISTERS)
ADDR 0x0C0
ADDR 0x0C0
ADDR 0x042
STAGE0 RESULTS
(36 REGISTERS)
STAGE3 RESULTS
(36 REGISTERS)
ADDR 0x0A0
432 REGISTERS
ADDR 0x090
ADDR 0x005
ADDR 0x00B
BANK 3 REGISTERS
ADDR 0x0E0
STAGE0 CONFIGURATION
(8 REGISTERS)
STAGE1 CONFIGURATION
(8 REGISTERS)
INTERRUPT STATUS
(3 REGISTERS)
ADDR 0x0D8
ADDR 0x28F
STAGE11 CONFIGURATION
(8 REGISTERS)
ADDR 0x7F0
Rev. E | Page 42 of 70
STAGE11 RESULTS
(36 REGISTERS)
06663-059
BANK 1 REGISTERS
ADDR 0x000
Data Sheet
AD7147
Data Bit
[1:0]
Default
Value
0
Type
R/W
Name
POWER_MODE
[3:2]
R/W
LP_CONV_DELAY
[7:4]
R/W
SEQUENCE_STAGE_NUM
[9:8]
R/W
DECIMATION
[10]
R/W
SW_RESET
[11]
R/W
INT_POL
[12]
R/W
EXT_SOURCE
[13]
[15:14]
0
0
R/W
Unused
CDC_BIAS
Rev. E | Page 43 of 70
Description
Operating modes
00 = full power mode (normal operation, CDC
conversions approximately every 36 ms)
01 = full shutdown mode (no CDC conversions)
10 = low power mode (automatic wake-up operation)
11 = full shutdown mode (no CDC conversions)
Low power mode conversion delay
00 = 200 ms
01 = 400 ms
10 = 600 ms
11 = 800 ms
Number of stages in sequence (N + 1)
0000 = 1 conversion stage in sequence
0001 = 2 conversion stages in sequence
AD7147
Data Sheet
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_CAL_EN
[1]
R/W
STAGE1_CAL_EN
[2]
R/W
STAGE2_CAL_EN
[3]
R/W
STAGE3_CAL_EN
[4]
R/W
STAGE4_CAL_EN
[5]
R/W
STAGE5_CAL_EN
[6]
R/W
STAGE6_CAL_EN
[7]
R/W
STAGE7_CAL_EN
[8]
R/W
STAGE8_CAL_EN
[9]
R/W
STAGE9_CAL_EN
[10]
R/W
STAGE10_CAL_EN
[11]
R/W
STAGE11_CAL_EN
[13:12]
R/W
AVG_FP_SKIP
[15:14]
R/W
AVG_LP_SKIP
Rev. E | Page 44 of 70
Description
STAGE0 calibration enable
0 = disable
1 = enable
STAGE1 calibration enable
0 = disable
1 = enable
STAGE2 calibration enable
0 = disable
1 = enable
STAGE3 calibration enable
0 = disable
1 = enable
STAGE4 calibration enable
0 = disable
1 = enable
STAGE5 calibration enable
0 = disable
1 = enable
STAGE6 calibration enable
0 = disable
1 = enable
STAGE7 calibration enable
0 = disable
1 = enable
STAGE8 calibration enable
0 = disable
1 = enable
STAGE9 calibration enable
0 = disable
1 = enable
STAGE10 calibration enable
0 = disable
1 = enable
STAGE11 calibration enable
0 = disable
1 = enable
Full power mode skip control
00 = skip 3 samples
01 = skip 7 samples
10 = skip 15 samples
11 = skip 31 samples
Low power mode skip control
00 = use all samples
01 = skip one sample
10 = skip two samples
11 = skip three samples
Data Sheet
AD7147
Data Bit
[3:0]
Default
Value
0
Type
R/W
Name
FF_SKIP_CNT
[7:4]
R/W
FP_PROXIMITY_CNT
[11:8]
R/W
LP_PROXIMITY_CNT
[13:12]
R/W
PWR_DOWN_TIMEOUT
[14]
R/W
FORCED_CAL
[15]
R/W
CONV_RESET
Description
Fast filter skip control (N + 1)
0000 = no sequence of results is skipped
0001 = one sequence of results is skipped for every one
allowed into fast FIFO
0010 = two sequences of results are skipped for every
one allowed into fast FIFO
1011 = maximum value = 12 sequences of results are
skipped for every one allowed into fast FIFO
Calibration disable period in full power mode =
FP_PROXIMITY_CNT 16 time for one conversion
sequence in full power mode
Calibration disable period in low power mode =
LP_PROXIMITY_CNT 4 time for one conversion
sequence in low power mode
Full power to low power mode timeout control
00 = 1.25 (FP_PROXIMITY_CNT)
01 = 1.50 (FP_PROXIMITY_CNT)
10 = 1.75 (FP_PROXIMITY_CNT)
11 = 2.00 (FP_PROXIMITY_CNT)
Forced calibration control
0 = normal operation
1 = forces all conversion stages to recalibrate
Conversion reset control (self-clearing)
0 = normal operation
1 = resets the conversion sequence to STAGE0
Data Bit
[7:0]
Default
Value
64
Type
R/W
Name
PROXIMITY_RECAL_LVL
[13:8]
R/W
PROXIMITY_DETECTION_RATE
[15:14]
R/W
SLOW_FILTER_UPDATE_LVL
Description
Proximity recalibration level; the value is multiplied by
16 to determine actual recalibration level
Proximity detection rate; the value is multiplied by 16 to
determine actual detection rate
Slow filter update level
Name
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
Description
Full power mode proximity recalibration time control
Low power mode proximity recalibration time control
Data Bit
[9:0]
[15:10]
Default
Value
3FF
3F
Type
R/W
R/W
Rev. E | Page 45 of 70
AD7147
Data Sheet
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_LOW_INT_ENABLE
[1]
R/W
STAGE1_LOW_INT_ENABLE
[2]
R/W
STAGE2_LOW_INT_ENABLE
[3]
R/W
STAGE3_LOW_INT_ENABLE
[4]
R/W
STAGE4_LOW_INT_ENABLE
[5]
R/W
STAGE5_LOW_INT_ENABLE
[6]
R/W
STAGE6_LOW_INT_ENABLE
[7]
R/W
STAGE7_LOW_INT_ENABLE
[8]
R/W
STAGE8_LOW_INT_ENABLE
[9]
R/W
STAGE9_LOW_INT_ENABLE
[10]
R/W
STAGE10_LOW_INT_ENABLE
[11]
R/W
STAGE11_LOW_INT_ENABLE
[13:12]
R/W
GPIO_SETUP
[15:14]
R/W
GPIO_INPUT_CONFIG
Rev. E | Page 46 of 70
Description
STAGE0 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 low threshold is exceeded
STAGE1 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 low threshold is exceeded
STAGE2 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 low threshold is exceeded
STAGE3 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 low threshold is exceeded
STAGE4 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 low threshold is exceeded
STAGE5 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 low threshold is exceeded
STAGE6 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 low threshold is exceeded
STAGE7 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 low threshold is exceeded
STAGE8 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE8 low threshold is exceeded
STAGE9 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE9 low threshold is exceeded
STAGE10 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 low threshold is exceeded
STAGE11 low interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE11 low threshold is exceeded
GPIO setup
00 = disable GPIO pin
01 = configure GPIO as an input
10 = configure GPIO as an active low output
11 = configure GPIO as an active high output
GPIO input configuration
00 = triggered on negative level
01 = triggered on positive edge
10 = triggered on negative edge
11 = triggered on positive level
Data Sheet
AD7147
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_HIGH_INT_ENABLE
[1]
R/W
STAGE1_HIGH_INT_ENABLE
[2]
R/W
STAGE2_HIGH_INT_ENABLE
[3]
R/W
STAGE3_HIGH_INT_ENABLE
[4]
R/W
STAGE4_HIGH_INT_ENABLE
[5]
R/W
STAGE5_HIGH_INT_ENABLE
[6]
R/W
STAGE6_HIGH_INT_ENABLE
[7]
R/W
STAGE7_HIGH_INT_ENABLE
[8]
R/W
STAGE8_HIGH_INT_ENABLE
[9]
R/W
STAGE9_HIGH_INT_ENABLE
[10]
R/W
STAGE10_HIGH_INT_ENABLE
[11]
R/W
STAGE11_HIGH_INT_ENABLE
[15:12]
Unused
Rev. E | Page 47 of 70
Description
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE1 high threshold is exceeded
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE2 high threshold is exceeded
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE3 high threshold is exceeded
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE4 high threshold is exceeded
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE5 high threshold is exceeded
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE6 high threshold is exceeded
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE7 high threshold is exceeded
STAGE8 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE8 high threshold is exceeded
STAGE9 sensor high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE9 high threshold is exceeded
STAGE10 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE10 high threshold is exceeded
STAGE11 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE11 high threshold is exceeded
Set to 0
AD7147
Data Sheet
Data Bit
[0]
Default
Value
0
Type
R/W
Name
STAGE0_COMPLETE_INT_ENABLE
[1]
R/W
STAGE1_COMPLETE_INT_ENABLE
[2]
R/W
STAGE2_COMPLETE_INT_ENABLE
[3]
R/W
STAGE3_COMPLETE_INT_ENABLE
[4]
R/W
STAGE4_COMPLETE_INT_ENABLE
[5]
R/W
STAGE5_COMPLETE_INT_ENABLE
[6]
R/W
STAGE6_COMPLETE_INT_ENABLE
[7]
R/W
STAGE7_COMPLETE_INT_ENABLE
[8]
R/W
STAGE8_COMPLETE_INT_ENABLE
[9]
R/W
STAGE9_COMPLETE_INT_ENABLE
[10]
R/W
STAGE10_COMPLETE_INT_ENABLE
[11]
R/W
STAGE11_COMPLETE_INT_ENABLE
[12]
R/W
GPIO_INT_ENABLE
[15:13]
Unused
Rev. E | Page 48 of 70
Description
STAGE0 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE0 conversion
STAGE1 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
STAGE2 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
STAGE3 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
STAGE4 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
STAGE5 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
STAGE6 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
STAGE7 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
STAGE8 conversion complete interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE8 conversion
STAGE9 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE9 conversion
STAGE10 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE10 conversion
STAGE11 conversion interrupt control
0 = interrupt source disabled
1 = INT asserted at completion of STAGE11 conversion
Interrupt control when GPIO input pin changes level
0 = disabled
1 = enabled
Set to 0
Data Sheet
AD7147
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_LOW_INT_STATUS
[1]
STAGE1_LOW_INT_STATUS
[2]
STAGE2_LOW_INT_STATUS
[3]
STAGE3_LOW_INT_STATUS
[4]
STAGE4_LOW_INT_STATUS
[5]
STAGE5_LOW_INT_STATUS
[6]
STAGE6_LOW_INT_STATUS
[7]
STAGE7_LOW_INT_STATUS
[8]
STAGE8_LOW_INT_STATUS
[9]
STAGE9_LOW_INT_STATUS
[10]
STAGE10_LOW_INT_STATUS
[11]
STAGE11_LOW_INT_STATUS
[15:12]
1
Unused
Rev. E | Page 49 of 70
Description
STAGE0 CDC conversion low limit interrupt result
1 = indicates STAGE0_LOW_THRESHOLD value was
exceeded
STAGE1 CDC conversion low limit interrupt result
1 = indicates STAGE1_LOW_THRESHOLD value was
exceeded
STAGE2 CDC conversion low limit interrupt result
1 = indicates STAGE2_LOW_THRESHOLD value was
exceeded
STAGE3 CDC conversion low limit interrupt result
1 = indicates STAGE3_LOW_THRESHOLD value was
exceeded
STAGE4 CDC conversion low limit interrupt result
1 = indicates STAGE4_LOW_THRESHOLD value was
exceeded
STAGE5 CDC conversion low limit interrupt result
1 = indicates STAGE5_LOW_THRESHOLD value was
exceeded
STAGE6 CDC conversion low limit interrupt result
1 = indicates STAGE6_LOW_THRESHOLD value was
exceeded
STAGE7 CDC conversion low limit interrupt result
1 = indicates STAGE7_LOW_THRESHOLD value was
exceeded
STAGE8 CDC conversion low limit interrupt result
1 = indicates STAGE8_LOW_THRESHOLD value was
exceeded
STAGE9 CDC conversion low limit interrupt result
1 = indicates STAGE9_LOW_THRESHOLD value was
exceeded
STAGE10 CDC Conversion Low Limit Interrupt result
1 = indicates STAGE10_LOW_THRESHOLD value was
exceeded
STAGE11 CDC conversion low limit interrupt result
1 = indicates STAGE11_LOW_THRESHOLD value was
exceeded
Set to 0
AD7147
Data Sheet
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_HIGH_INT_STATUS
[1]
STAGE1_HIGH_INT_STATUS
[2]
STAGE2_HIGH_INT_STATUS
[3]
STAGE3_HIGH_INT_STATUS
[4]
STAGE4_HIGH_INT_STATUS
[5]
STAGE5_HIGH_INT_STATUS
[6]
STAGE6_HIGH_INT_STATUS
[7]
STAGE7_HIGH_INT_STATUS
[8]
STAGE8_HIGH_INT_STATUS
[9]
STAGE9_HIGH_INT_STATUS
[10]
STAGE10_HIGH_INT_STATUS
[11]
STAGE11_HIGH_INT_STATUS
[15:12]
1
Unused
Rev. E | Page 50 of 70
Description
STAGE0 CDC conversion high limit interrupt result
1 = indicates STAGE0_HIGH_THRESHOLD value was
exceeded
STAGE1 CDC conversion high limit interrupt result
1 = indicates STAGE1_HIGH_THRESHOLD value was
exceeded
Stage2 CDC conversion high limit interrupt result
1 = indicates STAGE2_HIGH_THRESHOLD value was
exceeded
STAGE3 CDC conversion high limit interrupt result
1 = indicates STAGE3_HIGH_THRESHOLD value was
exceeded
STAGE4 CDC conversion high limit interrupt result
1 = indicates STAGE4_HIGH_THRESHOLD value was
exceeded
STAGE5 CDC conversion high limit interrupt result
1 = indicates STAGE5_HIGH_THRESHOLD value was
exceeded
STAGE6 CDC conversion high limit interrupt result
1 = indicates STAGE6_HIGH_THRESHOLD value was
exceeded
STAGE7 CDC conversion high limit interrupt result
1 = indicates STAGE7_HIGH_THRESHOLD value was
exceeded
STAGE8 CDC conversion high limit interrupt result
1 = indicates STAGE8_HIGH_THRESHOLD value was
exceeded
STAGE9 CDC conversion high limit interrupt result
1 = indicates STAGE9_HIGH_THRESHOLD value was
exceeded
STAGE10 CDC conversion high limit interrupt result
1 = indicates STAGE10_HIGH_THRESHOLD value was
exceeded
STAGE11 CDC conversion high limit interrupt result
1 = indicates STAGE11_HIGH_THRESHOLD value was
exceeded
Set to 0
Data Sheet
AD7147
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_COMPLETE_INT_STATUS
[1]
STAGE1_COMPLETE_INT_STATUS
[2]
STAGE2_COMPLETE_INT_STATUS
[3]
STAGE3_COMPLETE_INT_STATUS
[4]
STAGE4_COMPLETE_INT_STATUS
[5]
STAGE5_COMPLETE_INT_STATUS
[6]
STAGE6_COMPLETE_INT_STATUS
[7]
STAGE7_COMPLETE_INT_STATUS
[8]
STAGE8_COMPLETE_INT_STATUS
[9]
STAGE9_COMPLETE_INT_STATUS
[10]
STAGE10_COMPLETE_INT_STATUS
[11]
STAGE11_COMPLETE_INT_STATUS
[12]
GPIO_INT_STATUS
[15:13]
1
Unused
Description
STAGE0 conversion complete register interrupt status
1 = indicates STAGE0 conversion completed
STAGE1 conversion complete register interrupt status
1 = indicates STAGE1 conversion completed
STAGE2 conversion complete register interrupt status
1 = indicates STAGE2 conversion completed
STAGE3 conversion complete register interrupt status
1 = indicates STAGE3 conversion completed
STAGE4 conversion complete register interrupt status
1 = indicates STAGE4 conversion completed
STAGE5 conversion complete register interrupt status
1 = indicates STAGE5 conversion completed
STAGE6 conversion complete register interrupt status
1 = indicates STAGE6 conversion completed
STAGE7 conversion complete register interrupt status
1 = indicates STAGE7 conversion completed
STAGE8 conversion complete register interrupt status
1 = indicates STAGE8 conversion completed
STAGE9 conversion complete register interrupt status
1 = indicates STAGE9 conversion completed
STAGE10 conversion complete register interrupt status
1 = indicates STAGE10 conversion completed
STAGE11 conversion complete register interrupt status
1 = indicates STAGE11 conversion completed
GPIO input pin status
1 = indicates level on GPIO pin has changed
Set to 0
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
Type
R
R
R
R
R
R
R
R
R
R
R
R
Name
CDC_RESULT_S0
CDC_RESULT_S1
CDC_RESULT_S2
CDC_RESULT_S3
CDC_RESULT_S4
CDC_RESULT_S5
CDC_RESULT_S6
CDC_RESULT_S7
CDC_RESULT_S8
CDC_RESULT_S9
CDC_RESULT_S10
CDC_RESULT_S11
Rev. E | Page 51 of 70
Description
STAGE0 CDC 16-bit conversion data
STAGE1 CDC 16-bit conversion data
STAGE2 CDC 16-bit conversion data
STAGE3 CDC 16-bit conversion data
STAGE4 CDC 16-bit conversion data
STAGE5 CDC 16-bit conversion data
STAGE6 CDC 16-bit conversion data
STAGE7 CDC 16-bit conversion data
STAGE8 CDC 16-bit conversion data
STAGE9 CDC 16-bit conversion data
STAGE10 CDC 16-bit conversion data
STAGE11 CDC 16-bit conversion data
AD7147
Data Sheet
Data Bit
[3:0]
[15:4]
Default
Value
0
147
Type
R
R
Name
REVISION_CODE
DEVID
Description
Revision code
Device ID = 0001 0100 0111
Description
STAGE0 proximity status register
1 = indicates proximity has been detected on STAGE0
STAGE1 proximity status register
1 = indicates proximity has been detected on STAGE1
STAGE2 proximity status register
1 = indicates proximity has been detected on STAGE2
STAGE3 proximity status register
1 = indicates proximity has been detected on STAGE3
STAGE4 proximity status register
1 = indicates proximity has been detected on STAGE4
STAGE5 proximity status register
1 = indicates proximity has been detected on STAGE5
STAGE6 proximity status register
1 = indicates proximity has been detected on STAGE6
STAGE7 proximity status register
1 = indicates proximity has been detected on STAGE7
STAGE8 proximity status register
1 = indicates proximity has been detected on STAGE8
STAGE9 proximity status register
1 = indicates proximity has been detected on STAGE9
STAGE10 proximity status register
1 = indicates proximity has been detected on STAGE10
STAGE11 proximity status register
1 = indicates proximity has been detected on STAGE11
Set to 0
Data Bit
[0]
Default
Value
0
Type
R
Name
STAGE0_PROXIMITY_STATUS
[1]
STAGE1_PROXIMITY_STATUS
[2]
STAGE2_PROXIMITY_STATUS
[3]
STAGE3_PROXIMITY_STATUS
[4]
STAGE4_PROXIMITY_STATUS
[5]
STAGE5_PROXIMITY_STATUS
[6]
STAGE6_PROXIMITY_STATUS
[7]
STAGE7_PROXIMITY_STATUS
[8]
STAGE8_PROXIMITY_STATUS
[9]
STAGE9_PROXIMITY_STATUS
[10]
STAGE10_PROXIMITY_STATUS
[11]
STAGE11_PROXIMITY_STATUS
[15:12]
Unused
Rev. E | Page 52 of 70
Data Sheet
AD7147
BANK 2 REGISTERS
All address values are expressed in hexadecimal.
Table 34. STAGEx_CONNECTION[6:0] Register Description (x = 0 to 11)
Data Bit
[1:0]
Default
Value
X
Type
R/W
Name
CIN0_CONNECTION_SETUP
[3:2]
R/W
CIN1_CONNECTION_SETUP
[5:4]
R/W
CIN2_CONNECTION_SETUP
[7:6]
R/W
CIN3_CONNECTION_SETUP
[9:8]
R/W
CIN4_CONNECTION_SETUP
[11:10]
R/W
CIN5_CONNECTION_SETUP
[13:12]
R/W
CIN6_CONNECTION_SETUP
[15:14]
Unused
Description
CIN0 connection setup
00 = CIN0 not connected to CDC inputs
01 = CIN0 connected to CDC negative input
10 = CIN0 connected to CDC positive input
11 = CIN0 connected to BIAS (connect unused CINx inputs)
CIN1 connection setup
00 = CIN1 not connected to CDC inputs
01 = CIN1 connected to CDC negative input
10 = CIN1 connected to CDC positive input
11 = CIN1 connected to BIAS (connect unused CINx inputs)
CIN2 connection setup
00 = CIN2 not connected to CDC inputs
01 = CIN2 connected to CDC negative input
10 = CIN2 connected to CDC positive input
11 = CIN2 connected to BIAS (connect unused CINx inputs)
CIN3 connection setup
00 = CIN3 not connected to CDC inputs
01 = CIN3 connected to CDC negative input
10 = CIN3 connected to CDC positive input
11 = CIN3 connected to BIAS (connect unused CINx inputs)
CIN4 connection setup
00 = CIN4 not connected to CDC inputs
01 = CIN4 connected to CDC negative input
10 = CIN4 connected to CDC positive input
11 = CIN4 connected to BIAS (connect unused CINx inputs)
CIN5 connection setup
00 = CIN5 not connected to CDC inputs
01 = CIN5 connected to CDC negative input
10 = CIN5 connected to CDC positive input
11 = CIN5 connected to BIAS (connect unused CINx inputs)
CIN6 connection setup
00 = CIN6 not connected to CDC inputs
01 = CIN6 connected to CDC negative input
10 = CIN6 connected to CDC positive input
11 = CIN6 connected to BIAS (connect unused CINx inputs)
Set to 0
Rev. E | Page 53 of 70
AD7147
Data Sheet
Default
Value
X
Type
R/W
Name
CIN7_CONNECTION_SETUP
[3:2]
R/W
CIN8_CONNECTION_SETUP
[5:4]
R/W
CIN9_CONNECTION_SETUP
[7:6]
R/W
CIN10_CONNECTION_SETUP
[9:8]
R/W
CIN11_CONNECTION_SETUP
[11:10]
R/W
CIN12_CONNECTION_SETUP
[13:12]
R/W
SE_CONNECTION_SETUP
[14]
R/W
NEG_AFE_OFFSET_DISABLE
[15]
R/W
POS_AFE_OFFSET_DISABLE
Description
CIN7 connection setup
00 = CIN7 not connected to CDC inputs
01 = CIN7 connected to CDC negative input
10 = CIN7 connected to CDC positive input
11 = CIN7 connected to BIAS (connect unused CINx inputs)
CIN8 connection setup
00 = CIN8 not connected to CDC inputs
01 = CIN8 connected to CDC negative input
10 = CIN8 connected to CDC positive input
11 = CIN8 connected to BIAS (connect unused CINx inputs)
CIN9 connection setup
00 = CIN9 not connected to CDC inputs
01 = CIN9 connected to CDC negative input
10 = CIN9 connected to CDC positive input
11 = CIN9 connected to BIAS (connect unused CINx inputs)
CIN10 connection setup
00 = CIN10 not connected to CDC inputs
01 = CIN10 connected to CDC negative input
10 = CIN10 connected to CDC positive input
11 = CIN10 connected to BIAS (connect unused CINx inputs)
CIN11 connection setup
00 = CIN11 not connected to CDC inputs
01 = CIN11 connected to CDC negative input
10 = CIN11 connected to CDC positive input
11 = CIN11 connected to BIAS (connect unused CINx inputs)
CIN12 connection setup
00 = CIN12 not connected to CDC inputs
01 = CIN12 connected to CDC negative input
10 = CIN12 connected to CDC positive input
11 = CIN12 connected to BIAS (connect unused CINx inputs)
Single-ended measurement connection setup
00 = do not use
01 = use when one CINx connected to CDC positive input,
single-ended measurements only
10 = use when one CINx connected to CDC negative input,
single-ended measurements only
11 = differential connection to CDC
Negative AFE offset enable control
0 = enable
1 = disable
Positive AFE offset enable control
0 = enable
1 = disable
Rev. E | Page 54 of 70
Data Sheet
AD7147
Default
Value
X
Type
R/W
Name
NEG_AFE_OFFSET
[6]
[7]
X
X
R/W
Unused
NEG_AFE_OFFSET_SWAP
[13:8]
R/W
POS_AFE_OFFSET
[14]
[15]
X
X
R/W
Unused
POS_AFE_OFFSET_SWAP
Description
Negative AFE offset setting (20 pF range)
1 LSB value = 0.32 pF of offset
Set to 0
Negative AFE offset swap control
0 = NEG_AFE_OFFSET applied to CDC negative input
1 = NEG_AFE_OFFSET applied to CDC positive input
Positive AFE offset setting (20 pF range)
1 LSB value = 0.32 pF of offset
Set to 0
Positive AFE offset swap control
0 = POS_AFE_OFFSET applied to CDC positive input
1 = POS_AFE_OFFSET applied to CDC negative input
Default
Value
X
Type
R/W
Name
NEG_THRESHOLD_SENSITIVITY
[6:4]
R/W
NEG_PEAK_DETECT
[7]
[11:8]
X
X
R/W
R/W
Unused
POS_THRESHOLD_SENSITIVITY
[14:12]
R/W
POS_PEAK_DETECT
[15]
R/W
Unused
Description
Negative threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Negative peak detect setting
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Set to 0
Positive threshold sensitivity control
0000 = 25%, 0001 = 29.73%, 0010 = 34.40%, 0011 = 39.08%
0100 = 43.79%, 0101 = 48.47%, 0110 = 53.15%
0111 = 57.83%, 1000 = 62.51%, 1001 = 67.22%
1010 = 71.90%, 1011 = 76.58%, 1100 = 81.28%
1101 = 85.96%, 1110 = 90.64%, 1111 = 95.32%
Positive peak detect setting
000 = 40% level, 001 = 50% level, 010 = 60% level
011 = 70% level, 100 = 80% level, 101 = 90% level
Set to 0
Rev. E | Page 55 of 70
AD7147
Data Sheet
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
STAGE0_CONNECTION[6:0]
STAGE0_CONNECTION[12:7]
STAGE0_AFE_OFFSET
STAGE0_SENSITIVITY
STAGE0_OFFSET_LOW
STAGE0_OFFSET_HIGH
STAGE0_OFFSET_HIGH_CLAMP
STAGE0_OFFSET_LOW_CLAMP
STAGE1_CONNECTION[6:0]
STAGE1_CONNECTION[12:7]
STAGE1_AFE_OFFSET
STAGE1_SENSITIVITY
STAGE1_OFFSET_LOW
STAGE1_OFFSET_HIGH
STAGE1_OFFSET_HIGH_CLAMP
STAGE1_OFFSET_LOW_CLAMP
STAGE2_CONNECTION[6:0]
STAGE2_CONNECTION[12:7]
STAGE2_AFE_OFFSET
STAGE2_SENSITIVITY
STAGE2_OFFSET_LOW
STAGE2_OFFSET_HIGH
STAGE2_OFFSET_HIGH_CLAMP
STAGE2_OFFSET_LOW_CLAMP
STAGE3_CONNECTION[6:0]
STAGE3_CONNECTION[12:7]
STAGE3_AFE_OFFSET
STAGE3_SENSITIVITY
STAGE3_OFFSET_LOW
STAGE3_OFFSET_HIGH
STAGE3_OFFSET_HIGH_CLAMP
STAGE3_OFFSET_LOW_CLAMP
STAGE4_CONNECTION[6:0]
STAGE4_CONNECTION[12:7]
STAGE4_AFE_OFFSET
STAGE4_SENSITIVITY
STAGE4_OFFSET_LOW
STAGE4_OFFSET_HIGH
STAGE4_OFFSET_HIGH_CLAMP
STAGE4_OFFSET_LOW_CLAMP
STAGE5_CONNECTION[6:0]
STAGE5_CONNECTION[12:7]
STAGE5_AFE_OFFSET
STAGE5_SENSITIVITY
STAGE5_OFFSET_LOW
STAGE5_OFFSET_HIGH
STAGE5_OFFSET_HIGH_CLAMP
STAGE5_OFFSET_LOW_CLAMP
Rev. E | Page 56 of 70
Description
STAGE0 CIN[6:0] connection setup (see Table 34)
STAGE0 CIN[12:7] connection setup (see Table 35)
STAGE0 AFE offset control (see Table 36)
STAGE0 sensitivity control (see Table 37)
STAGE0 initial offset low value
STAGE0 initial offset high value
STAGE0 offset high clamp value
STAGE0 offset low clamp value
STAGE1 CIN[6:0] connection setup (see Table 34)
STAGE1 CIN[12:7] connection setup (see Table 35)
STAGE1 AFE offset control (see Table 36)
STAGE1 sensitivity control (see Table 37)
STAGE1 initial offset low value
STAGE1 initial offset high value
STAGE1 offset high clamp value
STAGE1 offset low clamp value
STAGE2 CIN[6:0] connection setup (see Table 34)
STAGE2 CIN[12:7] connection setup (see Table 35)
STAGE2 AFE offset control (see Table 36)
STAGE2 sensitivity control (see Table 37)
STAGE2 initial offset low value
STAGE2 initial offset high value
STAGE2 offset high clamp value
STAGE2 offset low clamp value
STAGE3 CIN[6:0] connection setup (see Table 34)
STAGE3 CIN[12:7] connection setup (see Table 35)
STAGE3 AFE offset control (see Table 36)
STAGE3 sensitivity control (see Table 37)
STAGE3 initial offset low value
STAGE3 initial offset high value
STAGE3 offset high clamp value
STAGE3 offset low clamp value
STAGE4 CIN[6:0] connection setup (see Table 34)
STAGE4 CIN[12:7] connection setup (see Table 35)
STAGE4 AFE offset control (see Table 36)
STAGE4 sensitivity control (see Table 37)
STAGE4 initial offset low value
STAGE4 initial offset high value
STAGE4 offset high clamp value
STAGE4 offset low clamp value
STAGE5 CIN[6:0] connection setup (see Table 34)
STAGE5 CIN[12:7] connection setup (see Table 35)
STAGE5 AFE offset control (see Table 36)
STAGE5 sensitivity control (see Table 37)
STAGE5 initial offset low value
STAGE5 initial offset high value
STAGE5 offset high clamp value
STAGE5 offset low clamp value
Data Sheet
Address
0x0B0
0x0B1
0x0B2
0x0B3
0x0B4
0x0B5
0x0B6
0x0B7
0x0B8
0x0B9
0x0BA
0x0BB
0x0BC
0x0BD
0x0BE
0x0BF
0x0C0
0x0C1
0x0C2
0x0C3
0x0C4
0x0C5
0x0C6
0x0C7
0x0C8
0x0C9
0x0CA
0x0CB
0x0CC
0x0CD
0x0CE
0x0CF
0x0D0
0x0D1
0x0D2
0x0D3
0x0D4
0x0D5
0x0D6
0x0D7
0x0D8
0x0D9
0x0DA
0x0DB
0x0DC
0x0DD
0x0DE
0x0DF
Data Bit
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
AD7147
Default
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
STAGE6_CONNECTION[6:0]
STAGE6_CONNECTION[12:7]
STAGE6_AFE_OFFSET
STAGE6_SENSITIVITY
STAGE6_OFFSET_LOW
STAGE6_OFFSET_HIGH
STAGE6_OFFSET_HIGH_CLAMP
STAGE6_OFFSET_LOW_CLAMP
STAGE7_CONNECTION[6:0]
STAGE7_CONNECTION[12:7]
STAGE7_AFE_OFFSET
STAGE7_SENSITIVITY
STAGE7_OFFSET_LOW
STAGE7_OFFSET_HIGH
STAGE7_OFFSET_HIGH_CLAMP
STAGE7_OFFSET_LOW_CLAMP
STAGE8_CONNECTION[6:0]
STAGE8_CONNECTION[12:7]
STAGE8_AFE_OFFSET
STAGE8_SENSITIVITY
STAGE8_OFFSET_LOW
STAGE8_OFFSET_HIGH
STAGE8_OFFSET_HIGH_CLAMP
STAGE8_OFFSET_LOW_CLAMP
STAGE9_CONNECTION[6:0]
STAGE9_CONNECTION[12:7]
STAGE9_AFE_OFFSET
STAGE9_SENSITIVITY
STAGE9_OFFSET_LOW
STAGE9_OFFSET_HIGH
STAGE9_OFFSET_HIGH_CLAMP
STAGE9_OFFSET_LOW_CLAMP
STAGE10_CONNECTION[6:0]
STAGE10_CONNECTION[12:7]
STAGE10_AFE_OFFSET
STAGE10_SENSITIVITY
STAGE10_OFFSET_LOW
STAGE10_OFFSET_HIGH
STAGE10_OFFSET_HIGH_CLAMP
STAGE10_OFFSET_LOW_CLAMP
STAGE11_CONNECTION[6:0]
STAGE11_CONNECTION[12:7]
STAGE11_AFE_OFFSET
STAGE11_SENSITIVITY
STAGE11_OFFSET_LOW
STAGE11_OFFSET_HIGH
STAGE11_OFFSET_HIGH_CLAMP
STAGE11_OFFSET_LOW_CLAMP
Rev. E | Page 57 of 70
Description
STAGE6 CIN[6:0] connection setup (see Table 34)
STAGE6 CIN[12:7]connection setup (see Table 35)
STAGE6 AFE offset control (see Table 36)
STAGE6 sensitivity control (see Table 37)
STAGE6 initial offset low value
STAGE6 initial offset high value
STAGE6 offset high clamp value
STAGE6 offset low clamp value
STAGE7 CIN[6:0] connection setup (see Table 34)
STAGE7 CIN[12:7] connection setup (see Table 35)
STAGE7 AFE offset control (see Table 36)
STAGE7 sensitivity control (see Table 37)
STAGE7 initial offset low value
STAGE7 initial offset high value
STAGE7 offset high clamp value
STAGE7 offset low clamp value
STAGE8 CIN[6:0] connection setup (see Table 34)
STAGE8 CIN[12:7]connection setup (see Table 35)
STAGE8 AFE offset control (see Table 36)
STAGE8 sensitivity control (see Table 37)
STAGE8 initial offset low value
STAGE8 initial offset high value
STAGE8 offset high clamp value
STAGE8 offset low clamp value
STAGE9 CIN[6:0] connection setup (see Table 34)
STAGE9 CIN[12:7]connection setup (see Table 35)
STAGE9 AFE offset control (see Table 36)
STAGE9 sensitivity control (see Table 37)
STAGE9 initial offset low value
STAGE9 initial offset high value
STAGE9 offset high clamp value
STAGE9 offset low clamp value
STAGE10 CIN[6:0] connection setup (see Table 34)
STAGE10 CIN[12:7]connection setup (see Table 35)
STAGE10 AFE offset control (see Table 36)
STAGE10 sensitivity control (see Table 37)
STAGE10 initial offset low value
STAGE10 initial offset high value
STAGE10 offset high clamp value
STAGE10 offset low clamp value
STAGE11 CIN[6:0] connection setup (see Table 34)
STAGE11 CIN[12:7] connection setup (see Table 35)
STAGE11 AFE offset control (see Table 36)
STAGE11 sensitivity control (see Table 37)
STAGE11 initial offset low value
STAGE11 initial offset high value
STAGE11 offset high clamp value
STAGE11 offset low clamp value
AD7147
Data Sheet
BANK 3 REGISTERS
All address values are expressed in hexadecimal.
Table 39. STAGE0 Results Registers
Address
0x0E0
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE0_CONV_DATA
0x0E1
0x0E2
0x0E3
0x0E4
0x0E5
0x0E6
0x0E7
0x0E8
0x0E9
0x0EA
0x0EB
0x0EC
0x0ED
0x0EE
0x0EF
0x0F0
0x0F1
0x0F2
0x0F3
0x0F4
0x0F5
0x0F6
0x0F7
0x0F8
0x0F9
0x0FA
0x0FB
0x0FC
0x0FD
0x0FE
0x0FF
0x100
0x101
0x102
0x103
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE0_FF_WORD0
STAGE0_FF_WORD1
STAGE0_FF_WORD2
STAGE0_FF_WORD3
STAGE0_FF_WORD4
STAGE0_FF_WORD5
STAGE0_FF_WORD6
STAGE0_FF_WORD7
STAGE0_SF_WORD0
STAGE0_SF_WORD1
STAGE0_SF_WORD2
STAGE0_SF_WORD3
STAGE0_SF_WORD4
STAGE0_SF_WORD5
STAGE0_SF_WORD6
STAGE0_SF_WORD7
STAGE0_SF_AMBIENT
STAGE0_FF_AVG
STAGE0_PEAK_DETECT_WORD0
STAGE0_PEAK_DETECT_WORD1
STAGE0_MAX_WORD0
STAGE0_MAX_WORD1
STAGE0_MAX_WORD2
STAGE0_MAX_WORD3
STAGE0_MAX_AVG
STAGE0_HIGH_THRESHOLD
STAGE0_MAX_TEMP
STAGE0_MIN_WORD0
STAGE0_MIN_WORD1
STAGE0_MIN_WORD2
STAGE0_MIN_WORD3
STAGE0_MIN_AVG
STAGE0_LOW_THRESHOLD
STAGE0_MIN_TEMP
Unused
Rev. E | Page 58 of 70
Description
STAGE0 CDC 16-bit conversion data
(copy of CDC_RESULT_S0 register)
STAGE0 fast FIFO WORD0
STAGE0 fast FIFO WORD1
STAGE0 fast FIFO WORD2
STAGE0 fast FIFO WORD3
STAGE0 fast FIFO WORD4
STAGE0 fast FIFO WORD5
STAGE0 fast FIFO WORD6
STAGE0 fast FIFO WORD7
STAGE0 slow FIFO WORD0
STAGE0 slow FIFO WORD1
STAGE0 slow FIFO WORD2
STAGE0 slow FIFO WORD3
STAGE0 slow FIFO WORD4
STAGE0 slow FIFO WORD5
STAGE0 slow FIFO WORD6
STAGE0 slow FIFO WORD7
STAGE0 slow FIFO ambient value
STAGE0 fast FIFO average value
STAGE0 peak FIFO WORD0 value
STAGE0 peak FIFO WORD1 value
STAGE0 maximum value FIFO WORD0
STAGE0 maximum value FIFO WORD1
STAGE0 maximum value FIFO WORD2
STAGE0 maximum value FIFO WORD3
STAGE0 average maximum FIFO value
STAGE0 high threshold value
STAGE0 temporary maximum value
STAGE0 minimum value FIFO WORD0
STAGE0 minimum value FIFO WORD1
STAGE0 minimum value FIFO WORD2
STAGE0 minimum value FIFO WORD3
STAGE0 average minimum FIFO value
STAGE0 low threshold value
STAGE0 temporary minimum value
Set to 0
Data Sheet
AD7147
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE1_CONV_DATA
0x105
0x106
0x107
0x108
0x109
0x10A
0x10B
0x10C
0x10D
0x10E
0x10F
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
0x11E
0x11F
0x120
0x121
0x122
0x123
0x124
0x125
0x126
0x127
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_FF_WORD0
STAGE1_FF_WORD1
STAGE1_FF_WORD2
STAGE1_FF_WORD3
STAGE1_FF_WORD4
STAGE1_FF_WORD5
STAGE1_FF_WORD6
STAGE1_FF_WORD7
STAGE1_SF_WORD0
STAGE1_SF_WORD1
STAGE1_SF_WORD2
STAGE1_SF_WORD3
STAGE1_SF_WORD4
STAGE1_SF_WORD5
STAGE1_SF_WORD6
STAGE1_SF_WORD7
STAGE1_SF_AMBIENT
STAGE1_FF_AVG
STAGE1_PEAK_DETECT_WORD0
STAGE1_PEAK_DETECT_WORD1
STAGE1_MAX_WORD0
STAGE1_MAX_WORD1
STAGE1_MAX_WORD2
STAGE1_MAX_WORD3
STAGE1_MAX_AVG
STAGE1_HIGH_THRESHOLD
STAGE1_MAX_TEMP
STAGE1_MIN_WORD0
STAGE1_MIN_WORD1
STAGE1_MIN_WORD2
STAGE1_MIN_WORD3
STAGE1_MIN_AVG
STAGE1_LOW_THRESHOLD
STAGE1_MIN_TEMP
Unused
Rev. E | Page 59 of 70
Description
STAGE1 CDC 16-bit conversion data
(copy of CDC_RESULT_S1 register
STAGE1 fast FIFO WORD0
STAGE1 fast FIFO WORD1
STAGE1 fast FIFO WORD2
STAGE1 fast FIFO WORD3
STAGE1 fast FIFO WORD4
STAGE1 fast FIFO WORD5
STAGE1 fast FIFO WORD6
STAGE1 fast FIFO WORD7
STAGE1 slow FIFO WORD0
STAGE1 slow FIFO WORD1
STAGE1 slow FIFO WORD2
STAGE1 slow FIFO WORD3
STAGE1 slow FIFO WORD4
STAGE1 slow FIFO WORD5
STAGE1 slow FIFO WORD6
STAGE1 slow FIFO WORD7
STAGE1 slow FIFO ambient value
STAGE1 fast FIFO average value
STAGE1 peak FIFO WORD0 value
STAGE1 peak FIFO WORD1 value
STAGE1 maximum value FIFO WORD0
STAGE1 maximum value FIFO WORD1
STAGE1 maximum value FIFO WORD2
STAGE1 maximum value FIFO WORD3
STAGE1 average maximum FIFO value
STAGE1 high threshold value
STAGE1 temporary maximum value
STAGE1 minimum value FIFO WORD0
STAGE1 minimum value FIFO WORD1
STAGE1 minimum value FIFO WORD2
STAGE1 minimum value FIFO WORD3
STAGE1 average minimum FIFO value
STAGE1 low threshold value
STAGE1 temporary minimum value
Set to 0
AD7147
Data Sheet
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE2_CONV_DATA
0x129
0x12A
0x12B
0x12C
0x12D
0x12E
0x12F
0x130
0x131
0x132
0x133
0x134
0x135
0x136
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
0x13E
0x13F
0x140
0x141
0x142
0x143
0x144
0x145
0x146
0x147
0x148
0x149
0x14A
0x14B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE2_FF_WORD0
STAGE2_FF_WORD1
STAGE2_FF_WORD2
STAGE2_FF_WORD3
STAGE2_FF_WORD4
STAGE2_FF_WORD5
STAGE2_FF_WORD6
STAGE2_FF_WORD7
STAGE2_SF_WORD0
STAGE2_SF_WORD1
STAGE2_SF_WORD2
STAGE2_SF_WORD3
STAGE2_SF_WORD4
STAGE2_SF_WORD5
STAGE2_SF_WORD6
STAGE2_SF_WORD7
STAGE2_SF_AMBIENT
STAGE2_FF_AVG
STAGE2_PEAK_DETECT_WORD0
STAGE2_PEAK_DETECT_WORD1
STAGE2_MAX_WORD0
STAGE2_MAX_WORD1
STAGE2_MAX_WORD2
STAGE2_MAX_WORD3
STAGE2_MAX_AVG
STAGE2_HIGH_THRESHOLD
STAGE2_MAX_TEMP
STAGE2_MIN_WORD0
STAGE2_MIN_WORD1
STAGE2_MIN_WORD2
STAGE2_MIN_WORD3
STAGE2_MIN_AVG
STAGE2_LOW_THRESHOLD
STAGE2_MIN_TEMP
Unused
Rev. E | Page 60 of 70
Description
STAGE2 CDC 16-bit conversion data
(copy of CDC_RESULT_S2 register)
STAGE2 fast FIFO WORD0
STAGE2 fast FIFO WORD1
STAGE2 fast FIFO WORD2
STAGE2 fast FIFO WORD3
STAGE2 fast FIFO WORD4
STAGE2 fast FIFO WORD5
STAGE2 fast FIFO WORD6
STAGE2 fast FIFO WORD7
STAGE2 slow FIFO WORD0
STAGE2 slow FIFO WORD1
STAGE2 slow FIFO WORD2
STAGE2 slow FIFO WORD3
STAGE2 slow FIFO WORD4
STAGE2 slow FIFO WORD5
STAGE2 slow FIFO WORD6
STAGE2 slow FIFO WORD7
STAGE2 slow FIFO ambient value
STAGE2 fast FIFO average value
STAGE2 peak FIFO WORD0 value
STAGE2 peak FIFO WORD1 value
STAGE2 maximum value FIFO WORD0
STAGE2 maximum value FIFO WORD1
STAGE2 maximum value FIFO WORD2
STAGE2 maximum value FIFO WORD3
STAGE2 average maximum FIFO value
STAGE2 high threshold value
STAGE2 temporary maximum value
STAGE2 minimum value FIFO WORD0
STAGE2 minimum value FIFO WORD1
STAGE2 minimum value FIFO WORD2
STAGE2 minimum value FIFO WORD3
STAGE2 average minimum FIFO value
STAGE2 low threshold value
STAGE2 temporary minimum value
Set to 0
Data Sheet
AD7147
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE3_CONV_DATA
0x14D
0x14E
0x14F
0x150
0x151
0x152
0x153
0x154
0x155
0x156
0x157
0x158
0x159
0x15A
0x15B
0x15C
0x15D
0x15E
0x15F
0x160
0x161
0x162
0x163
0x164
0x165
0x166
0x167
0x168
0x169
0x16A
0x16B
0x16C
0x16D
0x16E
0x16F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE3_FF_WORD0
STAGE3_FF_WORD1
STAGE3_FF_WORD2
STAGE3_FF_WORD3
STAGE3_FF_WORD4
STAGE3_FF_WORD5
STAGE3_FF_WORD6
STAGE3_FF_WORD7
STAGE3_SF_WORD0
STAGE3_SF_WORD1
STAGE3_SF_WORD2
STAGE3_SF_WORD3
STAGE3_SF_WORD4
STAGE3_SF_WORD5
STAGE3_SF_WORD6
STAGE3_SF_WORD7
STAGE3_SF_AMBIENT
STAGE3_FF_AVG
STAGE3_PEAK_DETECT_WORD0
STAGE3_PEAK_DETECT_WORD1
STAGE3_MAX_WORD0
STAGE3_MAX_WORD1
STAGE3_MAX_WORD2
STAGE3_MAX_WORD3
STAGE3_MAX_AVG
STAGE3_HIGH_THRESHOLD
STAGE3_MAX_TEMP
STAGE3_MIN_WORD0
STAGE3_MIN_WORD1
STAGE3_MIN_WORD2
STAGE3_MIN_WORD3
STAGE3_MIN_AVG
STAGE3_LOW_THRESHOLD
STAGE3_MIN_TEMP
Unused
Rev. E | Page 61 of 70
Description
STAGE3 CDC 16-bit conversion data
(copy of CDC_RESULT_S3 register)
STAGE3 fast FIFO WORD0
STAGE3 fast FIFO WORD1
STAGE3 fast FIFO WORD2
STAGE3 fast FIFO WORD3
STAGE3 fast FIFO WORD4
STAGE3 fast FIFO WORD5
STAGE3 fast FIFO WORD6
STAGE3 fast FIFO WORD7
STAGE3 slow FIFO WORD0
STAGE3 slow FIFO WORD1
STAGE3 slow FIFO WORD2
STAGE3 slow FIFO WORD3
STAGE3 slow FIFO WORD4
STAGE3 slow FIFO WORD5
STAGE3 slow FIFO WORD6
STAGE3 slow FIFO WORD7
STAGE3 slow FIFO ambient value
STAGE3 fast FIFO average value
STAGE3 peak FIFO WORD0 value
STAGE3 peak FIFO WORD1 value
STAGE3 maximum value FIFO WORD0
STAGE3 maximum value FIFO WORD1
STAGE3 maximum value FIFO WORD2
STAGE3 maximum value FIFO WORD3
STAGE3 average maximum FIFO value
STAGE3 high threshold value
STAGE3 temporary maximum value
STAGE3 minimum value FIFO WORD0
STAGE3 minimum value FIFO WORD1
STAGE3 minimum value FIFO WORD2
STAGE3 minimum value FIFO WORD3
STAGE3 average minimum FIFO value
STAGE3 low threshold value
STAGE3 temporary minimum value
Set to 0
AD7147
Data Sheet
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE4_CONV_DATA
0x171
0x172
0x173
0x174
0x175
0x176
0x177
0x178
0x179
0x17A
0x17B
0x17C
0x17D
0x17E
0x17F
0x180
0x181
0x182
0x183
0x184
0x185
0x186
0x187
0x188
0x189
0x18A
0x18B
0x18C
0x18D
0x18E
0x18F
0x190
0x191
0x192
0x193
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE4_FF_WORD0
STAGE4_FF_WORD1
STAGE4_FF_WORD2
STAGE4_FF_WORD3
STAGE4_FF_WORD4
STAGE4_FF_WORD5
STAGE4_FF_WORD6
STAGE4_FF_WORD7
STAGE4_SF_WORD0
STAGE4_SF_WORD1
STAGE4_SF_WORD2
STAGE4_SF_WORD3
STAGE4_SF_WORD4
STAGE4_SF_WORD5
STAGE4_SF_WORD6
STAGE4_SF_WORD7
STAGE4_SF_AMBIENT
STAGE4_FF_AVG
STAGE4_PEAK_DETECT_WORD0
STAGE4_PEAK_DETECT_WORD1
STAGE4_MAX_WORD0
STAGE4_MAX_WORD1
STAGE4_MAX_WORD2
STAGE4_MAX_WORD3
STAGE4_MAX_AVG
STAGE4_HIGH_THRESHOLD
STAGE4_MAX_TEMP
STAGE4_MIN_WORD0
STAGE4_MIN_WORD1
STAGE4_MIN_WORD2
STAGE4_MIN_WORD3
STAGE4_MIN_AVG
STAGE4_LOW_THRESHOLD
STAGE4_MIN_TEMP
Unused
Rev. E | Page 62 of 70
Description
STAGE4 CDC 16-bit conversion data
(copy of CDC_RESULT_S4 register)
STAGE4 fast FIFO WORD0
STAGE4 fast FIFO WORD1
STAGE4 fast FIFO WORD2
STAGE4 fast FIFO WORD3
STAGE4 fast FIFO WORD4
STAGE4 fast FIFO WORD5
STAGE4 fast FIFO WORD6
STAGE4 fast FIFO WORD7
STAGE4 slow FIFO WORD0
STAGE4 slow FIFO WORD1
STAGE4 slow FIFO WORD2
STAGE4 slow FIFO WORD3
STAGE4 slow FIFO WORD4
STAGE4 slow FIFO WORD5
STAGE4 slow FIFO WORD6
STAGE4 slow FIFO WORD7
STAGE4 slow FIFO ambient value
STAGE4 fast FIFO average value
STAGE4 peak FIFO WORD0 value
STAGE4 peak FIFO WORD1 value
STAGE4 maximum value FIFO WORD0
STAGE4 maximum value FIFO WORD1
STAGE4 maximum value FIFO WORD2
STAGE4 maximum value FIFO WORD3
STAGE4 average maximum FIFO value
STAGE4 high threshold value
STAGE4 temporary maximum value
STAGE4 minimum value FIFO WORD0
STAGE4 minimum value FIFO WORD1
STAGE4 minimum value FIFO WORD2
STAGE4 minimum value FIFO WORD3
STAGE4 average minimum FIFO value
STAGE4 low threshold value
STAGE4 temporary minimum value
Set to 0
Data Sheet
AD7147
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE5_CONV_DATA
0x195
0x196
0x197
0x198
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
0x19F
0x1A0
0x1A1
0x1A2
0x1A3
0x1A4
0x1A5
0x1A6
0x1A7
0x1A8
0x1A9
0x1AA
0x1AB
0x1AC
0x1AD
0x1AE
0x1AF
0x1B0
0x1B1
0x1B2
0x1B3
0x1B4
0x1B5
0x1B6
0x1B7
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE5_FF_WORD0
STAGE5_FF_WORD1
STAGE5_FF_WORD2
STAGE5_FF_WORD3
STAGE5_FF_WORD4
STAGE5_FF_WORD5
STAGE5_FF_WORD6
STAGE5_FF_WORD7
STAGE5_SF_WORD0
STAGE5_SF_WORD1
STAGE5_SF_WORD2
STAGE5_SF_WORD3
STAGE5_SF_WORD4
STAGE5_SF_WORD5
STAGE5_SF_WORD6
STAGE5_SF_WORD7
STAGE5_SF_AMBIENT
STAGE5_FF_AVG
STAGE5_PEAK_DETECT_WORD0
STAGE5_PEAK_DETECT_WORD1
STAGE5_MAX_WORD0
STAGE5_MAX_WORD1
STAGE5_MAX_WORD2
STAGE5_MAX_WORD3
STAGE5_MAX_AVG
STAGE5_HIGH_THRESHOLD
STAGE5_MAX_TEMP
STAGE5_MIN_WORD0
STAGE5_MIN_WORD1
STAGE5_MIN_WORD2
STAGE5_MIN_WORD3
STAGE5_MIN_AVG
STAGE5_LOW_THRESHOLD
STAGE5_MIN_TEMP
Unused
Rev. E | Page 63 of 70
Description
STAGE5 CDC 16-bit conversion data
(copy of CDC_RESULT_S5 register)
STAGE5 fast FIFO WORD0
STAGE5 fast FIFO WORD1
STAGE5 fast FIFO WORD2
STAGE5 fast FIFO WORD3
STAGE5 fast FIFO WORD4
STAGE5 fast FIFO WORD5
STAGE5 fast FIFO WORD6
STAGE5 fast FIFO WORD7
STAGE5 slow FIFO WORD0
STAGE5 slow FIFO WORD1
STAGE5 slow FIFO WORD2
STAGE5 slow FIFO WORD3
STAGE5 slow FIFO WORD4
STAGE5 slow FIFO WORD5
STAGE5 slow FIFO WORD6
STAGE5 slow FIFO WORD7
STAGE5 slow FIFO ambient value
STAGE5 fast FIFO average value
STAGE5 peak FIFO WORD0 value
STAGE5 peak FIFO WORD1 value
STAGE5 maximum value FIFO WORD0
STAGE5 maximum value FIFO WORD1
STAGE5 maximum value FIFO WORD2
STAGE5 maximum value FIFO WORD3
STAGE5 average maximum FIFO value
STAGE5 high threshold value
STAGE5 temporary maximum value
STAGE5 minimum value FIFO WORD0
STAGE5 minimum value FIFO WORD1
STAGE5 minimum value FIFO WORD2
STAGE5 minimum value FIFO WORD3
STAGE5 average minimum FIFO value
STAGE5 low threshold value
STAGE5 temporary minimum value
Set to 0
AD7147
Data Sheet
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE6_CONV_DATA
0x1B9
0x1BA
0x1BB
0x1BC
0x1BD
0x1BE
0x1BF
0x1C0
0x1C1
0x1C2
0x1C3
0x1C4
0x1C5
0x1C6
0x1C7
0x1C8
0x1C9
0x1CA
0x1CB
0x1CC
0x1CD
0x1CE
0x1CF
0x1D0
0x1D1
0x1D2
0x1D3
0x1D4
0x1D5
0x1D6
0x1D7
0x1D8
0x1D9
0x1DA
0x1DB
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE6_FF_WORD0
STAGE6_FF_WORD1
STAGE6_FF_WORD2
STAGE6_FF_WORD3
STAGE6_FF_WORD4
STAGE6_FF_WORD5
STAGE6_FF_WORD6
STAGE6_FF_WORD7
STAGE6_SF_WORD0
STAGE6_SF_WORD1
STAGE6_SF_WORD2
STAGE6_SF_WORD3
STAGE6_SF_WORD4
STAGE6_SF_WORD5
STAGE6_SF_WORD6
STAGE6_SF_WORD7
STAGE6_SF_AMBIENT
STAGE6_FF_AVG
STAGE6_PEAK_DETECT_WORD0
STAGE6_PEAK_DETECT_WORD1
STAGE6_MAX_WORD0
STAGE6_MAX_WORD1
STAGE6_MAX_WORD2
STAGE6_MAX_WORD3
STAGE6_MAX_AVG
STAGE6_HIGH_THRESHOLD
STAGE6_MAX_TEMP
STAGE6_MIN_WORD0
STAGE6_MIN_WORD1
STAGE6_MIN_WORD2
STAGE6_MIN_WORD3
STAGE6_MIN_AVG
STAGE6_LOW_THRESHOLD
STAGE6_MIN_TEMP
Unused
Rev. E | Page 64 of 70
Description
STAGE6 CDC 16-bit conversion data
(copy of CDC_RESULT_S6 register)
STAGE6 fast FIFO WORD0
STAGE6 fast FIFO WORD1
STAGE6 fast FIFO WORD2
STAGE6 fast FIFO WORD3
STAGE6 fast FIFO WORD4
STAGE6 fast FIFO WORD5
STAGE6 fast FIFO WORD6
STAGE6 fast FIFO WORD7
STAGE6 slow FIFO WORD0
STAGE6 slow FIFO WORD1
STAGE6 slow FIFO WORD2
STAGE6 slow FIFO WORD3
STAGE6 slow FIFO WORD4
STAGE6 slow FIFO WORD5
STAGE6 slow FIFO WORD6
STAGE6 slow FIFO WORD7
STAGE6 slow FIFO ambient value
STAGE6 fast FIFO average value
STAGE6 peak FIFO WORD0 value
STAGE6 peak FIFO WORD1 value
STAGE6 maximum value FIFO WORD0
STAGE6 maximum value FIFO WORD1
STAGE6 maximum value FIFO WORD2
STAGE6 maximum value FIFO WORD3
STAGE6 average maximum FIFO value
STAGE6 high threshold value
STAGE6 temporary maximum value
STAGE6 minimum value FIFO WORD0
STAGE6 minimum value FIFO WORD1
STAGE6 minimum value FIFO WORD2
STAGE6 minimum value FIFO WORD3
STAGE6 average minimum FIFO value
STAGE6 low threshold value
STAGE6 temporary minimum value
Set to 0
Data Sheet
AD7147
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE7_CONV_DATA
0x1DD
0x1DE
0x1DF
0x1E0
0x1E1
0x1E2
0x1E3
0x1E4
0x1E5
0x1E6
0x1E7
0x1E8
0x1E9
0x1EA
0x1EB
0x1EC
0x1ED
0x1EE
0x1EF
0x1F0
0x1F1
0x1F2
0x1F3
0x1F4
0x1F5
0x1F6
0x1F7
0x1F8
0x1F9
0x1FA
0x1FB
0x1FC
0x1FD
0x1FE
0x1FF
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE7_FF_WORD0
STAGE7_FF_WORD1
STAGE7_FF_WORD2
STAGE7_FF_WORD3
STAGE7_FF_WORD4
STAGE7_FF_WORD5
STAGE7_FF_WORD6
STAGE7_FF_WORD7
STAGE7_SF_WORD0
STAGE7_SF_WORD1
STAGE7_SF_WORD2
STAGE7_SF_WORD3
STAGE7_SF_WORD4
STAGE7_SF_WORD5
STAGE7_SF_WORD6
STAGE7_SF_WORD7
STAGE7_SF_AMBIENT
STAGE7_FF_AVG
STAGE7_PEAK_DETECT_WORD0
STAGE7_PEAK_DETECT_WORD1
STAGE7_MAX_WORD0
STAGE7_MAX_WORD1
STAGE7_MAX_WORD2
STAGE7_MAX_WORD3
STAGE7_MAX_AVG
STAGE7_HIGH_THRESHOLD
STAGE7_MAX_TEMP
STAGE7_MIN_WORD0
STAGE7_MIN_WORD1
STAGE7_MIN_WORD2
STAGE7_MIN_WORD3
STAGE7_MIN_AVG
STAGE7_LOW_THRESHOLD
STAGE7_MIN_TEMP
Unused
Rev. E | Page 65 of 70
Description
STAGE7 CDC 16-bit conversion data
(copy of CDC_RESULT_S7 register)
STAGE7 fast FIFO WORD0
STAGE7 fast FIFO WORD1
STAGE7 fast FIFO WORD2
STAGE7 fast FIFO WORD3
STAGE7 fast FIFO WORD4
STAGE7 fast FIFO WORD5
STAGE7 fast FIFO WORD6
STAGE7 fast FIFO WORD7
STAGE7 slow FIFO WORD0
STAGE7 slow FIFO WORD1
STAGE7 slow FIFO WORD2
STAGE7 slow FIFO WORD3
STAGE7 slow FIFO WORD4
STAGE7 slow FIFO WORD5
STAGE7 slow FIFO WORD6
STAGE7 slow FIFO WORD7
STAGE7 slow FIFO ambient value
STAGE7 fast FIFO average value
STAGE7 peak FIFO WORD0 value
STAGE7 peak FIFO WORD1 value
STAGE7 maximum value FIFO WORD0
STAGE7 maximum value FIFO WORD1
STAGE7 maximum value FIFO WORD2
STAGE7 maximum value FIFO WORD3
STAGE7 average maximum FIFO value
STAGE7 high threshold value
STAGE7 temporary maximum value
STAGE7 minimum value FIFO WORD0
STAGE7 minimum value FIFO WORD1
STAGE7 minimum value FIFO WORD2
STAGE7 minimum value FIFO WORD3
STAGE7 average minimum FIFO value
STAGE7 low threshold value
STAGE7 temporary minimum value
Set to 0
AD7147
Data Sheet
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE8_CONV_DATA
0x201
0x202
0x203
0x204
0x205
0x206
0x207
0x208
0x209
0x20A
0x20B
0x20C
0x20D
0x20E
0x20F
0x210
0x211
0x212
0x213
0x214
0x215
0x216
0x217
0x218
0x219
0x21A
0x21B
0x21C
0x21D
0x21E
0x21F
0x220
0x221
0x222
0x223
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE8_FF_WORD0
STAGE8_FF_WORD1
STAGE8_FF_WORD2
STAGE8_FF_WORD3
STAGE8_FF_WORD4
STAGE8_FF_WORD5
STAGE8_FF_WORD6
STAGE8_FF_WORD7
STAGE8_SF_WORD0
STAGE8_SF_WORD1
STAGE8_SF_WORD2
STAGE8_SF_WORD3
STAGE8_SF_WORD4
STAGE8_SF_WORD5
STAGE8_SF_WORD6
STAGE8_SF_WORD7
STAGE8_SF_AMBIENT
STAGE8_FF_AVG
STAGE8_PEAK_DETECT_WORD0
STAGE8_PEAK_DETECT_WORD1
STAGE8_MAX_WORD0
STAGE8_MAX_WORD1
STAGE8_MAX_WORD2
STAGE8_MAX_WORD3
STAGE8_MAX_AVG
STAGE8_HIGH_THRESHOLD
STAGE8_MAX_TEMP
STAGE8_MIN_WORD0
STAGE8_MIN_WORD1
STAGE8_MIN_WORD2
STAGE8_MIN_WORD3
STAGE8_MIN_AVG
STAGE8_LOW_THRESHOLD
STAGE8_MIN_TEMP
Unused
Rev. E | Page 66 of 70
Description
STAGE8 CDC 16-bit conversion data
(copy of CDC_RESULT_S8 register)
STAGE8 fast FIFO WORD0
STAGE8 fast FIFO WORD1
STAGE8 fast FIFO WORD2
STAGE8 fast FIFO WORD3
STAGE8 fast FIFO WORD4
STAGE8 fast FIFO WORD5
STAGE8 fast FIFO WORD6
STAGE8 fast FIFO WORD7
STAGE8 slow FIFO WORD0
STAGE8 slow FIFO WORD1
STAGE8 slow FIFO WORD2
STAGE8 slow FIFO WORD3
STAGE8 slow FIFO WORD4
STAGE8 slow FIFO WORD5
STAGE8 slow FIFO WORD6
STAGE8 slow FIFO WORD7
STAGE8 slow FIFO ambient value
STAGE8 fast FIFO average value
STAGE8 peak FIFO WORD0 value
STAGE8 peak FIFO WORD1 value
STAGE8 maximum value FIFO WORD0
STAGE8 maximum value FIFO WORD1
STAGE8 maximum value FIFO WORD2
STAGE8 maximum value FIFO WORD3
STAGE8 average maximum FIFO value
STAGE8 high threshold value
STAGE8 temporary maximum value
STAGE8 minimum value FIFO WORD0
STAGE8 minimum value FIFO WORD1
STAGE8 minimum value FIFO WORD2
STAGE8 minimum value FIFO WORD3
STAGE8 average minimum FIFO value
STAGE8 low threshold value
STAGE7 temporary minimum value
Set to 0
Data Sheet
AD7147
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE9_CONV_DATA
0x225
0x226
0x227
0x228
0x229
0x22A
0x22B
0x22C
0x22D
0x22E
0x22F
0x230
0x231
0x232
0x233
0x234
0x235
0x236
0x237
0x238
0x239
0x23A
0x23B
0x23C
0x23D
0x23E
0x23F
0x240
0x241
0x242
0x243
0x244
0x245
0x246
0x247
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE9_FF_WORD0
STAGE9_FF_WORD1
STAGE9_FF_WORD2
STAGE9_FF_WORD3
STAGE9_FF_WORD4
STAGE9_FF_WORD5
STAGE9_FF_WORD6
STAGE9_FF_WORD7
STAGE9_SF_WORD0
STAGE9_SF_WORD1
STAGE9_SF_WORD2
STAGE9_SF_WORD3
STAGE9_SF_WORD4
STAGE9_SF_WORD5
STAGE9_SF_WORD6
STAGE9_SF_WORD7
STAGE9_SF_AMBIENT
STAGE9_FF_AVG
STAGE9_PEAK_DETECT_WORD0
STAGE9_PEAK_DETECT_WORD1
STAGE9_MAX_WORD0
STAGE9_MAX_WORD1
STAGE9_MAX_WORD2
STAGE9_MAX_WORD3
STAGE9_MAX_AVG
STAGE9_HIGH_THRESHOLD
STAGE9_MAX_TEMP
STAGE9_MIN_WORD0
STAGE9_MIN_WORD1
STAGE9_MIN_WORD2
STAGE9_MIN_WORD3
STAGE9_MIN_AVG
STAGE9_LOW_THRESHOLD
STAGE9_MIN_TEMP
Unused
Rev. E | Page 67 of 70
Description
STAGE9 CDC 16-bit conversion data
(copy of CDC_RESULT_S9 register)
STAGE9 fast FIFO WORD0
STAGE9 fast FIFO WORD1
STAGE9 fast FIFO WORD2
STAGE9 fast FIFO WORD3
STAGE9 fast FIFO WORD4
STAGE9 fast FIFO WORD5
STAGE9 fast FIFO WORD6
STAGE9 fast FIFO WORD7
STAGE9 slow FIFO WORD0
STAGE9 slow FIFO WORD1
STAGE9 slow FIFO WORD2
STAGE9 slow FIFO WORD3
STAGE9 slow FIFO WORD4
STAGE9 slow FIFO WORD5
STAGE9 slow FIFO WORD6
STAGE9 slow FIFO WORD7
STAGE9 slow FIFO ambient value
STAGE9 fast FIFO average value
STAGE9 peak FIFO WORD0 value
STAGE9 peak FIFO WORD1 value
STAGE9 maximum value FIFO WORD0
STAGE9 maximum value FIFO WORD1
STAGE9 maximum value FIFO WORD2
STAGE9 maximum value FIFO WORD3
STAGE9 average maximum FIFO value
STAGE9 high threshold value
STAGE9 temporary maximum value
STAGE9 minimum value FIFO WORD0
STAGE9 minimum value FIFO WORD1
STAGE9 minimum value FIFO WORD2
STAGE9 minimum value FIFO WORD3
STAGE9 average minimum FIFO value
STAGE9 low threshold value
STAGE9 temporary minimum value
Set to 0
AD7147
Data Sheet
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE10_CONV_DATA
0x249
0x24A
0x24B
0x24C
0x24D
0x24E
0x24F
0x250
0x251
0x252
0x253
0x254
0x255
0x256
0x257
0x258
0x259
0x25A
0x25B
0x25C
0x25D
0x25E
0x25F
0x260
0x261
0x262
0x263
0x264
0x265
0x266
0x267
0x268
0x269
0x26A
0x26B
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE10_FF_WORD0
STAGE10_FF_WORD1
STAGE10_FF_WORD2
STAGE10_FF_WORD3
STAGE10_FF_WORD4
STAGE10_FF_WORD5
STAGE10_FF_WORD6
STAGE10_FF_WORD7
STAGE10_SF_WORD0
STAGE10_SF_WORD1
STAGE10_SF_WORD2
STAGE10_SF_WORD3
STAGE10_SF_WORD4
STAGE10_SF_WORD5
STAGE10_SF_WORD6
STAGE10_SF_WORD7
STAGE10_SF_AMBIENT
STAGE10_FF_AVG
STAGE10_PEAK_DETECT_WORD0
STAGE10_PEAK_DETECT_WORD1
STAGE10_MAX_WORD0
STAGE10_MAX_WORD1
STAGE10_MAX_WORD2
STAGE10_MAX_WORD3
STAGE10_MAX_AVG
STAGE10_HIGH_THRESHOLD
STAGE10_MAX_TEMP
STAGE10_MIN_WORD0
STAGE10_MIN_WORD1
STAGE10_MIN_WORD2
STAGE10_MIN_WORD3
STAGE10_MIN_AVG
STAGE10_LOW_THRESHOLD
STAGE10_MIN_TEMP
Unused
Rev. E | Page 68 of 70
Description
STAGE10 CDC 16-bit conversion data
(copy of CDC_RESULT_S10 register)
STAGE10 fast FIFO WORD0
STAGE10 fast FIFO WORD1
STAGE10 fast FIFO WORD2
STAGE10 fast FIFO WORD3
STAGE10 fast FIFO WORD4
STAGE10 fast FIFO WORD5
STAGE10 fast FIFO WORD6
STAGE10 fast FIFO WORD7
STAGE10 slow FIFO WORD0
STAGE10 slow FIFO WORD1
STAGE10 slow FIFO WORD2
STAGE10 slow FIFO WORD3
STAGE10 slow FIFO WORD4
STAGE10 slow FIFO WORD5
STAGE10 slow FIFO WORD6
STAGE10 slow FIFO WORD7
STAGE10 slow FIFO ambient value
STAGE10 fast FIFO average value
STAGE10 peak FIFO WORD0 value
STAGE10 peak FIFO WORD1 value
STAGE10 maximum value FIFO WORD0
STAGE10 maximum value FIFO WORD1
STAGE10 maximum value FIFO WORD2
STAGE10 maximum value FIFO WORD3
STAGE10 average maximum FIFO value
STAGE10 high threshold value
STAGE10 temporary maximum value
STAGE10 minimum value FIFO WORD0
STAGE10 minimum value FIFO WORD1
STAGE10 minimum value FIFO WORD2
STAGE10 minimum value FIFO WORD3
STAGE10 average minimum FIFO value
STAGE10 low threshold value
STAGE10 temporary minimum value
Set to 0
Data Sheet
AD7147
Data Bit
[15:0]
Default
Value
X
Type
R/W
Name
STAGE11_CONV_DATA
0x26D
0x26E
0x26F
0x270
0x271
0x272
0x273
0x274
0x275
0x276
0x277
0x278
0x279
0x27A
0x27B
0x27C
0x27D
0x27E
0x27F
0x280
0x281
0x282
0x283
0x284
0x285
0x286
0x287
0x288
0x289
0x28A
0x28B
0x28C
0x28D
0x28E
0x28F
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE11_FF_WORD0
STAGE11_FF_WORD1
STAGE11_FF_WORD2
STAGE11_FF_WORD3
STAGE11_FF_WORD4
STAGE11_FF_WORD5
STAGE11_FF_WORD6
STAGE11_FF_WORD7
STAGE11_SF_WORD0
STAGE11_SF_WORD1
STAGE11_SF_WORD2
STAGE11_SF_WORD3
STAGE11_SF_WORD4
STAGE11_SF_WORD5
STAGE11_SF_WORD6
STAGE11_SF_WORD7
STAGE11_SF_AMBIENT
STAGE11_FF_AVG
STAGE11_PEAK_DETECT_WORD0
STAGE11_PEAK_DETECT_WORD1
STAGE11_MAX_WORD0
STAGE11_MAX_WORD1
STAGE11_MAX_WORD2
STAGE11_MAX_WORD3
STAGE11_MAX_AVG
STAGE11_HIGH_THRESHOLD
STAGE11_MAX_TEMP
STAGE11_MIN_WORD0
STAGE11_MIN_WORD1
STAGE11_MIN_WORD2
STAGE11_MIN_WORD3
STAGE11_MIN_AVG
STAGE11_LOW_THRESHOLD
STAGE11_MIN_TEMP
Unused
Rev. E | Page 69 of 70
Description
STAGE11 CDC 16-bit conversion data
(copy of CDC_RESULT_S11 register)
STAGE11 fast FIFO WORD0
STAGE11 fast FIFO WORD1
STAGE11 fast FIFO WORD2
STAGE11 fast FIFO WORD3
STAGE11 fast FIFO WORD4
STAGE11 fast FIFO WORD5
STAGE11 fast FIFO WORD6
STAGE11 fast FIFO WORD7
STAGE11 slow FIFO WORD0
STAGE11 slow FIFO WORD1
STAGE11 slow FIFO WORD2
STAGE11 slow FIFO WORD3
STAGE11 slow FIFO WORD4
STAGE11 slow FIFO WORD5
STAGE11 slow FIFO WORD6
STAGE11 slow FIFO WORD7
STAGE11 slow FIFO ambient value
STAGE11 fast FIFO average value
STAGE11 peak FIFO WORD0 value
STAGE11 peak FIFO WORD1 value
STAGE11 maximum value FIFO WORD0
STAGE11 maximum value FIFO WORD1
STAGE11 maximum value FIFO WORD2
STAGE11 maximum value FIFO WORD3
STAGE11 average maximum FIFO value
STAGE11 high threshold value
STAGE11 temporary maximum value
STAGE11 minimum value FIFO WORD0
STAGE11 minimum value FIFO WORD1
STAGE11 minimum value FIFO WORD2
STAGE11 minimum value FIFO WORD3
STAGE11 average minimum FIFO value
STAGE11 low threshold value
STAGE11 temporary minimum value
Set to 0
AD7147
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
24
19
18
EXPOSED
PAD
2.65
2.50 SQ
2.45
13
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
6
12
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
03-11-2013-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
ORDERING GUIDE
Model1, 2
AD7147ACPZ-REEL
AD7147ACPZ-500RL7
AD7147PACPZ-RL
AD7147PACPZ-500R7
AD7147ACPZ-1REEL
AD7147ACPZ-1500RL7
AD7147PACPZ-1RL
AD7147PACPZ-1500R7
AD7147WPACPZ-RL
AD7147WPACPZ-500R7
AD7147WPACPZ-1RL
AD7147WPACPZ-1500R
EVAL-AD7147EBZ
EVAL-AD7147-1EBZ
1
2
Temperature
Range
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
40C to +85C
Description
Wake up on touch
Wake up on touch
Wake up on proximity
Wake up on proximity
Wake up on touch
Wake up on touch
Wake up on proximity
Wake up on proximity
Wake up on proximity
Wake up on proximity
Wake up on proximity
Wake up on proximity
Serial Interface
Description
SPI Interface
SPI Interface
SPI Interface
SPI Interface
I2C Interface
I2C Interface
I2C Interface
I2C Interface
SPI Interface
SPI Interface
I2C Interface
I2C Interface
SPI Interface
I2C Interface
Package Description
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
24-Lead LFCSP_WQ
Evaluation Board
Evaluation Board
Package
Option
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
CP-24-7
AUTOMOTIVE PRODUCTS
The AD7147W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. E | Page 70 of 70