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I. INTRODUCTION
INGLE-PHASE ac/dc converters are one of the most common power conversion systems and can be found in many
industrial as well as residential applications, e.g., variable speed
drive, electric vehicle chargers, and power supplies for consumer
electronics. In order to meet the ever more stringent grid codes
like the IEC61000-3-2 harmonic limits, high-power factor and
sinusoidal current regulation are required for basically all such
applications as long as their power ratings exceed 75 W [1].
Presently, single-phase power factor correction (PFC) converters are a very popular solution to ensure the compliance of such
Manuscript received November 19, 2013; revised February 12, 2014; accepted March 15, 2014. Date of publication March 28, 2014; date of current
version October 7, 2014. Recommended for publication by Associate Editor
R. Redl.
Y. Tang and F. Blaabjerg are with the Department of Energy Technology, Aalborg University, Aalborg East 9220, Denmark (e-mail: yta@et.aau.dk;
fbl@et.aau.dk).
D. Zhu, C. Jin, and P. Wang are with the School of Electrical and Electronic
Engineering, Nanyang Technological University, Singapore 639798 (e-mail:
ZHUD0009@e.ntu.edu.sg; jinchi@ntu.edu.sg; epwang@ntu.edu.sg).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2014.2314136
0885-8993 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
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Fig. 1. Circuit diagram of the proposed three-level PFC converter for singlephase PHEV chargers.
Vin | sin t|
VL
(1)
Vin | sin t| VL
.
VH VL
(2)
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is the root reason that why the dc/dc converter may only process partial input power and higher conversion efficiency can be
obtained through the proposed topology. The idealized operating waveforms during these two modes are presented in Fig. 2.
In order to ensure smooth transition between the low- and
high-voltage level commutations, an offset is injected into the
carrier of the pulse-width modulation (PWM) for Q2 as shown in
Fig. 2. As a result, a unified reference signal Vm can be derived
to simultaneously modulate Q1 and Q2, which is written as
Vin | sin t|
,
Vin | sin t| VL
1
VL
vm (t) =
.
(3)
VL Vin | sin t|
VH VL
Compared with the conventional boost PFC, the proposed
converter will have slightly higher conduction losses because
of the series connection of Q2 and D1. However, its switching losses can be greatly reduced due to its three-level output
that splits the high dc bus voltage into two low voltage portions. Moreover, efficiency gain from the dc/dc converter is also
significant because it only converts the input power that flow
through D2.
To estimate the percentage of input power that is converted
by this buck stage, it is assumed that the power converter is
lossless and harmonic free. In this case, the instantaneous input
power from ac side will be
Vin Iin
(1 cos 2t) (4)
pin = Vin | sin t| Iin | sin t| =
2
where Iin is the peak value of the boost inductor current. If the
PFC is commutating at high-voltage levels, part of the input
power will be directly supplied into the load when Q2 is on, and
it can be found as
pbatt
= Iin | sin t| d2 VL
Fig. 3. Instantaneous power distribution in the PFC converter and the buck
converter, given fixed gird voltage, output voltage, and dc-link voltage.
Vin | sin t| VL
= Iin | sin t| 1
VL
VH VL
VH Vin | sin t|
= VL Iin | sin t|
.
VH VL
(5)
Plotting (4) and (5) will give rise to the time domain waveforms of power distribution shown in Fig. 3, and it is clear that
the shaded area enclosed by pin and pbatt H indicates the active
power pdc that needs to be processed by the buck converter.
Taking the integration of pin and pdc over half fundamental
period, it is possible to find that
arcsin(V L /V i n )
=
arcsin(V L /V i n )
(pin pbatt
H ) dt
pin dt
arcsin(V L /V i n )
=
pdc dt
arcsin(V L /V i n )
0 pin dt
arcsin(V L /V i n )
=
VH Iin | sin t| (1
arcsin(V L /V i n )
V i n Ii n
0
2 (1 cos 2t)dt
arcsin(V L /V i n )
=
arcsin(V L /V i n )
VH | sin t|
d2 ) dt
V i n | sin t|V L
V H V L
(1 cos 2t)dt
Vin
VH
VL
=
2 arcsin
Vin VH VL
Vin
VL
2VL
cos arcsin
.
VH VL
Vin
dt
Vin
2
(6)
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be designed to reject this periodic disturbance. In order to realize these control objectives, two independent control loops
are designed for controlling the PFC stage and the buck stage,
respectively, and the control algorithms will be elaborated as
follows.
A. PFC Converter Control
s2 + (2)2
s2 + K2 s + (2)2
(9)
pfc (s)
Vdc
Iin (s)
=
dpfc (s)
sLin
(10)
Fig. 5.
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Overall control block diagram for the proposed three-level PFC converter.
TABLE I
CIRCUIT PARAMETERS USED FOR SIMULATION AND EXPERIMENT
Gv d
1 + z
VL (s)
= VH
2
ddc (s)
1 + Qs o + s 2
o
1
Rload + RL dc
1
z =
, o =
RC L CL
Rload + RC L Ldc CL
dc (s) =
1
Ldc CL
(12)
(13)
RC L + RL dc
CL
Q=
where o is the LC resonant frequency introduced by the output filter. RC L is the ESR of the output capacitor CL and it
introduces a zero z in the open-loop gain. RL dc is the ESR of
the boost inductor and these two ESRs together determine the
quality factor Q of this second-order system and they can provide damping effect to the LC resonance. Using the parameters
listed in Table I, the Bode diagram of (12) can then be plotted as
dotted line in Fig. 6. As shown, its closed-loop control system
is inherently stable even if a simple proportional gain is used.
However, if the crossover frequency of this control loop is tuned
to be less than one tenth of the switching frequency, e.g., 1 kHz,
the system phase margin is only 17 , which is obviously insufficient and may cause transient oscillations. Furthermore, this
system has limited dc gain, and its steady-state tracking error
may not be zero.
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Fig. 6. Bode diagrams of the original system (dotted line), type-III compensator (dashed line), and compensated system (solid line).
Kdc (1 +
s(1 +
s
z 1
s
p 1
)(1 +
)(1 +
s
z 2
s
p 2
(14)
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TABLE II
KEY COMPONENTS USED FOR THE EXPERIMENTAL PROTOTYPE
Fig. 9. Experimental load step-down waveforms, C1: grid voltage, C2: converter pole voltage, C3: buck converter current, and C4: grid current.
A 2-kW prototype circuit was built in the laboratory for experimental validation of the proposed PFC converter and the
circuit parameters are basically the same as those used in simulation, despite some very slight differences due to the tolerance
of passive components. The key active and passive components
used for the tested prototype are summarized in Table II.
The proposed topology was first tested with standard
230-V/50-Hz high-line ac input and its corresponding steadystate experimental waveforms are presented in Fig. 8. It is obvious that they can match well with those simulated ones presented
in Fig. 7. It should be noted that there is very slight current distortion during the mode transition period, and this is due to the
limited compensation gain of the controller.
Fig. 9 shows the dynamic response of the system when it
subjects to 100% to 50% step-down load change. As shown,
the transient process is very smooth and there is no obvious
distortion in the grid current, and the high bus voltage can be
well regulated with insignificant voltage overshoot.
In contrast, Fig. 10 shows the experimental waveforms when
the system undergoes 50% to 100% step-up load change, and the
probed signals are replaced by the two dc bus voltages, rectified
input voltage, and load current in order to observe their dynamic
responses. As can be seen, the load transient can be handled by
the high-voltage bus and the output voltage remains undisturbed.
In order to examine the line frequency ripple component in the
Fig. 10. Experimental load step-up waveforms, C1: input voltage, C2: high
dc bus voltage, C3: load voltage, and C4: load current.
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Fig. 11. Harmonic contents of the output voltage and high dc bus voltage
under 230-V/2-kW operation.
Fig. 14. Efficiency curves of the proposed PFC converter under universal input
voltages, shown in comparison with the conventional two-stage solution.
the results can well comply with the IEC 61000-3-2 Class A
standard, which is specified for equipment with power rating
above 600 W. The total harmonic distortion (THD) of the input
current is found to be 5.7% (calculated up to 50th harmonic
order) under high-line operation and it is improved to 3.1%
under low-line case. As mentioned previously, this is because
the intermittent operation of the buck converter may impose
disturbances to the system and affect the input current regulation
under high-line operation.
The proposed PFC converter is also compared with a conventional two-stage solution, i.e., a boost PFC cascaded with a
dc/dc buck converter, and its circuitry is obtained by removing
D1 and Q2 shown in Fig. 1. Therefore, the proposed three-level
PFC will have higher cost than the conventional one, and it
is complicated with one fast recovery diode (D1), one switch
(Q2), and one isolated gate driver. The remaining active and
passive components in the two-stage PFC are exactly the same
as those in the proposed one and therefore, a fair performance
comparison can be conducted.
Fig. 15. Efficiency curve of the proposed PFC converter under different output
voltages, shown in comparison with the conventional two-stage solution.
V. CONCLUSION
In this paper, a three-level quasi-two-stage single-phase PFC
converter has been presented. It has flexible output voltage and
can be used for single-phase PHEV charger applications, where
the battery voltage can be either lower or higher than the peak
ac input voltage. The proposed converter features high quality
input current, three-level output voltage, and improved conversion efficiency. By designing a fast regulation loop for the buck
converter, the inherent fluctuating power issue in single phase
systems can also be resolved, and the load voltage will be fairly
constant and insensitive to load changes and external disturbances. Moreover, a dynamic gain compensator is implemented
in the current control loop and in this case, its control bandwidth can be kept relatively constant irrespective of the dc bus
voltage change during two different operation modes. Therefore, the grid current can be well regulated with low THD and
high-power factor. Experimental results obtained from a 2-kW
laboratory prototype have been presented in the paper, which
are in good agreement with the theoretical analysis. The efficiency curves under universal input conditions were recorded
from a commercial power analyzer, and it is found that the
proposed PFC may have 1% efficiency gain under high-line
operation as compared to a conventional cascaded two-stage solution. This efficiency improvement is partly contributed by the
reduced switching voltage in the PFC stage, and also partly by
the reduced power conversion in the dc/dc buck stage.
REFERENCES
[1] Electromagnetic Compatibility (EMC)Part3: LimitsSection 2: Limits
for Harmonic Current Emissions (Equipment Input Current < 16 A Per
Phase), IEC Standard 61000-3-2, 1998.
[2] L. Huber, Y. Jang, and M. M. Jovanovic, Performance evaluation of
bridgeless PFC boost rectifiers, IEEE Trans. Power Electron., vol. 23,
no. 3, pp. 13811390, May 2008.
[3] F. Musavi, W. Eberle, and W. G. Dunford, A high-performance singlephase bridgeless interleaved PFC converter for plug-in hybrid electric
vehicle battery chargers, IEEE Trans. Ind. Appl., vol. 47, no. 4, pp. 1833
1843, Jul./Aug. 2011.
[4] F. Musavi, M. Edington, W. Eberle, and W. G. Dunford, Evaluation and
efficiency comparison of front end ACDC plug-in hybrid charger topologies, IEEE Trans. Smart Grid, vol. 3, no. 1, pp. 413421, Mar. 2012.
[5] M. Pahlevaninezhad, P. Das, J. Drobnik, P. K. Jain, and A. Bakhshai, A
ZVS interleaved boost AC/DC converter used in plug-in electric vehicles,
IEEE Trans. Power Electron., vol. 27, no. 8, pp. 35133529, Aug. 2012.
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Dexuan Zhu (S13) received the B.Sc. degree in electrical engineering from Wuhan University, Wuhan,
China, in 2011, and the M.Sc. degree in power engineering from the Nanyang Technological University
(NTU), Singapore, in 2012. He is currently working
toward the Ph.D. degree at Energy Research Institude, NTU, from August 2012.
His research interests include power electronics
for various applications such as motor drives, connecting renewable energy sources, and energy diveces to microgirds.
Chi Jin received the B.Sc. degree in electrical engineering from Wuhan University, Wuhan, China, in
2007, and the M.Sc. degree from Nanyang Technological University, Singapore, in 2009, where he
is currently working toward the Ph.D. degree in the
School of Electrical and Electronic Engineering.
In 2011, he was a Visiting Scholar with the Institute of Energy Technology, Aalborg University,
Aalborg East, Denmark, where he worked on the
control strategies of hybrid ac/dc/storage microgrid
system. Since 2013, he joined the Energy Research
Institute, Nanyang Technological University, Singapore, as a Research Associate.
Frede Blaabjerg (S86M88SM97F03) received the Ph.D. degree from Aalborg University,
Aalborg, Denmark, in 1992.
He was with ABB-Scandia, Randers, Denmark,
from 1987 to 1988. He became an Assistant Professor in 1992, an Associate Professor in 1996, and a Full
Professor of power electronics and drives in 1998 in
Aalborg University. His current research interests include power electronics and its applications such as
in wind turbines, PV systems, reliability, harmonics,
and adjustable speed drives.
Dr. Blaabjerg received 15 IEEE Prize Paper Awards, the IEEE PELS Distinguished Service Award in 2009, the EPE-PEMC Council Award in 2010,
the IEEE William E. Newell Power Electronics Award 2014, and the Villum
Kann Rasmussen Research Award 2014. He was an Editor-in-Chief of the IEEE
TRANSACTIONS ON POWER ELECTRONICS from 2006 to 2012. He has been a
Distinguished Lecturer for the IEEE Power Electronics Society from 2005 to
2007 and for the IEEE Industry Applications Society from 2010 to 2011.