VBMB - 007

8259 INTERFACE BOARD
(Model No : VBMB - 007)
Application Manual
Version 2.0
Technical Clarification /Suggestion :

/
Technical Support Division,
Vi Microsystems Pvt. Ltd.,

Plot No :75,Electronics Estate,
Perungudi,Chennai - 600 096,INDIA.
Ph: 91- 44-2496 3142, 91-44-2496 1852,
Mail : service@vimicrosystems.com,
Web : www.vimicrosystems.com
PREFACE:
This manual discusses in detail about VBMB-007,Revision 2. This board incorporates 8259
interfacing in normal and simulated mode.
The scope of the VBMB series is, to explain the microprocessor based interfaces in a simple
and straight forward manner, to utilize almost all the facilities available in an interface and to
create a real microprocessor lab environment by providing debugging facilities.
A noteworthy feature of this interface board is, that it can be used as a learning tool or as an
interface. This is true with all our VBMB boards.
VBMB-003 is compatible with our extended bus VXT -BUS and the pinout details of this
VXT-BUS is given at the end of this manual.
Some simple easy-to-understand software examples are presented in the following sections.
All this programs are written in Intels 8085 mnemonics, and you can directly execute them with
our Micro-85 ET, Micro-85 EB kits. Appendices gives assembly language programs for other
popular microprocessor.
We hopes this manual will be of immense use to you. We shall be grateful to consider
suggestions for further improvement of this manual.
Write to:
The Customer-Support Division,
Vi Microsystems Pvt.Ltd.,
Plot N0.75,Electronics Estate,
Perungudi,CHENNAI-600 096.
PHONE # (044) 496 1842
FAX # (044) 496 1536.
TABLE OF CONTENTS
CHAPTER
PAGE N0.
1.USE OF INTERRUPTS IN MICROCOMPUTER SYSTEMS...........................1

2.ABOUT 8259
2.1 INTRODUCTION....................................................................................3
2.2 FUNCTIONAL BLOCKS OF 8259 .........................................................5
3.CIRCUIT DETAILS
3.1 CIRCUIT IMPLEMENTATION ..............................................................10
3.2 I/O DECODING .......................................................................................11
4.PROGRAMMING THE 8259 A
4.1 INITIALIZATION COMMAND WORDS .............................................15
4.2 OPERATION COMMAND WORDS.......................................................21
4.3 SPECIAL MASK MODE..........................................................................26
4.4 POLL COMMAND ..................................................................................27
4.5 READING THE 8259 STATUS................................................................28
4.6 PROGRAM TO TEST THE VBMB-007 IN SIMULATED MODE.........29
LIST OF APPENDICES
APPENDIX-A
PROGRAMS IN 8086 ASSEMBLY LANGUAGE ....................A-1
APPENDIX-B
PROGRAMS IN 8031 ASSEMBLY LANGUAGE......................B-1
APPENDIX-C
IC PINOUTS.................................................................................C-1
APPENDIX-D
CIRCUIT DIAGRAMS..................................................................D-1
APPENDIX-E
COMPONENT LAYOUT..............................................................E-1
VBMB - 007
CHAPTER - 1
USE OF INTERRUPTS IN MICROCOMPUTER SYSTEMS

In any microprocessor based systems, there may be 2 or more input devices, say , keyboards,
display or other sensors that require the attention (servicing) of microprocessor from time to time.
There are different ways in which peripherals can be serviced by the microprocessor.
The most common method of servicing such devices is the polled approach. In this method, the
processor tests each device in sequence and asks each device if it needs servicing. Thus the
processor is continuously put in a waiting stage till the peripheral becomes ready. It is obvious
that this method is a less efficient way Figure 1.1 illustrates this.
Vi Microsystems Pvt Ltd.,
[1]
VBMB - 007
It will be desirable to let the microprocessor to execute main program and only interrupt when
the peripheral needs servicing. That is, the device should interrupt the processor whenever it
requires servicing. The processor will then stop the execution of the main program and execute
the service routine. Service routine is a special program or routine that is associated with the
peripherals specific functional or operational requirements. Once the servicing is completed the
processor would resume exactly where it left off. This method is known as interrupting the
processor. Figure 1.2 shows this process.
[2]
VBMB - 007
CHAPTER - 2
ABOUT 8259
2.1
INTRODUCTION:
The VBMB - 007 comprises of the Programmable Interrupt Controller Intel 8259.
The Programmable Interrupt Controller (PIC) Functions as an overall manager in an
interrupt driven system environment. It accepts requests from the peripheral equipment,
determines which of the incoming requests is of the highest importance (priority) , ascertains
whether the incoming request has a higher priority value than the level currently being serviced
and issues an interrupt to the CPU based on this determination.
The special features of 8259 are,

1) Eight level priority controller
2) Expandable to 64 levels
3) Programmable interrupt modes
4) Individual request mask capability
The 8259 is designed to minimize the software and real time overhead in handling
multilevel priority interrupts. It has several modes, permitting optimization for a variety of
system requirements.
The block diagram of 8259 is given in figure 2 - 1.
[3]
VBMB - 007
8259 BLOCK DIAGRAM
[4]
VBMB - 007
2.2 FUNCTIONAL BLOCKS OF 8259:

2.2.1 Interrupt Request Register (IRR) and In-Service Register (ISR)
The interrupts at the IR input lines are handled by 2 registers in cascade, the Interrupt
Request Register (IRR) and the IN-Service Register (ISR). The IRR is used to store all the
interrupt levels which are requesting service, and the ISR is used to store all the interrupt levels
which are being serviced.
2.2.2 Priority Resolver
This logic block determines the priorities of the bits set in the IRR. The highest priority
is selected and strobed into the corresponding bit of the ISR during INTA pulse .
2.2.3 Interrupt Mask Register

This IMR stores the bits which mask the interrupt lines to be masked. The IMR operates
on the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower
priority.
2.2.4 Data Bus Buffer
This 3 state, bidirectional 8 bit buffer is used to interface the 8259A to the system Data
Bus.Control words and status information are transferred through the Data Bus Buffer.
2.2.5 Read/Write Control logic
The function of this block is to accept output commands from the CPU. It contains the
Initialization Command Word (ICW) registers and Operations Command Word (OCW) registers
which store the various control formats for device operation. This function block also allows the
status of the 8259A to be transferred onto the Databus.
[5]
VBMB - 007
2.2.6 The Cascade Buffer/Comparator

This Function block stores and compares the IDs of all 8259As used in the system. The
associated 3 I/o pins (CASO-2) are outputs when the 8259A is used as a master and are inputs
when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave
on to the CASO-2 lines. The slave thus selected will send its preprogrammed subroutine address
onto the Databus during the next one or two consecutive INTA pulses.
2.2.7 Cascading PICs
The 8259A can be easily interconnected in a system of one master with up to eight
slaves to handle upto 64 priority levels. This is shown in fig.2-2.
The master controls the slaves through the 3 line cascade bus. The cascade bus acts like
chip selects to the slaves during the INTA sequence.
In a cascade configuration , the slave interrupt outputs are connected to the master
interrupt request inputs. When a slave request line is activated and afterwards acknowledged ,
the master will enable the corresponding slave to release the device routine address during bytes
2 and 3 of INTA (Byte 2 only for 8086/8088).
The cascade bus lines are normally low and will contain the slave address code from
the trailing edge of the first INTA plus to the trailing edge of the third plus. Each 8259 in the
system must follow a separate initialization sequence and can be programmed to work in a
different mode. An EOI command must be issued twice. Once for the master and once for the
corresponding slave. An address decoder is required to activate the chip select (CS) input of each
8259A.
[6]
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[7]
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8259 PINS AND THEIR FUNCTIONS

Symbol
Pin No
Name and function
Vcc
28
Supply: +5v Supply.
GND
14
GROUND
CS
CHIP SELECT: A low on this pin enables RD and WR

communication between the CPU and the 8259A. INTA functions are
independent of CS.
WR
WRITE: A low on this pin when CS is low enables the 8259A to

accept command words from the CPU.
RD
READ: A low on this pin when CS is low enables the 8259A to

release status onto the data bus for the CPU.
D7-D0
4-11
BIDIRECTIONAL DATA BUS: Control status and Interrupt-vector

information is transferred via this bus.
CASOCAS2
12,13,
15
CASCADE LINES: The CAS lines from a private 8259A bus to

control a multiple 8259A structure. These pins are outputs for a master
8259A and inputs for a slave 8259A.
SP/EN
16
SLAVE PROGRAM/ENABLE BUFFER:This is a dual function pin.

When in the Buffered Mode it can be used as an output to control
buffer transceivers (EN) . When not in the buffered mode it is used as
an input to designate a master (SP=1) or slave (SP=0).
INT
17
INTERRUPT : This pin goes high whenever a valid interrupt request

is asserted. It is used to interrupt the CPU, thus it is connected to the
CPUs interruption pin.
IROIR7
18-25
INTERRUPT REQUESTS: Asynchronous inputs. An interrupt

request is executed by raising as IR input (low to high), and holding it
high until it is acknowledged (Edge Triggered Mode), or just by a high
level on an IR input (Level Triggered Mode).
INTA
26
INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A

interrupt-vector data onto the data bus by a sequence of interrupt
acknowledge pulses issued by the CPU.
A0
27
A0 ADDRESS LINE: This pin acts in conjunction with the CS , WR

and RD pins. It is used by the 8259A to decipher various command
words the CPU writes and status the CPU wishes to read . It is
typically connected to the CPU A0 address line (A1 address line) (A1
for 8086,8088) .
[8]
VBMB - 007
CHAPTER - 3
CIRCUIT DETAILS
VBMB - 007 is designed to familiarise 8259 interfacing . This board has one unique feature
called simulation mode. That is the board can be operated in 2 modes normal or software mode
and manual or simulated mode. These modes are selected by means of jumper. In software mode
the 8259 is interfaced directly to the CPU as shown in figure 3.1. In simulated or manual mode
the user has to substitute the CPU. That is, we have to give Interrupt Acknowledge manually
through a latch and see the interrupt sequence. This lets the user understand how 8259 responds
to an interrupt request. This mode is shown in figure 3 . 2 .
[9]
VBMB - 007
To show the response of the 8258 during each interrupt sequence, the data lines are displayed
using a buffer.
3 . 1 CIRCUIT IMPLEMENTATION:
Design of this interrupt controller interface is quite simple . The 8259 interacts with
the CPU by D0-D7 , CS , RD , WR ,A0 ,INT, INTA .Description of the rest of pins of 8259 are
given below.
CASO-CAS2 - Cascade lines (pin 12, pin 13 and pin 15).
Private 8259 bus to control a multiple 8259 structure. These pins are left free.
SP/EN
- Slave program/Enable buffer (Pin 16).

In buffered mode , it can be used to control buffer transceivers (EN) . In other
modes, indicates whether a master (SP=1) or a slave (SP=0) 8259. It is pulled
high using a 3.3 k resistor.
[ 10 ]
VBMB - 007
IRO-IR&
- INTERRUPT REQUESTS.
In VBMB-007 these pins are connected to the switch settings so that interrupt
requests can be given manually. These interrupt request are also terminated at a 10 pin connector.
A latch 74LS273 (U3) is provided on-board, which transfers the ststus of the data bus
to glow the LEDS. This is meant for demonstration purposes.
3.2 I/O DECODING:

The Programmable Interrupt Controller, data read latch, data display latch, Interrupt
acknowledge latch, Interrupt clear, and Interrupt pol latch are selected using a 3-to-8 decoder
74LS138. Pin 1, Pin 2 and Pin 3 of 74LS138 are tied to the address lines A3,A4 and A5
respectively . Address lines A7 and A6 are NANDed and the NAND gate output is connected to
pin 5. Similarly IOW and IOR signals are NANDed and the NAND gate output is connected
to pin 6. Pin 4 of 74LS138 is grounded.
Address line A1 is connected to input A0 of 8259 . So 8259 is selected with the address
with the address C0 and C2.
A7
A6
A5
A4
A3
A2
A1
A0
= C0 (Hex)
= C2 (Hex)
Interrupt Acknowledge Latch is selected with address.

A7 A6
A5
A4
A3
A2
A1
A0
0
= C8 (Hex)
[ 11 ]
VBMB - 007
Other latches and buffers are selected as follows
A7
A6
A5
A4
A3
A2
A1
A0
= Do; Data read

buffer.
= D8; Interrupt
poll latch
= E0; Interrupt
clear latch.
The Data display latch is clocked as and when the PIC is selected . Thus we can see the data that
is inputted to or outputted from the 8259.
NOTE:
If VBMB -007 is interfaced with a microprocessor kit, which has got on-board PIC 8259,
then IC has to be removed or disabled using jumpers.
[ 12 ]
VBMB - 007
CHAPTER - 4
PROGRAMMING THE 8259A
The normal sequence of events during an interrupt depends on the type of CPU being used.
The events occur as follows in an 8080/85AH system:
1)
One or more of the INTERRUPT REQUEST lines (IR0 -IR7) are raised high,
setting the corresponding IRR bit(s).
2)
The 8259A evaluates these requests and sends an INT to the CPU, if appropriate.
3)
The CPU acknowledges the INT and responds with an INTA pulses .
4)
Upon receiving an INTA from the CPU group, the highest priority ISR bit is
set and the corresponding IRR bit is reset. The 8259 will also release a CALL
instruction code (1100 1101) onto the 8-bit data bus through its D7-D0 pins.
5)
This CALL instruction will initiate two more INTA pulses to sent to the 8259A
from the CPU group.
6)
These two INTA pulses allow the 8259A to release its preprogrammed
subroutine address onto the data bus. The lower 8-bit address is released at the
first INTA pulse and the higher 8-bit address is released at the second INTA
pulse.
7)
This completes the 3 byte CALL instruction released by the 8259A . In the AEOI
mode (Auto End of Interrupt) the ISR bit is reset at the end of the third INTA
pulse. Otherwise the ISR bit remains set until an appropriate EOI command is
issued at the end of interrupt sequence.
[ 13 ]
VBMB - 007
The events occurring in 8086/88 are the same until step-3 as above
4)
Upon receiving an INTA from the CPU group, the highest priority ISR bit is set
and the corresponding IRR bit is reset . The 8259A does not drive the data bus
during this cycle.
5)
The 8086/88 will initiate a second INTA pulse. During this pulse, the 8259A
releases an 8-bit pointer onto the data bus where it is read by the CPU.
6)
This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the
end of the second INTA pulse. Otherwise, the ISR bit remains set until an
appropriate EOI command is issued at the end of the Interrupt subroutine
The 8259 accepts two types of command words generated by the CPU.
i)
Initialization Command Words (ICWS):
Before the normal operation can begin, each 8259 in the system must be
initialized using 2 to 4 bytes of ICWS.
ii)
Operation Command Words (OCWS):
These are the command words which command the 8259 to operate in various interrupt
modes. These modes are:
a) Fully nested mode
b) Rotating priority mod
c) Special mask mode
d) Polled mode
The OCWS can be written into the 8259 any time after initialization.
[ 14 ]
VBMB - 007
4.1 INITIALISATION COMMAND WORDS:

ICW1: The format of ICW1 is
Whenever a command is issued with A0=0 and D4=1, this is interpreted as ICW1. The ICW1
for the following specifications,
* ICW4 needed
* Single 8259
* CALL address interval of 4
* Edge triggered mode
* A7 A6 A5 = 0 0 0
is 17 (hex).
[ 15 ]
VBMB - 007
ICW2:
ICW2 is issued following ICW1 with A0=1. Its format is,
As is explained already, during an interrupt sequence with 8080/8085 CPU, the CPU releases
three INTA pulses. During the first INTA pulse the CALL opcode is enabled onto the databus.
The content of the first interrupt vector byte is,
1
During the second INTA pulse, the lower address of the appropriate service routine is enabled
onto the data bus. When interval=4 bits (D2 of ICW1=1), A5-A7 are programmed while A4-A0
are automatically inserted by the 8259. When interval = 8 bits (D2 of ICW2=0), only A6 and A7
are programmed while A0-A5 are automatically inserted.
[ 16 ]
VBMB - 007
The content of second interrupt vector byte is,

IR
INTERVAL=4
IR
D7 D6 D5 D4 D3 D2 D1 D0
INTERVAL = 4
D7 D6 D5 D4 D3 D2 D1 D0
A7 A6 A5 1
0 0
A7 A6 1
0 0
A7 A6 A5 1
0 0
A7 A6 1
0 0
A7 A6 A5 1
0 1
0 0
A7 A6 1
0 0
A7 A6 A5 1
0 0
0 0
A7 A6 1
0 0
A7 A6 A5 0
1 1
0 0
A7 A6 0
0 0
A7 A6 A5 0
1 0
0 0
A7 A6 0
0 0
A7 A6 A5 0
0 1
0 0
A7 A6 0
0 0
A7 A6 A5 0
0 0 0
A7 A6 0
0 0
During the third INTA pulse, the higher address of the interrupt service routine, which was
programmed as ICW2 is enabled onto the bus.
Thus with the program segment,
4100
4102
4104
4106
3E
D3
3E
D3
17
C0
50
C2
MVI
OUT
MVI
OUT
A,17
OC0H
A,50
OC2H
the interrupt service routine starts at location 5000 (hex) when 8259 is interrupted at IRO,
and the jump address is 5004 (hex) when 8259 is interrupted at IR1 and so on.
Note that for ICW1,A0=0 and for ICW2, A0=1.
Since A0 input of is connected to address line A1 ICW1 should be addressed to C0" and ICW2
should be addressed to C2.
[ 17 ]
VBMB - 007
In the 8086/8088 mode only two interrupt acknowledge cycles are issued by the processor and
no CALL opcode is sent to the processor. On the first INTA pulse 8259 does not issue any data
to the processor. On the second INTA
pulse 8259 will send a byte of data with the
acknowledged interrupt code to the processor.
The content of interrupt vector byte for 8086/8088 system mode
D7
D6
D5
D4
D3
D2
D1
D0
IR7
T7
T6
T5
T4
T3
IR6
T7
T6
T5
T4
T3
IR5
T7
T6
T5
T4
T3
IR4
T7
T6
T5
T4
T3
IR3
T7
T6
T5
T4
T3
IR2
T7
T6
T5
T4
T3
IR1
T7
T6
T5
T4
T3
IR0
T7
T6
T5
T4
T3
In this mode, A15-A11 are inserted in the five most significant bits of the vectoring byte and the
8259 sets the three least significant bits according to the interrupt level. Also note that the state
of
the ADI mode control is ignored and A5-A10 are unused in this mode.
[ 18 ]
VBMB - 007
ICW3: (MASTER DEVICE)

This word is read only when there is more than one 8259, in which case SNGL=0 (D1 of
ICW1=0)
Issued with A0=1, when a bit=1, it indicates that IR input has a slave. When a bit=0, it means
that IR input does not have a slave. The master will then release byte 1 of call sequence (80/85
system) and will enable the corresponding slave to release bytes 2 and 3 through cascade lines
(for 86/88 system, only byte 2).
ICW3: (SLAVE DEVICE)
[ 19 ]
VBMB - 007
* -SLAVE ID = CORRESPONDING MASTER IR INPUT

In the slave mode bits 2-0 identify the slave. The slave compares its cascade input with these
bits
and if they are equal bytes 2 and 3 of the call sequence (or just byte 2 for 8086/8088
system) are released by it on the data bus.
ICW4:
ICW4 is issued with A0=1. Proceeding with the initialisation of 8259 with AUTO EOI, NON
BUFFERED MODE with SFNM=0 for 8080/8085 system mode,
[ 20 ]
4100
4102
4104
4106
4108
410A
:
3E 17
D3 C0
3E 50
D3 C2
3E 02
D3 C2
:
ORG
MVI
OUT
MVI
OUT
MVI
OUT
VBMB - 007
4100H
A,17
0C0H
A,50
0C2H
A,02
0C2H
4.2 OPERATION COMMAND WORDS (8259A):

After the ICWS are programmed into the 8259, the chip is ready to accept interrupt requests
at its input lines. However to specify the mode of operation it requires the Operation Command
Words be written into it.
OCW1:
Issued with A0=1, this is used to mask the interrupts.

To enable all the interrupt request lines the command word is 00.
The following program will initialize the 8259 in an 8080/8085 system.
[ 21 ]

4100
4102
4104
4106
4108
410A
410C
410E
4110
3E
D3
3E
D3
3E
D3
3E
D3
76
17
C0
50
C2
02
C2
00
C2
ORG
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
HLT
VBMB - 007
4100H
A,17
0C0H
A,50
0C2H
A,02
0C2H
A,00
0C2H
Execute the program. If you press the IR0 switch the system is interrupted and the CPU jumps
to address 5000H. You may verify this by putting the opcode CF(hex) at location 5000H. So on
interrupt, the system is automatically reseted.
[ 22 ]
VBMB - 007
OCW2:
[ 23 ]
VBMB - 007
EXAMPLE -1:
To initialize 8259 with the following specifications.

*
*
*
*
*
*
*
*
*
*
*
ICW4 needed
Single 8259
Interval of 4
Edge triggered mode
A7 A6 A5 = 0 0 0
Interrupt service routine address for IRO:5000H
8085 mode
Normal EOI
Non buffered mode (Since we are not using buffers)
Not special fully nested mode
Mask all interrupts except IR0
the program is,
4100
4102
4104
4106
4108
410A
410C
410E
4110
3E
D3
3E
D3
3E
D3
3E
D3
76
17
C0
50
C2
00
C2
FE
C2
ORG
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
HLT
4100H
A,17
0C0H
A,50
0C2H
A,00
0C2H
A,FE
0C2H
If you press the switch IR0, the CPU jumps to location 5000H. 8259 will not accept any more
interrupt at IR0 since AEOI is not set. The End of interrupt command should be given through
OCW2 as,
ORG 5000H
5000 3E
20
MVI A,20
5002 D3
C0
OUT 0C0H
5004 CF
RST 1
Note that non specific EOI command is given.
[ 24 ]
VBMB - 007
In fully nested mode, the interrupt requests are ordered in priority from 0 through 7 (0 highest).
But in some applications there are a number of interrupting devices of equal priority. In this
mode a device after being serviced receives the lowest priority. This is known as rotating
priority.
[ 25 ]
VBMB - 007
4.3 SPECIAL MASK MODE:

If an interrupt request is acknowledged and an End of Interrupt Command did not reset its IS bit
(i.e., while executing a service routine) the 8259A would have inhibited all lower priority
requests with no easy way for the routine to enable them. But some applications may require an
interrupt service routine to dynamically alter the system priority structure during its execution
under software control.
This is where the Special Mask mode comes in. In the Special Mask mode, when a mask bit
is set in OCW1, it inhibits further interrupts at that level and enables interrupts from all other
levels (lower as well as higher) that are not masked. Thus any interrupts may be selectively
enabled by loading the mask register.
EXAMPLE - 2: To program the 8259 in special mask mode.
Enter the following program, which will work as Interrupt service routine.
5000
5002
5004
3E
D3
CF
FD
C2
ORG
MVI
OUT
RST
5000
A,FD ;Enable IR1 only
0C2H
1
Execute the following program which initialise 8259, with normal EOI.
4101
4102
4104
4106
4108
410A
410C
410E
4110
4112
4114
3E
D3
3E
D3
3E
D3
3E
D3
3E
D3
76
17
C0
50
C2
00
C2
00
C2
68
C0
ORG
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
HLT
4101H
A,17
0C0H
A,50
0C2H
A,00
0C2H
A,00
0C2H
A,68 ;Set Special Mask
0C0H ;mode in OCW3
Press the switch IR0, The CPU jumps to 5000H and executes the program there. Normally, since
no EOI command is given 8259 will not accept further interrupts. However due to special mask
mode 8259 will accept interrupt only at IR1, since only IR1 is enabled at that location. You may
verify this.
[ 26 ]
VBMB - 007
4.4 POLL COMMAND:

In this mode, the INT output is not used or the microprocessor internal enable flipflop is reset
disabling its interrupt input. Services to devices is achieved through software by a Poll
Command. The Poll Command is issued by setting p=1 in OCW3. The 8259 treats the next RD
pulse to the 8259 as an interrupt acknowledge, sets the appropriate IS bits if there is a request and
reads the priority level.
The word enabled onto the databus during RD is,
D7
D6
D5
D4
D3
D2
D1
D0
M2
M1
M0
W0-W2
- Binary code of the highest priority level requesting service.
- Equal to 1 if there is a request.
EXAMPLE - 3:
The program given below, initializes 8259 in the Polling mode, reads the word enabled onto the
data bus and checks for an interrupt request. If there is any, it jumps to corresponding interrupt
service routine. (This program is written to check only interrupt by IRO input).
4100
4101
4103
4105
4107
4109
410B
410D
410F
4111
4113
4115
4117
4119
411B
411C
F3
3E
D3
3E
D3
3E
D3
3E
D3
3E
D3
3E
D3
DB
47
E6
17
C0
50
C2
02
C2
00
C2
40
C0
0C
C0
C0
80
ORG
DI
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
LOP: MVI
OUT
IN
MOV
ANI
4100
A,17
0C0H
A,50
0C2H
A,02
0C2H
A,00
0C2H
A,40
0C0H
A,0C
0C0H
0C0H
B,A
80
[ 27 ]

411E
4120
4123
4124
4126
FE
C2
78
E6
FE
80
15
4128 CA
412B 76
412C CF
2C
41
07
00
VBMB - 007
CPI
JNZ
MOV
ANI
CPI
41
JZ
HLT
RES: RST
80
LOP
A,B
07
00
RES
1
Execute the program and verify that, if you press IR0, the system gets reseted.
4.5 READING THE 8259 STATUS:

The input status of several internal registers can be read to update the user information on the
system via 0CW3.
With the program segment
3E
0A
D3
C0
DB
C0
:
:
the content of interrupt request register can be read. IRR ia an 8 bit which contains the levels that
are requesting service.
The content of 8 bit In-Service register (ISR), which contains the priority levels that are being
serviced can be read with the program segment.
3E
D3
DB
:
0B
C0
C0
:
For reading the Interrupt Mask Register (IMR) which contains the interrupt request lines which
are masked, no OCW3 is needed. The output databus will contain the IMR whenever RD is
active and A0=1.
Polling overrides status read when P=1 ,RR=1 in OCW3
[ 28 ]
VBMB - 007
4.6 PROGRAM TO TEST THE VBMB -007 IN SIMULATED MODE

4100
4102
4104
4106
4108
410A
410C
410E
4110
3E
D3
3E
D3
3E
D3
3E
D3
DB
17
C0
50
C2
02
C2
00
C2
D8
MVI
OUT
MVI
OUT
MVI
OUT
MVI
OUT
WAIT :IN
4112
4114
4117
4119
411B
E6
CA
3E
D3
3E
01
10 41
01
E0
01
ANI
JZ
MVI
OUT
MVI
01
WAIT
A,01
E0
A,01
411D
411F
4121
4123
4126
4129
D3
3E
D3
CD
CD
3E
C8
00
C8
00 45
00 45
01
OUT
MVI
OUT
CALL
CALL
MVI
C8
A,00
C8
DELAY
DELAY
A,01
4128
412A
412C
412E
4131
4134
D3
3E
D3
CD
CD
3E
C8
00
C8
00 45
00 45
01
OUT
MVI
OUT
CALL
CALL
MVI
C8
A,00
C8
DELAY
DELAY
A,01
4136
4138
413A
413C
4500
4503
4504
4505
4506
4509
D3
3E
D3
76
21
2B
7C
B5
C2
C9
C8
00
C8
OUT
MVI
OUT
HLT
FF FF DELAY:LX1
LOOP1:DCX
MOV
ORA
03
45
JCZ
RET
A,17
C0
A,50
C2
A,02
C2
A,00
C2
D8
;Initialize the
; PIC
;Check if any
;int. request
;has been given.
;Clear interrupt
;To give first
;int. acknowledge.
;Give second
;int. acknowledge.
;Give third
; int. acknowledge.
C8
A,00
C8
H, FFFF
H
A,H
L
LOOP1
[ 29 ]
VBMB - 007
PROGRAM DESCRIPTION:
By executing the above program you can see what happens after the interrupt request is given
to PIC. Here interrupt acknowledge is given by outputting 1 and 0 to C8 port. That is, instead of
the processor, we are giving the interrupt acknowledge.
Enter the program and execute it. Give any of the interrupt requests by pressing NC NO switch.
You can see CD (1100 1101) at the LEDs and the locations according to the interrupt request
one by one.
[ 30 ]
VBMB - 007
APPENDIX-A
PROGRAMS IN 8086 ASSEMBLY LANGUAGE

Example 1:
To initialize the 8259 with the following specification
*
ICW 4 needed.
*
Single 8259.
*
Interval of 4.
*
Edge triggered mode.
*
A7 A6 A5 = 000.
*
Initialize to type 8 interrupt.
*
8086 mode.
*
Normal EOI.
*
Non-buffered mode (Since we are not using buffers).
*
Not special fully-nested mode.
*
Mask all interrupts except IRQ 0.
PROGRAM:
1000
1002
1004
1006
1008
100A
100C
100E
1010
1011
B0
E6
B0
E6
B0
E6
B0
E6
FB
EB
17
C0
08
C2
01
C2
FE
C2
FE
ORG 1000
MOV AL,17
OUT C0,AL
MOV AL,08
OUT C2,AL
MOV AL,01
OUT C2,AL
MOV AL,FE
OUT C2,AL
STI
HERE:SJMP HERE
INTERRUPT VECTOR:
0000: 0020
0000: 0021
0000: 0022
0000: 0023
00
12
00
00
[A-1]
VBMB - 007
INTERRUPT SERVICE ROUTINE:

1200
1202
1204
B0
E6
CD
20
C0
02
MOV
OUT
INT
AL,20
C0,AL
2
PROGRAM DESCRIPTION:
The main program initializes the 8259 to the above specifications. The program initializes
the 8259 to type 8. So the interrupt vector for interrupt IRO is
0000: 0020
0000: 1200H
So at 0000:0020, enter the address

If the ISR is at 0:1200
In the ISR, non specific EOI command is given. In fully nested mode, the interrupt requests
are ordered in priority from 0 through 7 (0 highest). But in some applications there are a number
of interrupting devices of equal priority. In this mode, a device after being serviced receives the
lowest priority, This is known as Rotating priority,
[A-2]
VBMB - 007
Example 2: TO PROGRAM THE 8259 IN SPECIAL MASK MODE

Enter the following program which will work as Interrupt Service Routine.
1200
1202
1204
B0
E6
CD
FD
C2
02
MOV
OUT
INT
AL,FD
C2,AL
2
The main program initializes the 8259 with normal EOI.
1000
1002
1004
1006
1008
100A
100C
100E
1010
1012
1014
1015
B0
E6
B0
E6
B0
E6
B0
E6
B0
E6
FB
EB
17
C0
08
C2
01
C2
00
C2
68
C0
FE
ORG
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
STI
JMP
1000
C2,AL
C2,AL
C2,AL
C2,AL
AL,01
C2,AL
AL,FE
C2,AL
HERE
At the interrupt vector 0000:0020 give the location for ISR as follows.
0020
0021
0022
0023
00
12
00
00
Press the switch IR0. The CPU control is transferred to ISR. Since no EOI command is
given the 8259 will not accept further interrupts. However due to special mask mode, 8259 will
accept interrupt only at IRI, since only is enabled at that location.
[A-3]
VBMB - 007
Example 3:
The program given below, initializes 8259 in the polling mode, reads the word enabled on to the
data bus and checks for an interrupt service routine.If there is any , it jumps to corresponding
interrupt service routine.(This program is written to check only interrupt by IR0 input).
1000
1001
1003
1005
1007
1009
100B
100D
100F
1011
1013
1015
1017
1019
101B
101D
101F
1021
1023
FA
B0
E6
B0
E6
B0
E6
B0
E6
B0
E6
B0
E6
E4
A8
74
24
3C
74
17
C0
08
C2
01
C2
00
C2
40
C0
0C
00
C0
80
F6
07
00
2B
CD
02
CLI
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
WAIT: IN
TEST
JZ
ANA
CMP
JZ
AL,17
C2,AL
C2,AL
C2,AL
AL,01
C2,AL
C2,AL
AL,FE
C2,AL
AL,C0
AL,C0
AL,80
WAIT
AL,07
AL,00
ISR
ISR
1050
INT 2
Press the switch IRO. The CPU control is transferred to ISR. Since no EOI command is given
the 8259 will not accept further interrupts. However due to special mask mode, 8259 will accept
interrupt only at IRI, since only IRI is enabled at that location.
[A-4]
VBMB - 007
APPENDIX-B
PROGRAMS IN 8031 ASSEMBLY LANGUAGE

EXAMPLE
1:
To test VBMB-007 in polled method.

8100 75
74
90
F0
90
74
F0
F0
90
74
F0
74
F0
E0
F8
30
E8
54
B4
12
80
Interrupt Service
8150 74
12
80
A8
16
FF
00
FF
00
C2
FF
40
C0
C0
0C
E0
F8
07
00
03
81
50
FE
Routine;
00
00
20
FE
MOV
MOV
MOV
MOVX
MOV
MOV
MOVX
MOVX
MOV
MOV
MOVX
WAIT:MOV
MOVX
MOVX
MOV
JNB
MOV
ANL
CJNE
LCALL
HERE:
SJMP
1E, # 00
A,# 16
DPTR ,# FFC0
@DPTR ,A
DPTR ,#FFC2
A ,# 00
@DPTR , A
@DPTR , A
DPTR , # FFC0
A , # 40
@DPTR ,A
A, # 0C
@DPTR , A
A, @DPTR,A
R0 ,A
E7 WAIT
A,R0
A;# 07
A,# 00,HERE
ISR
HERE
MOV
LCALL
STOP: SJMP
a,# 00
0020
STOP
Since 8259 cannot support the interrupt structure of 8031 ,8031 can be interfaced to 8259
only in polled method.The above program checks in the interrupt request register for
interrupt.Note that this has been written only for interrupt request 0.
[B-1]
VBMB - 007
APPENDIX - C
IC PINOUTS
[C-1]
VBMB - 007
APPENDIX - D
CIRCUIT DIAGRAMS
[D-1]
VBMB - 007
[D-2]
VBMB - 007
APPENDIX - E
COMPONENT LAYOUT
[E-1]

VBMB - 007

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8259 INTERFACE BOARD

(Model No : VBMB - 007)

Technical Clarification /Suggestion :

Vi Microsystems Pvt. Ltd.,

1.USE OF INTERRUPTS IN MICROCOMPUTER SYSTEMS...........................1

PROGRAMS IN 8086 ASSEMBLY LANGUAGE ....................A-1

PROGRAMS IN 8031 ASSEMBLY LANGUAGE......................B-1

8259 INTERFACE BOARD

USE OF INTERRUPTS IN MICROCOMPUTER SYSTEMS

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8259 INTERFACE BOARD

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8259 INTERFACE BOARD

The special features of 8259 are,

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8259 INTERFACE BOARD

8259 BLOCK DIAGRAM

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8259 INTERFACE BOARD

2.2 FUNCTIONAL BLOCKS OF 8259:

2.2.3 Interrupt Mask Register

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8259 INTERFACE BOARD

2.2.6 The Cascade Buffer/Comparator

2.2.7 Cascading PICs

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8259 INTERFACE BOARD

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8259 INTERFACE BOARD

8259 PINS AND THEIR FUNCTIONS

Name and function

Supply: +5v Supply.

CHIP SELECT: A low on this pin enables RD and WR

WRITE: A low on this pin when CS is low enables the 8259A to

READ: A low on this pin when CS is low enables the 8259A to

BIDIRECTIONAL DATA BUS: Control status and Interrupt-vector

CASCADE LINES: The CAS lines from a private 8259A bus to

SLAVE PROGRAM/ENABLE BUFFER:This is a dual function pin.

INTERRUPT : This pin goes high whenever a valid interrupt request

INTERRUPT REQUESTS: Asynchronous inputs. An interrupt

INTERRUPT ACKNOWLEDGE: This pin is used to enable 8259A

A0 ADDRESS LINE: This pin acts in conjunction with the CS , WR

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8259 INTERFACE BOARD

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8259 INTERFACE BOARD

- Slave program/Enable buffer (Pin 16).

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8259 INTERFACE BOARD

3.2 I/O DECODING:

Interrupt Acknowledge Latch is selected with address.

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8259 INTERFACE BOARD

Other latches and buffers are selected as follows

= Do; Data read

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8259 INTERFACE BOARD

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8259 INTERFACE BOARD

Initialization Command Words (ICWS):

Operation Command Words (OCWS):

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8259 INTERFACE BOARD