A 3GHz Subthreshold CMOS Low Noise Amplifier

Hanil Lee and Saeed Mohammadi

School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, 47907, U.S.A.
Abstract This paper presents an integrated 3GHz ultra
low power CMOS Low Noise Amplifier (LNA) based on a
Cascode topology where both MOS transistors are biased in
subthreshold region. At 160W DC power consumption and
power supply of 0.6V, this LNA has a measured power gain
of 4.5dB and noise figure of 6.3dB. At 400W power
consumption, the LNA delivers a power gain of 9.1dB and a
noise figure of 4.7dB. The measured IIP3 under 400W
power dissipation is -11dBm while the input and output
matching is better than -13dB. By using a figure of merit that
contains the effect of amplifier noise figure, gain, linearity,
DC power consumption and operating frequency, we have
shown that this amplifier is superior to conventional CMOS
LNA designs reported in the literature.
Index Terms Low power, subthreshold, CMOS, low
noise amplifiers (LNAs).

I. INTRODUCTION
By the advent of sensor networks, there is a strong
demand for ultra low power RFICs to extend the battery
life of the wireless sensor motes used in these applications.
To date, most ultra low power motes have used simple
architectures such as super-regenerative and sub-sampling
receivers. In sub-sampling receivers, passive narrow-band
RF filters are used to suppress the noise-folding effects
associated with these receivers [1]-[3]. These high-Q
narrow-band filters are made with the help of integratable
high-Q (>1000) resonators, such as FBARs and RFMEMS.
Although sub-sampling receivers using passive high-Q
resonators consumes very low power, they require rather
expensive passive components and are only used for low
data-rate wireless applications. For high data-rate and
low-cost, low-power applications, standard CMOS
homodyne or super-heterodyne RF receivers are preferred.
In these standard architectures, it is important to
substantially reduce DC power consumption of CMOS
RFICs with other performances properly maintained. This
paper proposes a new design technique based on
subthreshold biasing of MOS transistors to lower the DC
power dissipation of RF receivers.
Traditionally, CMOS LNAs have been designed with
MOS transistors operating in strong inversion
(superthreshold
operation)
regime
rather
than
subthreshold, since current MOS transistor noise models
predict that the noise in subthreshold regime increases

significantly with decreasing drain current [4][5].

However, unlike common belief, the minimum noise
figure of advanced deep sub-micron MOS transistors in
subthreshold regime remains constant [6][7]. As a result,
the noise figure of the amplifier with CMOS transistors
biased in subthreshold does not degrade drastically as DC
power dissipation is reduced. Furthermore, the gain to DC
power consumption ratio of LNAs in subthreshold regime
is higher than that of superthreshold, since in subthreshold
regime, drain current has an exponential dependence to
the gate-source voltage. By increasing the width of the
transistors operating in subthreshold, the high gain can
still be maintained, while DC power consumption is
substantially reduced.
In order to demonstrate the advantages of subthreshold
CMOS design, we have implemented a 3GHz CMOS
LNA in a 0.13m technology that operates in
subthreshold regime and consumes only a few hundreds
of W of DC power. While the amplifier power gain to
DC power dissipation ratio improves in subthreshold, the
noise figure of the amplifier does not degrade drastically
in subthreshold regime. The overall performance of the
LNAs measured by a figure of merit (FOM) defined in
VDD
Output
Matching
LD
Input
Matching

Bias-T

PAD

CD

M2

LOS
COP1 COP2

PAD

CPAD
50

M1
LIS

50

CPAD

CIP1

CIP2
LS
Bias

Bias
LNA Core Schematic

VDD

LD

IN

LOS

OUT

LIS
LS
BIAS

Fig. 1. Circuit schematic of the proposed Cascode 3GHz CMOS

LNA with input/output test environments, where MOSFETs are
biased in subthreshold region for ultra low power RF
applications.

[8][9] is found to be higher for our subthreshold LNA

design compared to those reported for standard CMOS
LNAs.
Gain [dB]

To achieve ultra low power performance, we have

designed a Cascode LNA with NMOS transistors (M1 and
M2) biased in subthreshold region (see Fig. 1). W/L ratios
of the two transistors are increased and optimized to
increase the gain of the amplifier and help matching the
input impedance to 50. A source degeneration inductor
(LS) also facilitates the input matching to 50, and
provides good linearity and high reverse-isolation, which
helps with the amplifier stability. Transistors M1 and M2
are biased in subthreshold (threshold voltage VTH ~
0.45V), while the supply voltage (VDD) is lowered to
about 0.6V. Fig. 1 shows the circuit schematic of the
LNA along with a micrograph of the fabricated chip in
0.13m CMOS technology. LNA area is 1u2mm2
including the test pads.
To achieve high gain and low noise figure performance
with low power consumption, octagonal shaped inductors
are implemented using 4m thick Al top metals. A cross
hatch of deep trench (DT) lattice is used between a single
layer metal of inductors and conductive substrate to
reduce the capacitance to substrate, resulting in a decrease
in substrate loss and an increase in the inductor quality
factor and self-resonance frequency [10]. After design
optimization for 3GHz operation, turn to turn gap of
inductors is set to 5m, and the inductor LD, LS, LIS, and
LOS with values of 2.0nH, 8.4nH, 6.6nH, and 1.0nH are
used, respectively.
Due to the exponential dependence of IDS on VGS in
subthreshold, the ratio of transconductance to IDS (gm/IDS)
in subthreshold region is larger than that of strong
inversion region. The gm/IDS in strong inversion is
proportional to IDS-0.5, while it is constant value of
q/(n*kT) in subthreshold region, where q is the electronic
charge of 1.6x10-19 coulombs, k is Boltzmann constant, T
is the absolute temperature, and n = (gm+gmb)/gm (gmb:
transconductance due to body effect). By the same token,
the ratio of the amplifier gain to its DC power
consumption is higher in subthreshold than that of strong
inversion region.
Furthermore, one can show with analytical techniques
that the transistor minimum noise factor (Fmin-1) is
proportional to IDS-0.5 under strong inversion. The noise
figures becomes almost independent of drain current in
subthreshold regime except for extremely small current
values where it degrades drastically since cut-off
frequency (fT=gm/(CGS+CGD)) becomes smaller than

5
0
160uW
-5
400uW
-10
2.5

3.0

3.5

Frequency [GHz]

(a)
10
Noise Figure [dB]

II. CIRCUIT DESIGN

10

160uW
400uW

4
2.5

3.0

3.5

Frequency [GHz]

(b)
Fig. 2. Measured Gains and Noise Figures of LNA for different
DC power consumptions.

operating frequency in subthreshold region [7]. The

minimum noise factor behavior agrees with the
experimental results observed in [6]. It however contrasts
traditional CMOS noise models given by Van der Ziel [4]
and BSIM4.2.0 [5], which predict a sharp increase of Fmin.
Also note that Philips MOS11 model [11] mistakenly
predicts almost a zero Fmin in subthreshold region. Given
the advantages of subthreshold design, LNA circuit of Fig.
1 was implemented in 0.13m CMOS technology and was
then characterized and compared with the state of the art
low power LNAs from literature.
III. MEASUREMENT RESULT
The measurements are made on-wafer using 50
coplanar probes. Measured LNA gain and noise figure as
a function of DC power consumption are shown in Fig. 2.
The LNA has a 4.5dB gain and a 6.3dB NF at a supply
voltage of 0.6V, and a power consumption of 160W. To

order inter-modulation output signal power (IM3). Based

on these measurements plotted in Fig. 4 the input third
order intercept point (IIP3) of -11dBm is extrapolated.
A commonly used figure of merit (FOM) for low-power
LNAs is the ratio of power gain to dc power consumption
(Gain/Pdc). Our subthreshold LNA has a Gain/Pdc of
28.8dB/mW for the 160W LNA, and 22.6dB/mW for the
400W dc power. By comparison with other reported low
power LNAs shown in Table. I, this LNA achieves the
highest gain to Pdc ratio. To compare overall performance
of amplifiers, we have used an additional FOM which
includes the effect of amplifier gain, noise figure, linearity
(IIP3), operation frequency (fO) and DC power
consumption (Pdc) as follows [8][9].
Fig. 3. Measured S-parameters of LNA at 400W DC power
consumption.

authors best knowledge, this is the first time a fully

integrated 3GHz CMOS LNA with a power consumption
below 200W is reported. At 0.6V supply, a power gain
of 9.1dB and a noise figure of 4.7dB are measured while
the DC power consumption is only 400W.
Small-signal S-parameter measurement of the LNA
biased in subthreshold with 400W power dissipation are
shown in Fig. 3. While S21 of 9.1dB at 3GHz is achieved,
S11, S22, and S12 are better than -13dB, -20dB, and -33dB,
respectively.
Single-tone 1dB compression measurement and twotone large signal linearity measurement of the LNA under
the same bias condition with 400W power dissipation are
shown in Fig. 4. The input referred 1dB compression
point (P1dBin) was measured as -25dBm. A two-tone test
at 3GHz and 3.01GHz was performed to measure the
fundamental output signal power (Pout) and the third

Data from other state-of-the-art low power CMOS

LNAs are also provided in Fig. 5 and Table. I [9][12]-[18].
The comparison shows that this ultra low power
subthreshold LNA can provide better overall performance
than circuits designed in strong inversion in terms of gain,
noise figure, linearity, DC power consumption and
frequency of operation.
IV. CONCLUSION
An ultra low power CMOS Low Noise Amplifier
(LNA) using subthreshold design scheme in a standard
40

This LNA

Figure of Merit

Pout
-10.0

IM3

-20.0
-30.0
-40.0

Gain[dB]
IIP3[mW ]

)
( F  1) Pdc[mW ] Pdc[mW ] (1)

f
 10 log10 ( O )
1GHz

30

0.0

Pout & IM3 [dBm]

10 log10 (100

FOM

2004_Mohammadi

160uW

2004_Linten

400uW

2005_Chiu
2005_Wang

20

2005_Hsieh

2001_Gramegna
2004_Ohsato

10

-50.0

2003_Zencir

-60.0
-70.0

0
-80.0

P1dB_in = -25dBm

IIP3 = -11dBm

-90.0
-40

-35

-30

-25

-20

-15

-10

-5

10

100

Power Consumption [mW]

Pin [dBm]

Fig. 4. Measured IIP3 and P1dBin of LNA at 400W DC power

consumptions.

Fig. 5. Performance comparison graphs with previously published

low power CMOS LNA data using figure of merit versus DC
power consumption.

TABLE I
PERFORMANCES OF THIS LNA AT SEVERAL DC POWER CONSUMPTIONS AND THEIR COMPARISONS WITH
PREVIOUSLY PUBLISHED DATA. A FORMULA FOR FIGURE OF MERIT (FOM) IS IN EQUATION (1).

Previous LNAs

This
LNA

SUMMARIZED

Pdc=160W
Pdc=400W
[12] 2005RFIC_Wang
[13] 2005RFIC_Hsieh
[14] 2005ITMTT_Chiu
[15] 2004RFIC_Mohammadi
[16] 2004IMWCL_Ohsato
[17] 2004VLSI_Linten
[18] 2003IMTT_Zencir
[9] 2001JSSC_Gramegna

Vdd Idd Pdc

f
[GHz] [V] [mA] [mW]
3.00
0.6 0.26 0.16
3.00
0.6 0.67 0.40
0.96
1.2 0.60 0.72
5.00
0.6 1.50 0.90
5.20
- 3.60
5.80
1.8
- 4.50
1.60
1.5 5.00 7.50
5.50
0.6
- 1.00
0.44
2.5
- 12.50
0.90
- 4.95

0.13m CMOS technology is designed and implemented.

To substantially reduce the DC power consumption, the
proposed LNA uses oversized NMOS transistors which
are optimized to operate in the subthreshold region. At DC
power consumption of only 160W with 0.6V power
supply, this 3GHz LNA has a measured gain of 4.5dB and
noise figure of 6.3dB. This LNA when consuming 400W
with a 0.6V supply achieves a measured gain of 9.1dB
and noise figure of 4.7dB. Under this bias condition, the
measured IIP3 is -11dBm and the S11, S22, and S12 are
better than -13dB. This subthreshold LNA has the best
gain to DC power ratio and overall figure of merit (FOM)
[8][9] among recently published low power CMOS LNAs.
ACKNOWLEDGEMENT
The authors are grateful to the funding provided by
Tellab fellowship through Purdue Center for Wireless
Systems and Applications (CWSA) and DARPA
Technology for Efficient and Agile Microsystems
(TEAM) under project DAAB07-02-1-L430. The authors
wish to acknowledge helpful discussions and support of
Tae-young Choi at the University of Michigan and Dr.
Mark Johnson at Purdue University.
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Gain
[dB]
4.5
9.1
13.0
9.2
8.0
16.7
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9.2
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NF P1dBin IIP3 OIP3 Gain/Pdc FOM

[dB] [dBm] [dBm] [dBm] [dB/mW]
[]
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28.8
31.8
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