Circuit Design and Simulation with VHDL

second edition

Volnei A. Pedroni

The MIT Press

Cambridge, Massachusetts
London, England

6 2010 Massachusetts Institute of Technology

All rights reserved. No part of this book may be reproduced in any form by any electronic or mechanical means
(including photocopying, recording, or information storage and retrieval) without permission in writing from the
publisher.
For information about special quantity discounts, please email special_sales@mitpress.mit.edu
This book was set in Times New Roman on 3B2 by Asco Typesetters, Hong Kong.
Printed and bound in the United States of America.
Library of Congress Cataloging-in-Publication Data
Pedroni, Volnei A.
Circuit design and simulation with VHDL / Volnei A. Pedroni. 2nd ed.
p. cm.
Rev. ed. of: Circuit design with VHDL / Volnei A. Pedroni. 2004.
Includes bibliographical references and index.
ISBN 978-0-262-01433-5 (hardcover : alk. paper) 1. VHDL (Computer hardware description language).
2. Electronic circuit design. 3. System design. I. Pedroni, Volnei A. II. Title.
TK7885.7.P43 2010
2009045909
621.390 5dc22
10 9 8 7

6 5 4

3 2 1

Contents

Preface

xv

CIRCUIT-LEVEL VHDL

Introduction
1.1 About VHDL
1.2 VHDL Versions
1.3 Design Flow
1.4 EDA Tools
1.5 Translation of VHDL Code into a Circuit
1.6 Circuit Simulation
1.7 VHDL Syntax
1.8 Number and Character Representations in VHDL

3
3
3
5
5
6
7
8
8

Code
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10

Structure
Fundamental VHDL Units
VHDL Libraries and Packages
Library/Package Declarations
ENTITY
ARCHITECTURE
GENERIC
Introductory VHDL Examples
Coding Guidelines
VHDL 2008
Exercises

11
11
11
13
14
16
17
18
24
27
28

Data
3.1
3.2
3.3

Types
Introduction
VHDL Objects
Data-Type Libraries and Packages

31
31
31
36

viii

Contents

3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.22
3.23

Type Classications
Standard Data Types
Standard-Logic Data Types
Unsigned and Signed Data Types
Fixed- and Floating-Point Types
Predened Data Types Summary
User-Dened Scalar Types
User-Dened Array Types
Integer versus Enumerated Indexing
Array Slicing
Records
Subtypes
Specifying PORT Arrays
Qualied Types and Overloading
Type Conversion
Legal versus Illegal Assignments
ACCESS Types
FILE Types
VHDL 2008
Exercises

39
41
47
51
54
59
60
62
65
66
70
71
72
73
74
78
79
80
80
81

Operators and Attributes

4.1
Introduction
4.2
Predened Operators
4.3
Overloaded and User-Dened Operators
4.4
Predened Attributes
4.5
User-Dened Attributes
4.6
Synthesis Attributes
4.7
GROUP
4.8
ALIAS
4.9
VHDL 2008
4.10 Exercises

91
91
91
98
99
104
106
111
112
114
115

Concurrent Code
5.1
Introduction
5.2
Using Operators
5.3
The WHEN Statement
5.4
The SELECT Statement
5.5
The GENERATE Statement
5.6
Implementing Sequential Circuits with Concurrent Code

121
121
122
123
124
129
134

Contents

5.7
5.8
5.9
5.10
5.11

ix

Implementing Arithmetic Circuits with Operators

Preventing Combinational-Logic Simplication
Allowing Multiple Signal Assignments
VHDL 2008
Exercises

135
140
143
143
144

Sequential Code
6.1
Introduction
6.2
Latches and Flip-ops
6.3
PROCESS
6.4
The IF Statement
6.5
The WAIT Statement
6.6
The LOOP Statement
6.7
The CASE Statement
6.8
CASE versus SELECT
6.9
Implementing Combinational Circuits with Sequential Code
6.10 VHDL 2008
6.11 Exercises

151
151
152
153
154
159
161
165
168
169
171
172

SIGNAL and VARIABLE

7.1 Introduction
7.2 SIGNAL
7.3 VARIABLE
7.4 SIGNAL versus VARIABLE
7.5 The Inference of Registers
7.6 Dual-Edge Circuits
7.7 Making Multiple Signal Assignments
7.8 Exercises

177
177
177
178
180
185
187
190
193

II

SYSTEM-LEVEL VHDL

199

PACKAGE and COMPONENT

8.1 Introduction
8.2 PACKAGE
8.3 COMPONENT
8.4 GENERIC MAP
8.5 COMPONENT Instantiation with GENERATE
8.6 CONFIGURATION
8.7 BLOCK
8.8 VHDL 2008
8.9 Exercises

201
201
201
203
208
211
213
216
218
219

Contents

FUNCTION and PROCEDURE

9.1 Introduction
9.2 The ASSERT Statement
9.3 FUNCTION
9.4 PROCEDURE
9.5 FUNCTION versus PROCEDURE Summary
9.6 Overloading
9.7 VHDL 2008
9.8 Exercises

221
221
221
223
230
233
233
237
238

10

Simulation with VHDL Testbenches

10.1
Introduction
10.2
Simulation Types
10.3
Writing Data to Files
10.4
Reading Data from Files
10.5
Graphical Simulation (Preparing the Design)
10.6
Stimulus Generation
10.7
General VHDL Template for Testbenches
10.8
Type I Testbench (Manual Functional Simulation)
10.9
Type II Testbench (Manual Timing Simulation)
10.10 Type III Testbench (Automated Functional Simulation)
10.11 Type IV Testbench (Automated Timing Simulation)
10.12 Testbenches with Record Types
10.13 Testbenches with Data Files
10.14 Exercises

241
241
243
245
248
251
253
257
258
261
261
262
264
267
271

III

EXTENDED AND ADVANCED DESIGNS

275

11

VHDL Design of State Machines

11.1 Introduction
11.2 VHDL Template for FSMs
11.3 Poor FSM Model
11.4 FSM Encoding Styles
11.5 The State-Bypass Problem in FSMs
11.6 Systematic Design Technique for Timed Machines
11.7 FSMs with Repetitive States
11.8 Other FSM Designs
11.9 Exercises

277
277
279
289
291
292
298
312
312
313

12

VHDL Design with Basic Displays

12.1 Introduction
12.2 Basic LED/SSD/LCD Driver

319
319
322

Contents

12.3
12.4
12.5
12.6
12.7
12.8

xi

Playing with a Seven-Segment Display

Frequency Meter (with LCD)
Digital Clock (with SSDs)
Quick-Finger Game (with LEDs and SSDs)
Other Designs with Basic Displays
Exercises

327
330
337
340
345
346

13

VHDL Design of Memory Circuits

13.1 Introduction
13.2 Implementing Bidirectional Buses
13.3 Memory Initialization Files
13.4 ROM Design
13.5 RAM Design
13.6 External Memory Interfaces
13.7 Exercises

351
351
352
353
357
362
368
371

14

VHDL Design of Serial Communications Circuits

14.1 Introduction
14.2 Data Serializers/Deserializers
14.3 PS2 Interface
14.4 I 2 C Interface
14.5 SPI Interface
14.6 TMDS Interface
14.7 Video Interfaces: VGA, DVI, and FPD-Link
14.8 Exercises

375
375
376
380
388
399
409
419
419

15

VHDL Design of VGA Video Interfaces

15.1
Introduction
15.2
VGA Connector
15.3
DDC and EDID
15.4
Circuit Diagram
15.5
Control Signals
15.6
Pixel Signals
15.7
Setup for the Experiments
15.8
Comments on VHDL Code for VGA Systems
15.9
Hardware-Generated Image
15.10 Image Generation with a File and On-Chip Memory
15.11 Arbitrary Image Generation with a File and O-Chip Memory
15.12 Image Equalization with Gamma Expansion
15.13 Exercises

423
423
424
425
426
428
429
430
430
431
435
438
441
441

xii

Contents

16

VHDL Design of DVI Video Interfaces

16.1 Introduction
16.2 Circuit Diagram
16.3 Display Resolutions
16.4 DVI Types and DVI Connectors
16.5 DVI versus HDMI
16.6 Setup for the Experiments
16.7 Hardware-Generated Image
16.8 Other DVI Designs
16.9 Exercises

445
445
446
448
449
450
451
452
464
464

17

VHDL Design of FPD-Link Video Interfaces

17.1 Introduction
17.2 FPD-Link Encoder
17.3 Setup for the Experiments
17.4 Hardware-Generated Image
17.5 Hardware-Generated Image with Characters
17.6 Other Designs
17.7 Exercises

467
467
468
470
472
479
490
491

APPENDICES

493

Programmable Logic Devices

495

Altera Quartus II Tutorial

503

Xilinx ISE Tutorial

515

ModelSim Tutorial

525

Altera DE2 Board Tutorial

537

BMP-to-RAW File Converter Tutorial

545

Using Macrofunctions

547

Package standard (2002 and 2008)

551

Package std_logic_1164 (1993 and 2008)

555

Package numeric_std (1997 and 2008)

563

Package std_logic_arith

577

Package std_logic_signed

583

Package textio (2002 and 2008)

585

Contents

xiii

Package numeric_std_unsigned (2008)

589

Reserved Words in VHDL 2008

593

Bibliography
Index

595
597