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Supertex inc.

AN-H60
Application Note

Designing a Four-Channel, Return-to-Zero, Ultrasound Pulser


Using Supertex HV7370 & HV748 ICs
By Ching Chu, Sr. Application Engineer

Introduction

The Supertex HV7370 is a four-channel, high speed, high


voltage, ultrasound transmitter damper, and the HV748 is a
four-channel, high speed, high voltage ultrasound transmitter
pulser. Both integrated circuits (ICs) are designed for medical
ultrasound imaging applications. They can also be used as
piezoelectric, capacitive or MEMS sensors in ultrasonic
nondestructive detection and sonar ranger applications.
These high performance CMOS ICs are in 5x5x0.9mm 32lead QFN (HV7370) and 7x7x0.9mm 48-lead QFN (HV748)
packages.
The HV7370 can be also used as a damping circuit
with Supertexs HV738 and HV758 pulsers to generate
fast returntozero waveforms. Depending upon the load
capacitance, the frequency limit of this IC is as high as
20MHz.
The HV7370 consists of four controller logic interface
circuits, four level translators, four MOSFET gate drivers and
four pairs of high current N- and P-channel MOSFETs that
serve as the four push-pull output stages.

The output stages of each channel are designed to provide


peak damping currents over 0.85A with up to 100V pulser
(VPP/VNN) voltage. The HV7370s P- and N-Channel
MOSFET gate drivers are supplied by 5~12V (typical 8.0 to
11V) on VDN & VDP pins.
The voltages VDN and VDP are referenced to ground (0V).
The output pins of the HV7370 (PD1~4 and ND1~4) are
able to pull down from or up to 100V on the capacitive
loads, which have been charged by the high voltage pulser
channels. However, the VPP and VNN of the HV748 high
voltage pulser on this demoboard can only go up to 75V. The
damping action of the HV7370 is independently controlled by
the damper input logic signals IN1 to IN4. Internally the logic
signal controls a direct-coupled low voltage to high voltage
lever translator to switch the output MOSFETs. This direct
coupling topology of the gate drivers not only saves two high
voltage capacitors per channel, but also makes the PCB
layout easier.

Typical Application Circuit


+9V

+3.3V

+3.3V

VLL

EXCLK

VDD

+75V

VPP - 9V

0 to 75V

VSUB

VPF

VPP

OTP

OSC
40MHz

Waveform
Generator
CPLD

PIN 1-4
NIN 1-4
GREF

(1of 4 Channel Output shown)


VSS

VNF

VNN

RGND

TX1
VNN +8V
+3.3V

VLL

WAVE
FREQ
SEL
ENA
TEST

D1

TXN1

HV748

MC0, 1

EN

JTAG

R1

EN

CLKIN

Option

TXP1

END
MC1
MC0
PWR
ENP
OPT

+9V

VDD

+9 to +75V

VSUB

0 to -65V

R2

-9V

VDP

C4
330pF

R3
2.5k

GND

Dummy
Load

RGND
PD4

EN

HV7370

(Damp 1-4)
IN1-4

D2
ND4

(1of 4 Channel Output shown)


GREF

VSS

VDN

RGND

+9V

Doc.# DSAN-AN-H60
A040413

Supertex inc.
www.supertex.com

AN-H60
Designing an RTZ Pulser using Supertexs
HV7370 & HV748

and each one has a 330pF capacitor in parallel with a


2.5K 1W resistor via the small copper trace shorted zero
resistors connected to the RTZ pulser outputs for each
channel. The user can easily evaluate the transducer(s) with
this HV7370 and HV748 RTZ transmitter pulser. Just open
the short(s) and, using the coaxial cable, directly connect to
the output test points to the transducer.

This application note describes how to use the HV7370


damper and the HV748 pulser to design a high speed returnto-zero (RTZ) pulser.
The output of the damper must go through two DC blocking
diodes to connect to the pulser output as the schematic
shows. Having the diode pair D1 connected in series with
the pulser output is optional because in the three-level RTZ
pulser design, the pulsers VPP/VNN supplies are the lowest
voltage rails, and therefore there is no need for the DCblocking function.

PCB Layout Techniques

It is important that the thermal slab at the bottom of the HV748


package be externally connected to its VSUB pins to make
sure that it always has the highest potential in any condition,
because this is the connection of the ICs substrate.
In order to guarantee that the HV748 VSUB will never be
below its other voltage rails, even during the power-up or
down time periods, it is strongly recommended that a set of
Schottky diodes be added to the PCB of the pulser circuit.
Each voltage supply rail must have a 2~3A Schottky diode
connected to ground as part of the normal protection scheme
used in multirail CMOS power supply design. We suggest
that you add two more diodes for power up/down protection:
one Schottky from VCC, VLL (+3.3V in this design) to VDD,
and other one from VDD to VSUB of HV748. Adding these
two additional Schottky diodes means that the system can
power-up the VCC +3.3V first, then power-up the VDD
second, all before turning on the HV748 VSUB voltage. To
have the VCC turned on first is very practically important in
system power sequence design, because it allows the CPU
and FPGA control circuit to be up working first or powered
down last, thus allowing all the other voltage rails to be under
CPU and logic control. Furthermore, once the CPU and
control logic are working, these should immediately initialize
all pulser and damper chip enable and control signals to
zero. After VCC is powered-up with the said Schottky on
board, the VDD and VSUB voltage will be only one or two
Schottky diodes forward-drop voltage away from the VCC
voltage. This will protect the IC from having substrate bias
voltage reversal or latch up.

The diode pair D2 are necessary, however. Because the


dampers MOSFETs have both sources connected to RGND,
both damping outputs must have the DC blocking diode in
series before they connect to the pulsers output summing
node. These diodes are directing current and blocking
any reverse current that would otherwise pass through a
MOSFET body diode. If one is going to design a five-level
RTZ pulser, then the output of the middle level pulser should
also have these current steering diodes. Usually these
diodes must be high voltage, high peak current and fast
reverse recovery time diodes.
The input stages of both HV7370 and HV748 are high-speed
level translators that are able to operate with logic signals
of 1.8 to 5.0V and are optimized for 2.5 to 3.3V. In most
medical imaging systems, these control signals are from
an FPGA. If the control line traces are longer than about 2
inches (50mm), it is suggested that each control line should
have a 50 resistor in series, located near the FPGA output
pin, for impedance matching to the 50 impedance of their
PCB traces.
In this design example, the control logic signal is generated
from an on-board CPLD chip. The control logic line is very
short; therefore the series resistors are not needed. The logic
level of this CPLD is 3.3V on this design example board. The
programmable CPLD uses a 40MHz crystal oscillator as the
on-board clock to generate a fast clock signal to control the
timing of this RTZ pulser. There are six-pin JTAG connections
for the USB or a parallel CPLD programming link-cable.
Users can easily modify the test waveforms according their
own test pattern requirements.

The VDD rail (+8 to +12V) provides internal bias and low side
control circuits supply voltage in both HV748 and HV7370.
In most cases, the VDD or the unregulated VDD voltage source
will also be used for the input power supply of the isolated
DC/DC converter for the two floating rails (VPP - VPF) and
(VNF - VNN), and for the non-isolated DC/DC converter (for -9V
VDP etc.). Turning the VDD supply on is second in the powerup sequence and can be under CPU or logic control.

There is also an external clock input in this design example.


By inserting a shorting jumper, which disables the on-board
oscillator, the user can instead connect an external 3.3V
clock.

It is also important to make sure that the thermal slab at the


bottom of the HV7370 package be externally connected to
HV7370s VSUB pin and that the HV7370 VSUB pin be connected
to its VDD or HV748s VSUB voltage. It is recommended to
have 0.1~0.22F capacitors decoupling for both HV748 and
HV7370 VSUB and placed very close to the pins.

There are five push buttons for selecting the test waveform,
frequency, select, enable and test functions. There are six
color LED indicators associated with these push button
control functions. There are four on-board equivalent-loads,
Doc.# DSAN-AN-H60
A040413

Supertex inc.
www.supertex.com

AN-H60
Testing the Integrated Pulser

Designers need to pay attention to the connecting traces


as high-voltage and high-speed traces. In particular, low
capacitance to the ground plane and larger trace spacing is
required.

This HV7370 and HV748 RTZ pulser design example is


tested with multiple lab DC power supplies with current
limiting functions. The following power supply voltages and
current-limits settings are used in the testing: VPP +75V
2.5mA; VNN -75V 2.5mA; VDD +9.0V 20mA; VDN +9.0V 5mA;
VDP -9.0V 5mA; VPF and VNF two isolated DC/DC floating 9.0V
5mA.; and VCC and VLL +3.3V 70 to 80mA. The +3.3V supply
current is mainly for the VCC current of the +3.3V-only CPLD.

Use high-speed PCB trace design practices that are


compatible with about 50 to 100MHz operating speeds. The
internal circuitry of the HV7370 and HV748 can operate with
high frequencies, with the primary speed limitation being
load capacitance. Because of this high speed and the high
transient currents that result when driving capacitive loads,
the supply voltage bypass capacitors should be as close to
the pins as possible. The GREF and VLL are the low and
high logic level reference pins that should connect to the
control logic circuit ground and VCC voltage, with a 0.1uF
ceramic decoupling capacitor connected in between.

The on-board dummy load 330pF//2.5k is connected to the


RTZ pulser output through the zero resistor on board with
default as shorted for using the oscilloscope high impedance
probe to look at the output waveforms as the typical load
condition. For looking into the different loading conditions,
one may change the values of dummy loads within the
current and power limitations of the device.

The VDD, VDN, VDP, VPP, VNN and VSUB pins are voltage
supplies referenced to ground. The MOSFET gate-driver
floating supplies (VPF and VNF) are referenced to VPP and
VNN high voltage power supplies respectively. All these power
supply rails can be shared for multiple HV748 and HV7370
chips if there are a large number of transmit channels in the
system. All the power supply pins of each channel can draw
fast transient currents of up to 0.8 to 1.25A, so they should
be provided with a low-impedance bypass capacitor located
close to the pins. Use an X7R or X5R 0.47 to 1.0F ceramic
capacitor for each pin or or pair of pins. All by-pass capacitor
ground pads should have low inductance feed-through via
connections that are connected directly to a solid ground
plane. Minimize the trace length to the ground plane, and
insert a ferrite bead low value resistor in the power supply
lead to the capacitor to prevent resonance in the power
supply lines.

In order to drive the users piezo transducers with a cable,


one should connect each output in series with a small 6.2
to 22 pulse current rated resistor to match the load and
cable impedance properly. This is to avoid large cable and
transducer reflections. Usually the ultrasound cable is 50
to 75 impedance rated.
The on-board test point is designed to work with high
impedance probes of the oscilloscope. Some probes may
have limited input voltage. When using a probe on the
testpoints of the pulser outputs, make sure that VPP/VNN
does not exceed the probe limits. Using the high impedance
oscilloscope probe on the onboard test points, it is important
to have as short ground leads to the circuit board ground
plane as possible.
There are multiple frequency and waveform combinations
that can be selected as bipolar pulses and PW with and
without RTZ waveforms. The frequency of the pulses are 10,
5, 2.5MHz, etc. If one needs a specific transducer frequency,
an external clock input can be used instead if the on-board
40MHz-oscillator is disabled with a jumper shorted to
ground. There are push buttons for selecting the waveform,
frequency, phase, and HV748 & HV7370 chip enable
functions. Color LEDs indicate the test selection states.There
are push buttons for selecting the waveform, frequency,
phase, and HV748 & HV7370 chip enable functions. Color
LEDs indicate the demo selection states.

Pay particular attention to minimizing trace lengths and using


sufficient trace widths to reduce inductance. Surface mount
components are highly recommended. Since the output
impedance of pulser HV748s and damper HV7370s output
stages is very low, in most cases it is desirable to add a 5
to 18 pulser current rated resistor in series with the output
to obtain better waveform integrity at the load transmission
line terminals. This will, of course, reduce the output voltage
slew rate at the terminals of a capacitive load.
Be aware of the parasitic coupling from the outputs back
to the input signal terminals of the HV7370 and HV748.
This feedback may cause oscillations or spurious waveform
shapes on the edges of signal transitions. Since the input
operates with signals down to 1.8V, even small coupling
voltages may cause problems. The use of a solid ground
plane and good power and signal layout practices will
prevent this.

Doc.# DSAN-AN-H60
A040413

The HV7370DB1 RTZ pulser circuit schematic, input and


output waveforms diagrams, detailed signal definitions, and
testing of measured waveforms are shown on the following
pages.

Supertex inc.
www.supertex.com

J1
EX = 0

J2
EXCLK

2
1

SW1

EXTRG

SYNC

CLK

MH3

SW3

C31
0.22

SW2

C31
0.22

MH2

R42
200

R41
200

R40
200

MH4

C31
0.22

SW4

R28
33k

R27
33k

39

40

43

TP12

R26
33k

R20
1k

TP30
EXTRG

R16
1k

END

TP13

TP18
SYNC

R14
1k

OUT

VCC

R15
50

R25
33k

VCC

C30
0.22

GND

EN

40MHz X1

C18
0.22

32

R6
1k

R8
1k

R7
1k

VCC

RED

D7

GRN

XC9572XL_VQ44
CPLD

GND

C31
0.22

SW5

R43
200

R29
33k

MH1

25

VCC

R5
1k

31

END

D6

ENP
C31
0.22

R44
200

PIN1
NIN1
DMP1
PIN2
NIN2
DMP2
PIN3
NIN3
DMP3
PIN4
NIN4
DMP4

J3

R30
1

VCC

JTAG

38
37
36
22
21
20
19
18
16
14
13
12

TP3

C1
0.22

C2
0.22

R31
10

+9V
VDD

VCC

R32
10

R33
10

VNF

TP10

TP9

TP6

VNN

C22
0.22

TP2
C3
0.22

VCC

R34
10

VPF

R35
10

J4

HEADER 12

NIN4

PIN4

NIN3

PIN3

NIN2

PIN2

NIN1

PIN1

MC0

EN
MC1

OTP

VLL

-9V
VDP

R37
10

VSUBP

10

R36
10

VPP

TP29

TP27
TP28

TP22
TP25

TP20
TP19

TP16

14
15

13
46

48

C12
0.22

C19 C13
0.22 0.22

TP7

VCC

VDD

R9
1k

YLW
D8

VCC

YLW

28

PWR

TP8

VNF

TP36

+9V
VDN

R38
10

C14
1
100V

VSUBP

VPF

HV 748K6

C27
1
100V

R39
10

+9V or VSUBP
VSUBD

VNN

C23 C24
0.22 0.22

TP5

VPP

C9
C6
1
C5 C8 1
0.22 0.22 100V 100V

TP35

41

D5

35
26
VCC

42

R4
1k

30

MC1

WAV

GND

29

MC0

FRE

SEL

ENP

TEST

GND

17

15

VCC
VCC

10 TMS
9
TDI
24
TDO
11
TCK
1
2
3
4
5
6

DMP1
DMP2
DMP3
DMP4
1
2
3
4
5
6
7
8
9
10
11
12

16
25
VSUBP

12

VDD
VSS
2

VDD
VSS

11

36
VSUBP
45
VSUBP

VSUBP
VNF
VNF
37
24

VNN
VNN
VNN
VNN
VNN
VNN
TP33

TXN4

TXP4

TXN3

TXP3

TXN2

TXP2

TXN1

TXP1

D19A

VDN

C28
1
100V

40
39
38
23
22
21

GREF
47

17
VPF
44
VPF
18
VPP

19
VPP

20
VPP
6

VPP

43
VPP
RGND
D20A

27

28

29

30

31

32

33

34

VDP

35

RGND
26
BAT54DW-7
6
1

YLW

VCC

D19B

VDD

D20B

C29
330p
250V

VNN

D21A

VNF

R51
324

C21
330p
250V

D13
BAV99

R52
INF

R21
INF

R49
324

R50
INF

C20
330p
250V

D11
BAV99

R47
324

R48
INF

C4
330p
250V

D9
BAV99
1

R45
324

R46
INF

R17
INF

R11
INF

R1
INF

VCC

BAT54DW-7
4
3

D4

VPP

D21B

D16

VDD

D16

VPP

D9
BAV99
1

D12
BAV99
1

D10
BAV99
1

VSUBP

R24
2.55k
1W

VSUBP

TP34

R19
2.55k
1W

TP32

R23
0

TX4

TP31

R13
2.55k
1W

TP23

R18
0

TX3

R3
2.55k
1W

TP11

R12
0

TX2

TP4

R2
0

TX1

TP14

VPF

BAT54DW-7
3
4

VPP

3
4

6
1

1
2

1
2

RED

D17

VPP

C25
0.22

C26
0.22
VDN

+75V > VSUBP > VPP

VNN = 0 to -75V

(VNF - VNN ) = +9V (isolated)

(VPP - VPF ) = +9V (isolated)

VDN = +9V (or VDD )

VDP = -9V

VDD = +9V

VCC = +3.3V

R22
0

C15
1
100V

TP37

HV 7370K6

VPP = 0 to +75V

TP15

C10 C7
0.22 0.22

VDP VSUBD TP39

D18

VNN

ND1

PD1

ND2

PD2

ND3

PD3

ND4

PD4

TP40

23

24

21

22

19

20

17

18

R10
0
TP41

TP38

B1100-13

D3

B1100-13

1
2

30

D2
BAV99
1

B1100-13

2
1

31
VSUBD
25
VSUBD
16
VSUBD
10
VSUBD

TP1

B1100-13

RGND
29

VDP

11
VDP

VDN
VDN

14
RGND
13
RGND
12
RGND
RGND
28

RGND
27

26
15

8
VDD

VDD

IN1

IN2

IN3

IN4

EN

VLL

NC

C16
0.22

VSS
VSS

Doc.# DSAN-AN-H60
A040413
7
2

D1
BAV99
1

C11
0.22

TP26

TP24

TP21

TP17

32

C17
0.22

VCC

DMP4

DMP3

DMP2

DMP1

END

AN-H60

HV7370 RTZ Pulser Schematic

Supertex inc.

www.supertex.com

AN-H60
HV7370 RTZ Pulser Waveforms
Demo Waveform A (2-Cycle)

Demo Waveform A (8-Cycle)


PIN
NIN
DMP

TX

VPP
0V

VNN

Demo Waveform B (2-Cycle)

Demo Waveform B (2-Cycle)

PIN
NIN
DMP

TX

VPP

0V

VNN

Demo Waveform C (4.5-Cycle)

Demo Waveform C (4.5-Cycle)

PIN
NIN
DMP

TX

VPP

0V

VNN

Doc.# DSAN-AN-H60
A040413

Supertex inc.
www.supertex.com

AN-H60
HV7370 RTZ Pulser Waveforms (cont.)
Demo Waveform D (8-Cycle w/o Damping)
PIN
NIN
DMP

VPP

0V

TX

VNN

Demo Waveform D (16-Cycle w/o Damping)


PIN
NIN
DMP

TX

VPP

0V

VNN

Voltage Supply Power-Up Sequence


1

VCC & VLL

+3.3V positive logic voltage. (U2 CPLD 3.3V only)

VDD, VDN /VDP, (VSUBD)

9.0V positive drive voltage. (If VSUBD = +9.0V)

VSUBP, (VSUBD)

+75V positive high voltages. (VSUBD can be +75V or +9.0V)

(VPP- VPF), (VNF- VNN)

Two isolated floating 9.0V

VPP / VNN

0 to 75V positive and negative high voltages

Doc.# DSAN-AN-H60
A040413

Supertex inc.
www.supertex.com

AN-H60
HV7370 RTZ Pulser Waveform Screens
NIN1

NIN1

PIN1

PIN1
DMP1

DMP1
TX1

TX1

NIN1

NIN1

PIN1

PIN1

DMP1

DMP1

TX1

TX1

NIN1

NIN1
PIN1
DMP1

PIN1
DMP1

HV748
Mode 4,3,2,1

Doc.# DSAN-AN-H60
A040413

HV748
Mode 4,3,2,1

TX1

TX1

Supertex inc.
www.supertex.com

AN-H60
HV7370 RTZ Pulser Waveform Screens (cont.)

TX1
HV748
Mode 3

TX1
HV748
Mode 3

NIN1

NIN1
PIN1

PIN1
HV748
P-Delay
VDD = +9V

DMP1

DMP1

TX1

HV748
N-Delay
VDD = +9V

TX1

NIN1

NIN1

PIN1
DMP1

PIN1
HV7370
N-Delay
VDD = +9V

DMP1

HV7370
P-Delay
VDD = +9V

TX1
TX1

Doc.# DSAN-AN-H60
A040413

Supertex inc.
www.supertex.com

AN-H60
HV7370 RTZ Pulser Waveform Screens (cont.)
NIN1
PIN1
DMP1

TX1

TX1

TX1

TX1

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

Supertex inc.

2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.

Doc.# DSAN-AN-H60
A040413

1235 Bordeaux Drive, Sunnyvale, CA 94089


Tel: 408-222-8888
www.supertex.com