FinFET Technology

Ramiz Mahaboob [160942016]

Department of Electronics & Communication, Manipal Institute of Technology

Abstract
To achieve high current drive and
short channel effects control, the siliconon-insulator (SOI) MOS transistors has
changed from single gate, planar devices to
double gate three dimensional structure as
FinFETs. FinFET technology is now the
best alternative to planar bulk CMOS
technology as it has shown better results in
device variability, suppress leakage current,
better scalability and importantly short
channel characteristics in comparison with
CMOS bulk technology. This paper
provides some background on why
FinFETs are needed, SOI vs bulk FinFETs
and double patterning fabrication used in
FinFETs.
Introduction
The scaling of the MOSFET transistor is
necessary so as to have high packing
density, improved frequency response and
improved current drive by increasing
transconductance. But the main problem to
progress hen scaling is the leakage
phenomenon occurred due to variation in
threshold voltage. Leakage increases due to
lowering of oxide thickness, channel
lengths and higher substrate dopings. So in
order to reduce the leakage, the threshold
voltage is to be maintained high.
A. I-V characteristic
Figure 1 shows ID versus VDS for
FinFET transistors and bulk CMOS when

VGS changes from zero to 0.9 volts. From

the figure two ION and output resistance
features can be derived. The ION in FinFET
is higher in comparison to bulk CMOS. It
has lower channel length modulation and
high output resistance. This is because the
channel is surrounded on the two sides in
FinFETs. So this gives a better gate control
compared to single gate transistors.
B. Drain Induced Barrier Lowering
For long channel transistors, the
channel is formed far from the drain
contact. But as the channel dimensions of
transistors get shrunk, the gate loses control
over flow of current and potential
distribution in the channel. As the drain
voltage increases, the potential distribution
across the drain changes and the barrier
decreases in the channel, which is known as
Drain Induce Barrier Lowering (DIBL).
Thus the potential barrier reduction leads to
electron flow in the channel between source
and drain, even if VGS is less than the
threshold voltage.
C. Subthreshold Swing
The minimum subthreshold swing of a
conventional device is 60 mV/dec at room
temperature (300 K) as Cox -> . It shows
that for thinner oxides, the subthreshold
swing tends to be ideal. But this can cause
a higher gate leakage current which results
in tunneling. It reduces device reliability
and increases total power consumption.

Figure 1: I-V characteristic (a) FinFET (b) Bulk MOSFET

Figure 2 shows the drain induced barrier

lowering and SS vs LEFF for FinFETs and
Bulk MOSFETs.

current. Figure 3 also shows that IOFF can be

varied by varying the fin width of the
FinFET NMOS. So it depends on the fin
width that the IOFF is better for FinFET or
for the bulk NMOS. The ION increase is due
to the reduction of parasitic S/D resistances.
Thus the less channel control of the gate
causes an increase in IOFF.

Figure 2: DIBL and SS vs LEFF for

FinFETs and Bulk MOSFETs.
Figure 3: FinFET and bulk I-V
characteristics
D. Ion/Ioff ratio
FinFET Geometry
Figure 3 shows the ION and IOFF of
32nm Bulk NMOS and FinFET NMOS for
different fin widths (Wfin = 10nm). The on
current of FinFETs are more than that of
32nm Bulk NMOS, which gives faster
switching times. Bulk CMOS has many
leakage like gate-induced drain leakage
(GIDL), gate leakage due to tunneling,
subthreshold leakage and reverse-biased
junction which leads to decreased on

A. Fin Width (Tfin): It denotes the thickness

of the fin. It determines DIBL value.
B. Fin Height (Hfin): It denotes the height
of the fin. It is limited by etch
technology.
C. Fin Pitch: The fin pitch is the distance
between the fins plus the width of the
fin. Figure 4 shows the above
mentioned geometries.

3. Parasitic
Capacitance:
Junction
isolated Bulk-FF has more parasitic
capacitance than SOI but the impact of
the junction capacitance difference can
be kept below 5-6%
4.

Figure 4: Double-gate FinFET with

multiple fins and geometry labelled.

Variability Analysis: Fin width & Fin

height variability appear to be
significantly larger for Bulk-FinFET.

5. Cost: At high-volume the cost

difference of SOI-FinFET with BulkFinFET is less than 4%.

SOI vs Bulk FinFETs

Figure 5 and Figure 6 shows Doublegate Bulk and SOI FinFETs respectively.
Following are the comparison between the
two flavors of FinFETs:
1. Performance: Similar DC & AC
performance for SOI-FF & Bulk-FF are
observed
2. Heat Transfer rate: Bulk-FF has very
high heat transfer rate than SOI-FF.
Figure 5 shows the Heat Transfer Rate
comparison of Bulk and SOI FinFETs.

Figure 5: Heat Transfer Rate comparison

of Bulk and SOI FinFETs.

Figure 6:
structure

Double-gate

SOI

FinFET

Figure 7: Basic Double-gate Bulk-FinFET

structure.

Self-Aligned Double Patterning

Currently Argon Fluoride (ArF) Lasers
with 193nm wavelength are used for
Photolithography. Using variety of
enhancement techniques like Optical
Proximity
Correction
(OPC)
and
Immersion Lithography, we have been able
to extend down to 65nm node. But lower
technology nodes are achieved currently
using the same source by the use of Double
Patterning. Double Patterning is actually
achieved by overlaying two patterns of the
same pitch. So by double patterning we
achieve a pattern which is half the pitch.
Figure 7 shows a standard Self
Aligned Double patterning process flow. A
dummy pattern (mandrel) is used as a
mould for obtaining the first step. Then
silicon nitride (SiN) dielectric is grown
around the dummy lines. Then film is
etched back except the sidewalls forming
spacers around the resist. Now the dummy
pattern is removed leaving the sidewall.
The final etching removes the remaining
double density sidewall into the silicon. It
eliminates trouble with pattern overlay
tolerance. It is optimized for processes with
uniform patterns. Requires only one
lithography step which reduces the cost.

Figure 7: Self-Aligned Double Patterning

Process Flow
Conclusion
FinFET technology has made a great
impact to the digital world and entered the
market. For high performance computing,
devices have adapted it and will remain the
same for the near future. Even though the
fabrication is difficult to carry out it has
proven its worth in the digital market.
Relevant changes in has been brought up in
the design by FinFET and are developing
fast with the updates in the tool.
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