520.

424 FGPA Lab 2016

Tones

Before you start, carefully read this project assignment in its entirety. It contains a good deal of
information. At the end of this project assignment, there are questions related to the project. You
should look at them before starting the project, and try to answer them as you go.

Project overview
In this two-part project, you will generate waveforms with controllable frequency using a look-up
table containing each waveforms samples, an accumulator to index the look-up table and a DAC
to convert the samples to analog voltages.
In the first part, you will create a function generator to output a sine or triangle wave, using the
provided Matlab GUI to input the shape (triangle or sine) and the frequency in Hertz.
In the second part, you will output sine waves only, but at the maximum sampling rate that the
DAC supports, and with controllable volume and duration. You will test your code with a Matlab
script that plays Jingle Bells.

Digital to Analog Converter

A PIC microcontroller has been programmed to emulate a Digital to Analog Converter (DAC).
To make the sampling rate as high as possible, two important changes relative to previous labs
have been made: the microcontroller clock has been brought out to a pin and the DAC data bits
are supplied in parallel. The result is that the DAC update program loop is just 13 instructions,
or 52 clock cycles. At 10 MHz (the maximum clock frequency for this processor at 3.3V) that
corresponds to approximately 192 ksps (kilo-samples-per-second).
However, because the microcontroller is 8 bits, it cannot sample all 9 bits of the input data
simultaneously. In fact it samples the upper 3 bits first, and a few instructions later, it samples the
lower 6 bits. The problem is that if the FPGA changes the data between these two points, the PIC
will program garbage to the DAC. To get around this problem, the PIC outputs a dac busy signal
during data sampling do not change the dac data pins when dac busy is high! In fact, it is
recommended that you use the dac busy signal (suitably synchronized to avoid metastablity) to
trigger your state machine.
One other change that needs mentioning is that the DAC output is now buffered by an internal
Op-Amp. This was needed because the DAC output was otherwise affected by nearby digital
signals (i.e. cross-talk) which resulted in 200 mV glitches in the output. Buffering the output
eliminates the glitches, but renders the input range from approximately 416 to 511 unusable. It is
therefore recommended that you keep the DAC sample values between 128 and 384 (approximately
0.825 V to 2.475 V).
The suggested wiring is shown on the next page.

520.424 FGPA Lab 2016

Tones
n

2
n

USB

d
d
d
td GND td
d P75 d
td P79 td
td P81 td
td P83 td
td P85 td
td P88 td
d P93 d
d P95 d
d P98 d
d P100 d
d P102 d
d P105 d
d

d d d d d d d d d d d d d
d d d d d d d d d d d d d

dP74
dP78
dP80
dP82
dP84
dP87
dP92
dP94
dP97
dP99
dP101
dP104
d3.3V

3.3V
P143
P141
P139
P137
P133
P131
P126
P123
P118
P116
P114
P111

d d d d
d d d d
d d d d
d d d
14 tdGND
d
d d d
t
13 OUT
d d d
12 tdBUSY
d d d6
t
d
11 DATA
d d d0
10 tdDATA
t
d
d d d1
9 DATA
d d d2
8 tdDATA
d d d d
d d d d
d d d d
d d d d
d d d d
d d d d
d d d d

P144
P142
P140
P138
P134
P132
P127
P124
P119
P117
P115
P112
GND

3.3V td
P34 d
P32 d
P29 d
P26 d
P23 d
P22 d
P16 d
P14 d
P9 d
P7 d
P5 d
P1 d

d d d d d
d d d d d
d d d d d
dP35 td d VDD
d d td1
tdP33 tdCLOCK
d d d td2
tdP30 tdDATA
d d d8 td3
tdP27 tdDATA
d d d7 td4
tdP24 tdDATA
d d d5 td5
tdP21 tdDATA
d d d4 td6
tdP17 tdDATA
d d d3 td7
dP15 d d d d d
dP10 d d d d d
dP8
d d d d d
dP6
d d d d d
dP2
d d d d d
dGND d d d d d
d d d d d

Look-up table
One of the core components of this lab assignment is the look-up table. These tables are formed
from block RAMs whose contents are initialized in VHDL. To simplify the creation of these lookup tables, a Matlab function mk rom.m has been supplied. An example of using this function is
shown in mk lab10.m, which creates all the look-up tables needed for this lab assignment. As a
side benefit of using the mk rom.m function, the input address and output data are already padded
as needed.

Accumulator
The other core component of this lab assignment is the accumulator. An accumulator is similar
to a counter, except that the accumulator increments by an arbitrary value, whereas a counter
increments by 1 (or some other constant). The accumulator design for parts A and B are different,
so they will be discussed in more detail in those sections.

520.424 FGPA Lab 2016

Tones

Part A
In this part, we will create a function generator that produces either sine or triangle waves. The
FPGA will be controlled from a Matlab GUI in which we will specify the desired frequency in
Hertz and the desired waveform shape (sine or triangle).
The waveform shape can be changed simply by selecting the output of one of two look-up
tables, one containing a sine wave and the other a triangle wave.
The frequency can be changed by changing the accumulators increment. However, we want
the accumulator increment value to be the frequency in Hertz. For instance, when the increment
is 1, the accumulator must over flow once per second, or once every 48,000,000 system clock
cycles. This in turn means that the accumulators modulus (the over flow value) must evenly
divide 48,000,000.
The other constraint is that the modulus cannot exceed the DACs maximum sampling rate
(192,000), because we will be incrementing/updating the accumulator once per sample. The final
constraint is that the modulus should be of the form n 2k , where n is as large as possible but no
larger than the size of the look-up table (2048). For this part, the best modulus is 128,000, with
n = 2000 and k = 6.
However, this means that the DACs sampling rate must be 375 (48e6/128e3) clock cycles
that is, the dac clock signal must toggle 104 times every 375 clock cycles. To achieve this, we
need another accumulator: a modulo 375 accumulator that increments by 104 every clock cycle.
The dac clock signal should be toggled every time this accumulator over flows.
When implementing your modulo m accumulators, dont forget that the accumulator is not
reset to zero on over flow. Instead, the modulus is subtracted. Your code should look something
like:
process(clk)
begin
if rising_edge(clk) then
if (accumulator>=modulus-increment) then
accumulator<=accumulator+increment-modulus;
else
accumulator<=accumulator+increment;
end if;
end if;
end process;
Note that the magnitude check compares the accumulator to modulus-increment, rather
than comparing accumulator+increment to modulus. This is because there is a risk that adding
the increment to the accumulator might cause a roll-over resulting in a smaller number. For instance, if accumulator, modulus and increment are 10 bit unsigned numbers, and the accumulator
is 999, the modulus is 1000 and the increment is 25, then the sum of the accumulator and increment
is 0, so the over flow correction wont occur when it should. By computing the modulus minus the
increment (975), the comparison succeeds and the accumulator is set to the correct value (25).

520.424 FGPA Lab 2016

Tones

However, for this project, we want to investigate aliasing, which occurs when the increment is
larger than the modulus, as well as negative increments. In this instance, we cannot solve the rollover problem by altering the comparison, and we need to add an under flow check to the VHDL.
The code will look something like (note that you will need to add code to check the dac busy
signal):
process(clk)
begin
if rising_edge(clk) then
if (accumulator+increment>=modulus) then
accumulator<=accumulator+increment-modulus;
elseif (accumulator+increment<0)
accumulator<=accumulator+increment+modulus;
else
accumulator<=accumulator+increment;
end if;
end if;
end process;
To prevent roll-over problems, we need to ensure that we have enough bits to compute accumulator+increment. The accumulator should always be between 0 and +127,999. However, the
increment value from the Matlab GUI will be an 18-bit signed, so that its value ranges from 131,072 to +131,071. accumulator+increment therefore ranges from -131,072 to +259,070,
which requires a 19-bit signed. Since the increment will need to be 19 bits, the value from the
Matlab GUI will need to be signed extended as follows:
increment<=signed(data_out(17)&data_out(17 downto 0));
The Matlab GUI module lab10 gui.vhd provides a 24 bit data out. The waveform shape is
selected using data out(23): when 0, the output should be a sine wave, and when 1, the output
should be a triangle wave. (The module also provides a trig out signal which you can ignore.)

Part B
In part B, we will create a tone generator to play music. There are several differences between the
two parts:
1. The output only needs to produce sine waves.
2. The output amplitude and duration must be controllable.
3. The DAC should be operated at the maximum practical sampling rate.

520.424 FGPA Lab 2016

Tones

4. The frequency will be specified by Matlab as a MIDI code, and the FPGA must translate the
code to an increment value via a look-up table.
The Matlab interface will provide three bytes. The first byte (data out(7 downto 0)) will
contain the MIDI code (which is actually only 7 bits, so data out(7) should be ignored). The second byte (data out(15 downto 8)) will contain the volume. Multiplying the waveform look-up
table data by 255 (maximum volume) should yield the maximum DAC amplitude, so the waveform
look-up table data must be scaled appropriately.
The third byte (data out(23 downto 16)) will contain the tone duration in hundredths of a
second (i.e. 255 should produce a tone for 2.55 seconds). As a special case, a tone duration of
zero should produce a constant tone (until the next tone command is received). To help with this
aspect, an extra signal trig out has been added to the GUI interface. This signal pulses high for
one clock cycle whenever data out is updated.
To achieve the maximum sampling rate, you will need to modify the accumulator which generates data clock to generate a frequency as close to 10 MHz as possible, without actually exceeding 10 MHz. In principle, you could select a modulo 48 accumulator with an increment of 20
(recall that you must toggle twice for one period of data clock), but this will result in a variable
number of 48 MHz clocks per DAC sample. This jitter may affect the sound quality, so its better
to go for a slightly slower data clock that results in a constant number of 48 MHz clocks per
DAC sample.
Musical notes (see appendix) are spaced evenly on a log scale, so you will not be able to
convert from MIDI code to an accumulator increment with simple arithmetic in the FPGA. The
only practical way to perform the conversion is to use a look-up table. Since we only need 128
entries in this look-up table, we might as well use the widest possible block RAM organization:
512 words of 36 bits. Thus the accumulator should also be 36 bits. As before, you can use the
mk rom.m function to generate the look-up tables for this part of the project, and you can refer to
the example in mk lab10.m.

Suggestions
To hear the sound output from Part B, you should be able to connect computer speakers or even
headphones to the DAC output. (Note that to prevent possible damage to the headphones, you
should use a DC blocking capacitor between the DAC output and the headphones, and also start
with a low volume setting.)
Part B requires the ability to stop the output sound. To do this, you need only set the increment
to zero: speakers and headphones do not respond to DC and low frequencies. (This will result in
some harshness at the beginning and end of a note, so for a real application, you would want to
filter the audio signal in the analog domain (after the DAC) as well as the digital domain (in the
FPGA).)

520.424 FGPA Lab 2016

Tones

Grading
The overall project will count 100 points:
50 pts - Working demonstration of the function generator.
50 pts - Working demonstration of the music synthesizer playing Jingle Bells.
15 bonus pts - Demonstration of the music synthesizer playing another unique tune of comparable length to Jingle Bells. (The tune must be unique in that no other student has ever played
it).

Questions
The following are questions that you may be asked during your demonstration:
1. What kind of waveforms are not amenable to the look-up table and accumulator method of
frequency adjustment?
2. How would you modify the project to output a square wave with programmable duty-cycle?
(i.e. to have independent control of the frequency and duty-cycle)
3. Suppose we wanted to play chords (i.e. multiple notes simultaneously). Would we need
multiple look-up tables? Would we need multiple DACs?

520.424 FGPA Lab 2016

Tones

Appendix
The Musical Instrument Digital Interface (MIDI) standard assigns half-note number 69 to the A
above middle C. Typically, this corresponds to 440 Hz. Furthermore, there are twelve half-notes
per octave (doubling in frequency). Therefore, you can generate a vector of the MIDI frequencies
in Matlab with the following command:
f=440*(2.((-69:58)./12));
The resulting frequencies are given by the following tables (middle C and A above middle C
highlighted):
G]/A[
A
A]/B[
B
C
C]/D[
D
D]/E[
E
F
F]/G[
G

8.1758 Hz
8.6620 Hz
9.1770 Hz
9.7227 Hz
10.301 Hz
10.913 Hz
11.562 Hz
12.250 Hz

G]/A[
A
A]/B[
B
C
C]/D[
D
D]/E[
E
F
F]/G[
G

12.978 Hz
13.750 Hz
14.568 Hz
15.434 Hz
16.352 Hz
17.324 Hz
18.354 Hz
19.445 Hz
20.602 Hz
21.827 Hz
23.125 Hz
24.500 Hz

415.30 Hz
440.00 Hz
466.16 Hz
493.88 Hz
523.25 Hz
554.37 Hz
587.33 Hz
622.25 Hz
659.26 Hz
698.46 Hz
739.99 Hz
783.99 Hz

25.957 Hz
27.500 Hz
29.135 Hz
30.868 Hz
32.703 Hz
34.648 Hz
36.708 Hz
38.891 Hz
41.203 Hz
43.654 Hz
46.249 Hz
48.999 Hz

830.61 Hz
880.00 Hz
932.33 Hz
987.77 Hz
1.0465 kHz
1.1087 kHz
1.1747 kHz
1.2445 kHz
1.3185 kHz
1.3969 kHz
1.4800 kHz
1.5680 kHz

51.913 Hz
55.000 Hz
58.270 Hz
61.735 Hz
65.406 Hz
69.296 Hz
73.416 Hz
77.782 Hz
82.407 Hz
87.307 Hz
92.499 Hz
97.999 Hz

1.6612 kHz
1.7600 kHz
1.8647 kHz
1.9755 kHz
2.0930 kHz
2.2175 kHz
2.3493 kHz
2.4890 kHz
2.6370 kHz
2.7938 kHz
2.9600 kHz
3.1360 kHz

103.83 Hz 207.65 Hz
110.00 Hz 220.00 Hz
116.54 Hz 233.08 Hz
123.47 Hz 246.94 Hz
130.81 Hz 261.63 Hz
138.59 Hz 277.18 Hz
146.83 Hz 293.66 Hz
155.56 Hz 311.13 Hz
164.81 Hz 329.63 Hz
174.61 Hz 349.23 Hz
185.00 Hz 369.99 Hz
196.00 Hz 392.00 Hz

3.3224 kHz
3.5200 kHz
3.7293 kHz
3.9511 kHz
4.1860 kHz
4.4349 kHz
4.6986 kHz
4.9780 kHz
5.2740 kHz
5.5877 kHz
5.9199 kHz
6.2719 kHz

6.6449 kHz
7.0400 kHz
7.4586 kHz
7.9021 kHz
8.3720 kHz
8.8698 kHz
9.3973 kHz
9.9561 kHz
10.548 kHz
11.175 kHz
11.840 kHz
12.544 kHz