1.

8051 MICROCONTROLLER CORE

1.1. General Features

Versions
- Intel 8051 classical
- 8051 extended
extended: Philips 80C51MX, Dallas 390 etc,
- Intel / Atmel WM 251

SoC
SoC System on a Chip

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Block Diagram
- CPU
- Quartz Oscillator
- 4 kB ROM
- 128 B RAM
- 4 x 1 B I/O port
port
- 1 serial port
- 2 x 16 b timers
- Interrupt Controller

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1.2. Memory Organization

The program memory and the data memory are physically separated (Harvard
Harvard)
a) Program memory:
- ROM or EPROM type
- Memory map: 64 kB
- On the chip: 4 kB, 8 kB or 16kB.
- Some versions: all memory is external
- Write enable: PSEN (Program Store Enable)
- After RESET, (PC) 0000H
- Dedicated memory locations:
Program launch:
Interrupt vector type 0:
timer 0:
Interrupt vector type 1:
timer 1:

0000H 0002H
0003H 000AH
000BH
0013H 001AH
001BH

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b) Data memory:
- External memory has 64 kB
- Data Bus and Address Bus by Port 0 and (if necessary) by Port 2
- Enable with RD,
RD, WR
- External Data Memory addresses can be either 1 or 2 bytes wide

- Internal Memory is accessed by 88-bit address

- There are 3 blocks of 128 B each:
Lower 128
128,
Upper 128
128,
SFR Space
Space.

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- Internal Data Memory addresses are always one byte wide, which implies an address space of only
256 bytes.
However, the addressing modes for internal RAM can in fact accommodate
accommodate 384 bytes,
bytes, using a simple
trick: direct addresses higher than 7FH access one memory space, and indirect addresses higher than
7FH access a different memory space. The Figure shows the Upper 128
128 and SFR Space
Space occupying
the same block of addresses 80H through FFH,
FFH, although they are physically separate entities.
- Upper 128
128 is not implemented in classical 8051
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- Lower 128
128 Memory:
Memory:
4 register banks of 8 registers
each: R0 R7
16 B bit addressable memory
Available storage area

All of the bytes in the Lower 128

128 can
be accessed by either direct or indirect
addressing.
addressing.

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1.3. Registers
- 32 physical registers
- 8 logic registers workwork-set registers: R0,
R0, R1,
R1,, R7
- SFR special function registers:
Byte 1

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

F7

EF

E8
E0

Byte 8
FF

F8
F0

Byte 7

E7

ACC

D8

DF

PSW
C8 T2CON

D7

D0

RCAP2L RCAP2H

TL2

TH2

C7

C0
B8
B0
A8
A0
98
90
88
80

CF

IP
P3
IE
P2
SCON SBUF
P1
TCON TMOD
P0
SP

BF
B7
AF
A7
9F
97

TL0
DPL

TL1
DPH

TH0

TH1

8F

PCON 87

Bit addressable memory locations

Available only for 8052
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ACC
B
PSW
SP
DPTR

Accumulator
8 bit register (accumulator extension)
Program Status Word
Word
Stack Pointer
Data Pointer
DPL
DPH

P0
P1
P2
P3
IP
IE
TMOD
TCON
T2CON
TH0
TL0
TH1
TL1
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
PCON

Port 0
Port 1
Port 2
Port 3
Control interrupt priorities
Control interrupt enable
Control mode timer / counter
Control timer / counter
Control 2 timer / counter
timer / counter 0 high byte
\timer / counter 0 low byte
timer / counter 1 high byte
timer / counter 1 low byte
timer / counter 2 high byte
timer / counter 2 low byte
timer / counter 2 Capture Reg. high byte
timer / counter 2 Capture Reg. high byte
Serial Control
Serial Data Buffer
Power Control
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CY

PSW

Program Status Word

Word:

CY
AC
F0
RS1
RS0
OV
P

Carry Flag
Auxiliary Carry Flag
Flag 0 available to the user for general purpose
Register Bank selector bit 1
Register Bank selector bit 0
Overflow Flag
User definable flag
Parity flag (in the accumulator)

AC

F0

RS1

RS0

OV

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1.4. Addressing Techniques

Direct Addressing:
Addressing:
- The complete address is 8 b wide in the current instruction format
format
- Available for internal data memory: Lower 128 and SFR Space
Space

Indirect Addressing:
Addressing:
- The addresses are 8 b or 16 b wide
- Available for 256 B internal data memory: Lower 128
128 and Upper 128
128
or 64 kB de external data memory
- For 8 b addresses R0,
R0, R1 or SP are used
- For 16 b addresses only DPTR is used for the external data memory

Implied Register Addressing:

Addressing:
- Data in one of the 8 registers in the workwork-set registers: R0,
R0,, R7
- The target register selection: by 3 bits in the instruction code
code
- Some instructions point out specific registers (accumulator, data
data pointer etc.)

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Immediate Addressing:
Addressing:
- A constant which is in the current instruction format, after the
the code
- The constant is 8 b or 16 b wide

Indexed Addressing:
Addressing:
- Only for the program memory!
memory!
- For table translations DPTR or PC have the base address and ACC has the table entry
- For jumps ACC has the displacement

Relative Addressing:
Addressing:
- Only for the program memory
- The range of the jump is -128B to + 127B in the program memory relative
to the first byte following the instruction.

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1.5. The instruction Set

1) Arithmetic Operations:
Operations:

Syntax
ADD A, s
ADDC A, s
SUBB A, s
INC A
INC s
INC DPTR
DEC A
DEC s
MUL AB
DIV AB
DA A

Semantics
(ACC) (ACC) + (s)
(ACC) (ACC) + (s) + (CY)
(ACC) (ACC) - (s) - (CY)
(ACC) (ACC) + 1
(s) (s) + 1
(DPTR) (DPTR) + 1
(ACC) (ACC) - 1
(s) (s) - 1
(B) (A) (B) * (A)
(A) (A) div (B), (B) (A) mod (B)
Decimal adjust

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Addressing Modes
Dir. Ind. Reg. Im.

12

2) Logical Operations:
Operations:

Syntax
ANL A, s
ANL s, A
ANL s, #data
ORL A, s
ORL s, A
ORL s, #data
XRL A, s
XRL s, A
XRL s, #data
CRL A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A

Semantics
(ACC) (ACC) (s)
(s) (s) (ACC)
(s) (s) ((PC)+1)
(ACC) (ACC) (s)
(s) (s) (ACC)
(s) (s) ((PC)+1)
(ACC) (ACC) (s)
(s) (s) (ACC)
(s) (s) ((PC)+1)
(ACC) 00H
(ACC) not (ACC)
Rotate ACC left 1 bit
Rotate ACC with CY left 1 bit
Rotate ACC right 1 bit
Rotate ACC with CY right 1 bit
(ACC)h (ACC)l
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Addressing Modes
Dir. Ind. Reg. Im.

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3) Data Transfer:
Transfer:

Addressing Modes
Syntax
Semantics
Dir. Ind. Reg. Im.
MOV A, s

(ACC) (s)
MOV s, A

(s) (ACC)
MOV d, s

(d) (s)
MOV DPTR, #data16 (DPTR) ((PC)+2) ((PC)+1)

PUSH s

(SP) (SP) + 1, ((SP)) (s)

POP d

(d) ((SP)), (SP) (SP) - 1

XCH A, s

(ACC) (s)
XCHD A, @Ri

(ACC)l (Ri)l

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N.B.
- The external memory is accessed with MOVX
- The stack resides in onon-chip RAM, and grows upwards!
upwards!
PUSH s ; (SP) (SP) + 1
; ((SP)) (s)
POP d

; (d) ((SP))
; (SP) (SP) 1

- The stack access is, in fact, an indirect addressing through (SP

);
(SP);
So, the stack will never be in SFR space
space. Instead, the stack could be located
in Upper 128
128 or in Lower 128
128.

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4) Data Transfer with External Memory:

Syntax
MOVX A, @Ri
MOVX @Ri, A
MOVX A, @DPTR
MOVX @DPTR, A

Semantics
(ACC) ((R0)) or (ACC) ((R1))
((R0)) (ACC) or ((R1)) (ACC)
(ACC) ((DPTR))
((DPTR)) (ACC)

Addressing Modes
Dir. Ind. Reg. Im.

N.B.
The accumulator is always part of the transfer.
Only indirect addressing can be used. The choice is whether to use a oneone-byte address, @Ri
@Ri where
Ri can be either R0 or R1 of the selected register bank, or a twotwo-byte address, @DPTR
@DPTR..
For the last case, the Address Bus uses Port 0 and Port 2.
5) Lookup Tables Reading in the Program Memory:

Syntax
MOVC A, @A+DPTR
MOVC A, @A+PC

Semantics
(ACC) ((ACC)+(DPTR))
(ACC) ((ACC)+(PC))
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Addressing Modes
Dir. Indexat Reg. Im.

16

6) Boolean Variable Manipulation:

Manipulation:

Syntax
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
CLR C
CLR bit
SETB C
SETB bit
CPL C
CPL bit
JC disp
JNC disp
JB bit, disp
JNB bit, disp
JBC bit, disp

Semantics
(CY) (CY) bit
(CY) (CY) not bit
(CY) (CY) bit
(CY) (CY) not bit
(CY) bit
bit (CY)
(CY) 0
bit 0
(CY) 1
bit 1
(CY) not (CY)
bit not bit
(PC) (PC)+disp if (CY) = 1
(PC) (PC)+disp if (CY) = 0
(PC) (PC)+disp if bit = 1
(PC) (PC)+disp if bit = 0
(PC) (PC)+disp if bit = 1; bit 0
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Addressing Modes
Dir. Ind. Reg. Im.

17

N.B.
The accessed bits ate in Lower 128
128 or in SFR.
CY is in PSW.
The jumps are in the range of 128B to +127B relative to current instruction,
in the program memory.

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7) Program Branching:
Branching:

Syntax
JMP adr
JMP @a+DPTR
CALL adr
RET
RETI
NOP
JZ disp
JNZ disp
DJNZ s, disp
CJNE A, s, disp
CJNE s,#data,disp

Semantics
(PC) adr
(PC) ((A)+(DPTR))
(SP) (SP) + 1, ((SP)) (PC)
(PC) adr
(PC) ((SP)), (SP) (SP) - 1
(PC) ((SP)), (SP) (SP) - 1
(PC) (PC)+disp if (ACC) = 0
(PC) (PC)+disp if (ACC) 0
(s) (s) 1; if (s) 0
(PC) (PC)+disp
(PC) (PC)+disp if (ACC) (s)
(PC) (PC)+disp if
(s) ((PC)+1)

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Addressing Modes
Dir. Ind. Reg. Im.

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N.B.
JMP is a general mnemonic standing for:
SJMP jump with relative addressing 2B format.
LJMP jump with direct addressing 3B format.
AJMP jump with direct addressing using a 11b constant 2B format.
The same for CALL.
CALL.
All conditional jumps use relative addressing (the destination address is specified by
the relative offset method and so are limited to a jump distance of 128B to + 127B from
the instruction following the conditional jump instruction).
DJNZ is a loop instruction with s as the cycle counter.

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1.6. Instruction Timing

A machine cycle consists of a sequence of 6 states: S1,
S1,, S6.
S6.
Each state time lasts for two oscillator periods.
Thus a machine cycle takes 12 oscillator periods (for example, 1 s if the
oscillator frequency is 12 MHz).
Normally, the instructions last 1 machine cycle.
cycle.
Two program fetches are generated during each machine cycle (in S1 and in
S4),
S4), even if the instruction being executed doesn
doesnt require it. If the instruction
being executed doesn
doesnt need more code bytes, the CPU simply ignores the extra
fetch, and the Program Counter is not incremented.
The MOVX instructions take two machine cycles to execute. No program fetch
fetch is
generated during the second cycle of a MOVX instruction. This is the only time
program fetches are skipped.

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