MOSFET Cross-Section

Bulk/Substrate

Source

Gate

Drain

Polysilicon

p+

n+

Thin Oxide
(10-100nm
100-1000)

n+

p- substrate

Heavily
Doped p

Lightly
Doped p

Intrinsic
Doping

Lightly
Doped n

Heavily Metal
Doped n
Fig1.8-1

A MOSFET Transistor
Source

Drain

Gate
Drain

Source

Substrate

Gate

Formation of the Channel for an Enhancement MOS

Transistor
Subthreshold (VG<VT)
VB = 0

VS = 0

V G < VT

VD = 0

Polysilicon

p+

n+

n+

p- substrate
Threshold (VG=VT)
VB = 0

VS = 0

VG =VT

VD = 0

Polysilicon

p+

n+

n+

p- substrate

Inverted Region

Strong Threshold (VG>VT)

VB = 0
VS = 0

VG >VT

VD = 0

Polysilicon

p+
p- substrate

n+

n+
Inverted Region
Fig1.8-2

Fabrication Processes for VLSI Devices

Chip Fabrication
Processes
Silicon Wafer
Manufacture

Epitaxial
Growth

Photolithography

oxidation

Etching

Diffusion (Ion
Implantation)

Metallization

Packaging
6

What is a Silicon Chip?

A pattern of interconnected switches and gates on the surface of a crystal
of semiconductor (typically Si)
These switches and gates are made of

areas of n-type silicon

areas of p-type silicon
areas of insulator
lines of conductor (interconnects) joining areas together
Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten

The geometryof these areas is known as the layout of the chip

Connections from the chip to the outside world are made around the edge
of the chip to facilitate connections to other devices

CMOS Fabrication
CMOS transistors are fabricated on silicon
wafer
Wafers diameters (200-300 mm)
Lithography process similar to printing press
On each step, different materials are
deposited, or patterned or etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process

Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires to make an n-well for body of pMOS transistors
A
GND

VDD

SiO 2
n+ diffusion

n+

n+

p+

p+
n well

p substrate
nMOS transistor

p+ diffusion
polysilicon
metal1

pMOS transistor

Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
Use heavily doped well and substrate contacts/taps (or
ties)
A
GND

VDD

p+

n+

n+

p+

p+
n well

p substrate
substrate tap

well tap

n+

Inverter Mask Set

Top view
Transistors and wires are defined by masks
Cross-section taken along dashed line

GND

VDD
nMOS transistor
substrate tap

pMOS transistor
well tap

Detailed Mask Views

Six masks

In

n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
In reality >40 masks
may be needed

n well

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

Fabrication Steps
Start with blank wafer (typically p-type where NMOS is created)
Build inverter from the bottom up
First step will be to form the n-well (where PMOS would reside)

Cover wafer with protective layer of SiO2 (oxide)

Remove oxide layer where n-well should be built
Implant or diffuse n dopants into exposed wafer to form n-well
Strip off SiO2

p substrate

Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation
furnace

SiO 2

p substrate

Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Property changes where exposed to light
Two types of photoresists (positive or negative)
Positive resists can be removed if exposed to UV light
Negative resists cannot be removed if exposed to UV light

Photoresist

SiO 2

p substrate

Lithography
Expose photoresist to Ultra-violate (UV)
light through the n-well mask
Strip off exposed photoresist with
chemicals

Photoresist
SiO 2

p substrate

Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty
stuff!!!

Only attacks oxide where resist has been

exposed
N-well pattern is transferred from the mask
to silicon-di-oxide surface; creates an
opening to the silicon surface
Photoresist
SiO 2

p substrate

Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next

step

SiO 2

p substrate

n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic-rich gas
Heat until As atoms diffuse into exposed Si

Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si

SiO2 shields (or masks) areas which remain p-type

SiO 2
n well

Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps

n well
p substrate

Polysilicon
(self-aligned gate technology)

Deposit very thin layer of gate oxide

< 20 (6-7 atomic layers)

Chemical Vapor Deposition (CVD) of silicon

layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate

Polysilicon Patterning
Use same lithography process discussed
earlier to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide
n well
p substrate

Self-Aligned Process
Use gate-oxide/polysilicon and masking to
expose where n+ dopants should be
diffused or implanted
N-diffusion forms nMOS source, drain, and
n-well contact

n well
p substrate

N-diffusion/implantation
Pattern oxide and form n+ regions
Self-aligned process where gate blocks n-dopants
Polysilicon is better than metal for self-aligned gates
because it doesnt melt during later processing

n+ Diffusion

n well
p substrate

N-diffusion/implantation cont.
Historically dopants were diffused
Usually high energy ion-implantation used
today
But n+ regions are still called diffusion

n+

n+

n+
n well

p substrate

N-diffusion cont.
Strip off oxide to complete patterning step

n+

n+

n+
n well

p substrate

P-Diffusion/implantation
Similar set of steps form p+ diffusion
regions for PMOS source and drain and
substrate contact
p+ Diffusion

p+

n+

n+

p+

p+
n well

p substrate

n+

Contacts
Now we need to wire together the devices
Cover chip with thick field oxide (FO)
Etch oxide where contact cuts are needed
Contact

Thick field oxide

p+

n+

n+

p+

p+
n well

p substrate

n+

Metalization
Sputter on aluminum over whole wafer
Copper is used in newer technology
Pattern to remove excess metal, leaving wires

M etal

Metal
Thick field oxide
p+

n+

n+

p+

p+
n well

p substrate

n+

Physical Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor size
(and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process

Simplified Design Rules

Conservative rules to get you started

Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4-6/ 2, sometimes called 1 unit
In f = 0.25 m process, this is 0.5-0.75 m wide (W), 0.25
m long (L)
Since =f/2, =0.125 m.

by Dibyendu Roy et.al, IIT kgp data

Dibyendu Roy et.al, IIT kgp data

Dibyendu Roy et.al, IIT kgp data

Figure 1. FE-SEM images of

planar and cross-sectional view
of Ni43Ti49Cu8 thin films
deposited
at
substrate
temperatures of (a-b) 773K, (cd) 673K, (e-f) 573K and (g-h)
473K.

by Dibyendu Roy et.al, IIT kgp data

IC Technology
Speed / Power performance of available
technologies
The microelectronics evolution
SIA Roadmap (International Technology
Roadmap for Semiconductors)

Switches
Digital equipment is largely composed of switches
Switches can be built from many technologies
relays (from which the earliest computers were built)
thermionic valves
transistors
The perfect digital switch would have the following:
switch instantly
use no power
have an infinite resistance when off and zero resistance
when on
Real switches are not like this!

Semiconductors and Doping

Adding trace amounts of certain materials to semiconductors alters the
crystal structure and can change their electrical properties
in particular it can change the number of free electrons or holes

N-Type
semiconductor has free electrons
dopant is (typically) phosphorus, arsenic, antimony

P-Type
semiconductor has free holes
dopant is (typically) boron, indium, gallium

Dopants are usually implanted into the semiconductor using Implant

Technology, followed by thermal process to diffuse the dopants

Metal-oxide-semiconductor (MOS) and

related VLSI technology

pMOS
nMOS
CMOS
BiCMOS
GaAs

BiCMOS

A known deficiency of MOS technology is its limited load driving
capabilities (due to limited current sourcing and sinking abilities of
pMOS and nMOS transistors.

Bipolar transistors have
higher gain
better noise characteristics
better high frequency characteristics

BiCMOS gates can be an efficient way of speeding up VLSI circuits

CMOS fabrication process can be extended for BiCMOS

Example Applications
CMOS
- Logic
BiCMOS - I/O and driver circuits
ECL
- critical high speed parts of the system

VLSI DESIGN

Photo-litho-graphy: latin: light-stone-writing

Photolithography: an optical means for transferring
patterns onto a substrate.

Patterns are first transferred to an imagable
photoresist layer.

Photoresist is a liquid film that is spread out onto a
substrate, exposed with a desired pattern, and
developed into a selectively placed layer for
subsequent processing.

Photolithography is a binary pattern transfer: there
is no gray-scale, color, nor depth to the image.

Types of Photoresist
Negative Photoresist
Becomes insoluble
after exposure

Positive Photoresist
Becomes soluble after
exposure

When developed, the When developed, the

unexposed parts
exposed parts
dissolved.
dissolved
Cheaper

Better resolution

Negative and Positive Photoresists

Photoresist
Substrate
UV light
Mask/reticle
Photoresist

Exposure
Substrate

Negative
Photoresist
Substrate
Positive
Photoresist
Substrate

After
Development

Positive Photoresist

Novolac resin polymer

Sensitizer cross-linked within the resin
Energy from the light dissociates the
sensitizer and breaks down the crosslinks
Exposed part dissolve in developer
solution
Higher resolution
Commonly used in IC fabs

Negative Resist
Most negative PR are polyisoprene
type(an elastic hydrocarbon polymer)

Exposed PR becomes cross-linked
polymer

Unexposed part will be dissolved in
development solution.

Spin Coating

Wafer sit on a vacuum chuck

Slow spin ~ 500 rpm
Liquid photoresist applied at center
of wafer
Ramp up to ~ 3000 - 7000 rpm
Photoresist spread by centrifugal
force
Evenly coat on wafer surface

Photoresist Spin Coater

PR

Wafer

EBR
Water
Sleeve
Chuck
Drain

Exhaust
Vacuum

Photoresist Applying
PR dispenser
nozzle
Wafer

Chuck
Spindle
To vacuum pump

Photoresist Spin Coating

PR suck back

PR dispenser
nozzle
Wafer

Chuck
Spindle
To vacuum
pump

Photoresist Spin Coating

PR suck back

PR dispenser
nozzle
Wafer

Chuck
Spindle
To vacuum
pump

Photoresist Spin Coating

PR suck back

PR dispenser
nozzle
Wafer

Chuck
Spindle
To vacuum
pump

Photoresist Spin Coating

PR suck back

PR dispenser
nozzle
Wafer

Chuck
Spindle
To vacuum
pump

Photoresist Spin Coating

PR suck back

PR dispenser
nozzle
Wafer

Chuck
Spindle
To vacuum
pump

Relationship of Photoresist Thickness to Spin Rate and Viscosity

3.5
100 cst
3.0

Thickness (mm)

2.5
2.0
1.5
1.0
0.5
0

50 cst

27 cst
20 cst
10 cst
5 cst

2k

3k

4k

5k

Spin Rate (rpm)

6k 7k

Physical Vapour Deposition

techniques (PVD)
1.) Evaporation
2.) Sputtering
3.) Chemical Vapor Deposition (CVD)
4.) Electrochemical techniques

Evaporation:
Advantages: Highest purity (Good for Schottky contacts) due to
low pressures.
Disadvantages: Poor step coverage, forming alloys can be
difficult, lower throughput due to low vacuum.
Evaporation is based on the concept that there exists a finite
vapor pressure above any material. The material either
sublimes (direct solid to vapor transition) or evaporates (liquid
to vapor transition).

Evaporation Step Coverage

The step coverage of evaporated films is poor
due to the directional nature of the Evaporated
material (shadowing) (see figure 12-5). Heating
(resulting in surface diffusion) and rotating the
substrates (minimizing the shadowing) help
with the step coverage problem, but
evaporation can not form continuous films for
aspect ratios (AR=step height/step width or
diameter) greater than 1.
We need a less directional metalization
scheme====> Higher pressures!

Sputtering:
Advantages: Better step coverage, less
radiation damage than E-beam evaporation,
easier to deposit alloys.
Disadvantages: Some plasma damage
including implanted argon. Good for ohmics,
not Schottky diodes.
A plasma at higher pressure is used to
knock metal atoms out of a target. These
energetic atoms deposit on a wafer located
near the target. The higher pressure produces
better step coverage due to more random
angled delivery.
The excess energy of the ions also aids in
increasing the surface mobility
(movement of atoms on the surface).

SURVEY OF MICROSTRUCTURAL PROPERTY

RELATION
Table No 5: Microstructural property relation.

Film Microstructure

Property

Columnar

Optical property of this structure is not good.

In case of columnar structure mechanical property is very good.

Porous

Mechanical property of porous structure is bad.

Porous structure has bad electrical property.
Porous structure has good optical property.

Compact Featureless Electrical property is very good in compact featureless structure.

Optical property of compact featureless structure is not so good.
Exhibits very good mechanical proprty.
Crystal &
Amorphous

Mechanical property is good in crystal structure compared to

amorphous structure.
Crystal structure exhibits good electrical property than the
amorphous structure.
Comparing with amorphous material, crystal material has better
electrical properties.

E-beam Evaporation
Use an electron beam to provide the necessary heating
A hot filament emits electrons by
thermionic emission
The electrons are accelerated to
the source through a potential
difference of several to 15 kV
The electrons are steered by a Bfield via the Lorentz force to strike
the material to be evaporated

Advantages :
Electron K.E. is transferred as heat to the
evaporant causing it to locally melt; this avoids
contamination from the container
Hot crucibles are not in the line of sight of the
substrate
Disadvantage :
Energetic electrons and x-ray radiation may
damage some films so sputtering or CVD has
replaced e-beams for some applications (e.g.,
MOS devices)

Molecular Beam Epitaxy

Epitaxy: Deposition and growth of
monocrystalline structures/layers.
Epitaxial growth results in
monocrystalline layers differing from
deposition which gives rise to
polycrystalline and bulk structures.

MBE growth mechanism *

Epitaxy types:
Homoepitaxy: Substrate & material are
of same kind.
(Si-Si)
Heteroepitaxy: Substrate & material are
of different kinds. (Ga-As)
MBE growth mechanism **

 Molecular Beam Epitaxy (MBE)

Relies on the sublimation of ultrapure elements, then
condensation of them on wafer
In a vacuum chamber (pressure: ~10-11 Torr).
Beam: molecules do not collide to either chamber walls or
existent gas atoms.
Growth rate: 1m/hr.
Molecular Beam Epitaxy**

Advantages

Disadvantages

 Clean surfaces, free of an oxide layer

 Expensive (106 $ per MBE chamber)

 In-situ deposition of metal seeds,

 ATG instability

semiconductor materials, and dopants

 Low growth rate (1m/h)

 Very complicated system

 Precisely controllable thermal evaporation

 Epitaxial growth under ultra-high vacuum

conditions

 Seperate evaporation of each component

 Substrate temperature is not high
 Ultrasharp profiles

Applications of MBE

Novel structures as quantum devices

Silicon/Insulator/Metal Sandwiches
Superlattices
Microelectronic Devices

Advantages of PLD

Flexible, easy to implement

Growth in any environment
Exact transfer of complicated materials (YBCO)
Variable growth rate
Epitaxy at low temperature
Resonant interactions possible (i.e., plasmons in metals, absorption peaks in
dielectrics and semiconductors)
Atoms arrive in bunches, allowing for much more controlled deposition
Greater control of growth (e.g., by varying laser parameters)

Disadvantages of PLD

Uneven coverage
High defect or particulate concentration
Not well suited for large-scale film growth
Mechanisms and dependence on parameters not well
understood

calculate