GRD Journals | Global Research and Development Journal for Engineering | International Conference on Innovations in Engineering and Technology

(ICIET) - 2016 | July 2016

e-ISSN: 2455-5703

Partial Reconfiguration using FPGA A Review

1M.

Jothi 2Dr. N. B. Balamurugan 3Dr. R. Harikumar

1
Department of Information Technology 2,3Department of Electronics and Communication Engineering
1
K.L.N College of Engineering Pottapalayam, Sivagangai 630612, India 2Thiagarajar College Of
Engineering, Madurai 3Bannari amman Institute of Technology, Sathyamangalam
Abstract
This paper proposes a review on Partial reconfiguration using Field Programmable Gate Array (FPGA). By downloading
configuration bit files Partial Dynamic Reconfiguration (PDR) dynamically modifies the hardware portion of the device. Both
FPGA and reconfigurable are used to speed up the performance of various applications. This makes the FPGA to be used in new
dimension with an advantage of more flexibility. Literature surveys on various reconfigurable computing techniques were
performed with the results and discussions. A more suitable method can be selected based on the applications. A main contribution
of this review paper is that it summarizes the current research, key enabling techniques, applications, Research issues and
challenges in Partial reconfiguration. All these application are described with its basic block and its implementation.
Keyword- Partial reconfiguration, FPGA, Static Reconfiguration, Dynamic Reconfiguration, Partial Dynamic
Reconfiguration
__________________________________________________________________________________________________

I. INTRODUCTION
Reconfigurable computing plays an important role in this modern world. Select areas of an FPGA can be reconfigured any time
after its initial configuration using Partial reconfiguration. Recent FPGA system allows the designer to update reconfigure only a
specific part of FPGA internal structure. It has been used in various application like in the field of Hardware upgrades and remote
area updates, Adaptive hardware algorithm, Run time Reconfiguration. Some important technical terms are Bit stream:
Configuration data which can be downloaded into the device via the configuration port.
Packet: Fragment of the complete bit stream sent to the device
Configuration Memory: Processor memory dedicated for reconfiguration process.
Dirty packets: Marked packets showing the changes made between last configuration and the present one. Only a single bit
stream has been generated using FPGA regular synthesis. In contrast the PR flow physically divides the device in two regions.
One is Static region which is the portion of the device is programmed at starting stages and never changes. In second method,
the portion of the device will be reconfigured dynamically, potentially, multiple times and different designs. The two important
benefits of Partial Dynamic Reconfiguration (PDR) on reconfigurable hardware.
1) The reconfigurable area can be exploited more efficiently with respect to the static design
2) Some portion of the application must change over time and react to changes in its environment.
Partial Dynamic Reconfiguration (PDR) act as a middle point in the trade-off between speed of HW solutions and the
flexibility of SW. PDR can be implemented using Xilinx & Altera tool.

II. RECONFIGURABLE COMPUTING

A. Modular Reconfiguration using FPGA
Sedcole et al. describes the reconfigurable computing using FPGA. Modular systems implemented on field-programmable gate
arrays (FPGAs) can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the
research community. Although dynamic partial reconfiguration is possible in Virtex and Spartan series FPGAs, the configuration
architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical
or compromised resource allocation models. Two methods for implementing modular reconfiguration in Virtex FPGAs are
compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity
of the system. The second method, developed recently, enables modules to be allocated arbitrary areas of the FPGA, bridging the
gap between theory and reality and unlocking the latent potential of dynamic reconfiguration. The cost of this advancement is
increased reconfiguration time.

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Partial Reconfiguration using FPGA A Review

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Fig. 1: Virtex-II configuration architecture

The second method had been demonstrated in three applications, including the first reported implementation of modular
reconfiguration in a Virtex-4. In this paper, two methods for implementing modular partial reconfiguration on Virtex FPGAs are
compared. The first method is, applicable to Virtex, Virtex-II and Virtex-II Pro devices, modules must occupy the full height of
the device and the topology and connectivity are limited to 1D. This we term direct dynamic reconfiguration: it is fast and simple,
and has been previously documented by Lim and Peattie. The second method, recently developed by the authors, demonstrates
how 2Dmodular systems can be made tractable through the use of an innovative bit stream merging process and reserved routing.
Figure 1 shows the Virtex-II configuration architecture.
B. Partially Reconfigured FPGA with Global Floorplan
The authors Pritha Banerjee et al. propose a global floorplan generation method. Partial Hetero FP to obtain same positions for the
common modules across all instances. The Phase I is PartialHeteroFP, In Phase II, a set of slicing trees preliminary rectangular
region is assigned to each of its modules depending on the similarities between the slicing trees for different instances, a set of
groups is generated. In reconfiguration algorithm output is given as follows
A Partition tree i for each Ii as template for its slicing trees Bi-Partition netlist for SM into two super modules L, R;
for each instance Ii do
Bi-partition the netlist Si once such that L is in the left partition and R in right one;
While there are more than one module per partition
do
Recursively perform balanced min-cut bi-partitioning;
Swap sub-trees if required to retain L and R as leftmost and rightmost leaves;
C. Mobile Robot Application

Fig. 2: Architecture for intelligent reconfigurable mobile robots

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Partial Reconfiguration using FPGA A Review

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The author Tadigotla presents a methodology for the realization of intelligent, task-based reconfiguration of the computational
hardware for mobile robot applications. Task requirements are first partitioned into requirements on the system hardware and
software.
Architecture is proposed that enables these requirements to be addressed through appropriate hardware and software
components. Figure 2 displays the reconfigurable mobile robot architecture. Hardwaresoftware co-design and hardware
reconfiguration are utilized to design robotic systems that are fault-tolerant and have improved reliability. It is shown that this
design enables the implementation of efficient controllers for each task of the robot thereby permitting better operational efficiency
using fixed computational resources. The approach is validated through case studies where a team of robots is configured and the
behavior of the robots is dynamically modified at run-time. It is demonstrated through this implementation that the design
procedure results in increased flexibility in configuration at run-time. The ability to reconfigure the resources also aids
collaboration between robots, and results in improved performance and fault tolerance.
D. DSP Filter Application

Fig. 3: Simulated Waveform for FIR Filter.

FIR filters are employed in the majority digital signal processing (DSP) based electronic systems by the author. Figure. 3 show
the simulated form of FIR filter. The emergence of demanding applications (image, audio/ video processing and coding, sensor
filtering, etc.) in terms of power, speed, performance, system compatibility and reusability make it imperative to design the
reconfigurable architectures. This paper presents a partially reconfigurable FIR filter design that targets to meet all the objectives
are low-power consumption, autonomous adaptability reconfigurability, fault-tolerance etc. on the FPGA. FPGAs are
programmable logic devices that permit the implementation of digital systems. They provide an array of logic cells that can be
configured to perform a given functionality by means of a configuration bit stream. Many of FPGA systems can only be statically
configured. Static reconfiguration means to completely configure the device before system execution. If a new reconfiguration is
required, it is necessary to stop system execution and reconfigure the device it over again. Some FPGAs allow performing partial
reconfiguration, where a reduced bit stream reconfigures only a given subset of internal components. Dynamic Partial
Reconfiguration (DPR) allows the part of FPGA device be modified while the rest of the device (or system) continues to operate
and unaffected by the reprogramming .
Module-based partial reconfiguration was proposed by Xilinx. And now many researchers have proposed many partial
reconfiguration methods (JBits, PARBIT, etc). The modular design flow allows the designer to split the whole system into modules.
The partial reconfiguration of reconfigurable symmetric transposed FIR filters was implemented on Xilinx. Virtex2pro FPGA
device using test environment. XUPV2P FPGA test board and Agilent logi analyzer were used for board level verification. And
configuration bitstream download is operated by Xilinx Platform Cable USB and IMPACT. For dynamic partial reconfiguration
experiment, the partial reconfigurable module1 and module2 were reconfigured bypass module and 4-tap module respectively
while other areas of modules remain operational. For verification, we have performed following two methods. First, 12-tap and
20-tap FIR filters before/after partial reconfiguration have been simulated to verify the output results on FPGA test board using
Xilinx ChipScope Pro Analyzer.

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Partial Reconfiguration using FPGA A Review

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E. Erlang Slot Machine

Fig. 4: ESM Architecture overview

Mateusz Majer et al. was designed the erlangen slot machine. The Erlangen Slot Machine is used for the development of a new
FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural
constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The
uniqueness of this computer stems from (a) a new slot-oriented hardware architecture, (b) a set of novel inter-module
communication paradigms, and (c) concepts for dynamic and partial reconfiguration management. Figure 4 show the ESM
architecture overview and Figure 5 display the ESM Babyboard and Motherboard implementation.

Fig. 5: Implementation of the ESM BabyBoard and Mother- Board

F. Dynamic Reconfiguration FPGAs

Fig. 6: V-4 LX25 with 4 partially reconfigurable regions

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Patrick Lysaght et al. describe the architectural enhancements to Xilinx FPGAs that provide better support for the creation of
dynamically reconfigurable designs. Figure 6 displays the V-4 LX25 with 4 partially reconfigurable regions. These are augmented
by a new design methodology that uses pre-routed IP cores for communication between static and dynamic modules and permits
static designs to route through regions otherwise reserved for dynamic modules. A new CAD tool flow to automate the
methodology is also presented. The new tools initially target the Virtex-II, Virtex-II Pro and Virtex-4 families and are derived from
Xilinxs commercial CAD tools. It consists of 7 design phase.

III. RELATED WORK

Zaidi et al. explained the Power/Area Analysis of a FPGA Based Open Source processor using Partial Dynamic reconfiguration.
Utilization of run-time partial dynamic reconfiguration in Michael G. Lorenz et al paper using LEON 3 open source soft core
processor It explains the possibilities of sharing different arithmetic tightly coupled to the integer pipeline and same silicon area.
Author Eto Emi et al. discusses the difference based Partial reconfiguration design flow described in this application note
allows a designer to make logic changes using FPGA-Editor and generate a bitstream that programs only the difference between
the two versions of the design. Switching the configuration of a module from one implementation to another is very quickly because
the bitstream defences can be much smaller than the entire device bitstream.
Moraes et. al describes the dynamic and partial reconfiguration on System On Chips(SOCs)
dynamic partial reconfiguration, also known as an active partial reconfiguration - permits to change the part of the device
while the rest of an FPGA is still running;
Static partial reconfiguration - the device is not active during the reconfiguration process. While the partial data is sent into
the FPGA, the rest of the device is stopped (in the shutdown mode) and brought up after the configuration is completed.
Blodget et al. explains that how the partial and Dynamic reconfiguration can be involved in adaptive systems. To solve
the problem of substitution and I/o management main module is preferred to control the block.
Open Source Partial reconfiguration (Open PR) toolkit for Xilinx FPGAs were designed by the author Sohanghpurwala
et al.The Xilinx Partial Reconfiguration Early Access Software Tools for ISE 9.2i is superseded with the corresponding non free
add-on for ISE 12.3 for performing wide variety of research on Xilinx FPGAs. Rectangular partial reconfiguration modules could
be swapped in and out of a static baseline design with one or more PR slots. Being released as open source, it can be satisfies the
needs of individual researcher with free of cost.
Author Abhishek tiwari outlines a new approach of Digital Frequency Synthesis in conjunction with FPGA clock
managers. Flexibility and Programmability provided by the FPGA is critical to the scope of applications they can support. FPGA
configuration data at run time specific portion can be substituted using Partial and Dynamic reconfiguration.. Author proposed
frequency synthesis using Dynamic Reconfiguration Port (DRP) of a Digital Clock manager primitive through the reconfigurable
module in the fabric. Module hierarchy details, Design and simulation results, partial reconfiguration based implementation flow,
Quantitative comparison were discussed.
Solomon Raju et al. presents the algorithm for PR flow and implementation of Reconfigurable Modules(RM)on Xilinx
Virtex-4(XC4VFX12).Modelsim 6.0d simulation tool and Xilinx 9.1i (ISE) synthesis tool were used. Device utilization summaries,
resources used by the static and Dynamic Top module were discussed with the hyper terminal.

IV. CONCLUSIONS
From this review, the authors focus on various types of reconfigurable computing especially on FPGA This paper starts with an
introduction of Reconfigurable computing, after that various applications using reconfigurable computing were discussed with its
research issues. This Partial reconfiguration overcomes many architectural constraints of existing platforms and becomes the user
friendly. There are still challenging issues to be addressed in partial reconfiguration. Most complex issues must be checked by this
technique. It is concluded that the Dynamic reconfiguration optimizes the use of hardware resources and produce reduction in
power consumption. Thus the reconfigurable architectures offers user to deploy and implement many exciting application in the
same device.

REFERENCES
[1] Abhishek Tiwari. A Partial Reconfiguration based Approach for Frequency Synthesis using FPGA. (2012) International
Conference on Communication technology and system Design, Elsevier, procedia engineering,30, 234-241.
[2] Alireza shoa, Shahram Shirani (2005). Run-Time Reconfigurable Systems for Digital Signal Processing Applications: A
Survey, Journal of VLSI Signal Processing , , Springer, 39, 213235.
[3] Blodget, Brandon, et al.(2004), Partial and dynamically reconfiguration of Xilinx Virtex-II FPGAs, Field Programmable Logic
and Application. Springer Berlin Heidelberg, 2004. 801-810.
[4] Eto, Emi, (2007), Difference-Based Partial Reconfiguration. "XAPP290 (v2. 0), Xilinx, Inc., San Jose, CA, USA: 1-11.
[5] Kessal.Lounis, R. Bourguiba, D. Demigny, N. Boudouani, Karabernou. M. (2002), Reconfigurable Architecture Using High
Speed FPGA. SOC Design Methodologies, Springer US 75-86.

All rights reserved by www.grdjournals.com

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[6] Lorenz, M. G., Mengibar, L., Valderas, M. G., & Entrena, L.

(2004). Power consumption reduction through dynamic
reconfiguration. Field Programmable Logic and Application, Springer Berlin Heidelberg, 751-760,
[7] Mateusz majer, Jurgen teach (2007),The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer.
Journal of VLSI Signal Processing (47), 1531.
[8] Moraes, Fernando, Ney calazans, leandro moller, Eduardo Briao, Ewerson carvalho, (2005), Dynamic and partial
reconfiguration in FPGA SoCs: requirements tools and a case study. New Algorithms, Architectures and Applications for
Reconfigurable Computing. Springer US, 157-168.
[9] Patrick Lysaght, Brandon Blodget, Jeff Mason , Jay Young, Brendan Bridgford .Enhanced architectures, design methodologies
and CAD tools for dynamic reconfiguration of xilinx FPGAs.(2006),, Xilinx research lab paper
[10] Pritha Banerjee, Megha sangtani, susmita sur-kolay (2009).Floorplanning for Partial Reconfiguration in FPGAs. 22nd
International conference on VLSI Design,
IEEE Explore
[11] Sedcole, B. Blodget, T. Becker, J. Anderson and P. Lysaght (2006). Modular reconfiguration using FPGA. IEEE Proc.Comput. Digit. Tech., 153(3), 157.
[12] Sohanghpurwala, A, A, Athanas, P.Erangieh, T. wood. A. Open PR:An Open Source Partial Reconfiguration Toolkit for
Xilinx FPGAs.(2011) IEEE International
symposium on Partial and Distributed Processing
Workshops.
[13] Solomon Raju Kota, Ashutosh Gupta, shashikant nayak, sreekanth Varma. Module Based Implementaion of partial
reconfiguration using VHDL on Xilinx FPGA (2009), Interntional Journal of recent Trends in Engineering, 2(7).
[14] Tadigotla. V & L. Sliger Sesh Commuri (2007). Task-based Hardware Reconfiguration in Mobile Robots Using FPGAs. J
Intell Robot System 49: Springer, 111134,
[15] Zaidi, I, Nabina, A. canagarajah, C. N, Nunez Yanez. J, Power/Area Analysis of a FPGA-Based Open-Source Processor using
Partial Dynamic Reconfiguration, Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th
EUROMICRO Conference 2008,592-598

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