To Learn About The Op-Amp Based Schmitt Trigger Circuit and Understand Its Working

1.
EXPERIMENT NO: 01
2. TITLE: SCHMITT TRIGGER
3. LEARNING OBJECTIVES:
To learn about the Op-Amp based Schmitt trigger circuit and understand its working.
To learn simulation of Op-Amp based Schmitt trigger circuit.
4. AIM:
To design and implement an inverting Schmitt trigger using Op-Amp for a given
UTP and LTP values. .
To implement a Schmitt trigger using Op-amp using a simulation package for two
sets of UTP and LTP values.

5. MATERIAL / EQUIPMENT REQUIRED:
S. No
Components/Equipments
Specification/No
Quantity
Op-Amp
uA741
Resistor
10K
1K
DC Regulated Power Supply
Signal Generator
CRO
6. THEORY / HYPOTHESIS:
Schmitt Trigger converts an irregular shaped waveform to a square wave or pulse.
Here, the input voltage triggers the output voltage every time it exceeds certain
voltage levels called the upper threshold voltage V UTP and lower threshold voltage
VLTP. The input voltage is applied to the inverting input. Because the feedback
voltage is aiding the input voltage, the feedback is positive. A comparator using
positive feedback is usually called a Schmitt Trigger. Schmitt Trigger is used as a
squaring circuit, in digital circuitry, amplitude comparator, etc.
7. PROCEDURE / PROGRAMME / ACTIVITY:
1. Test all the components.
2. Rig up the circuit according to the circuit diagram.
3. Apply VCC =12V, VEE = -12V.
4. Apply a sinusoidal signal of peak voltage say 5V, with a frequency of 500Hz.
5. Observe the rectangular output on the CRO, measure the UTP and LTP values,
compare them with the design values.
6. Keep the CRO in X-Y mode (Vin to X-channel, Vout to Y-channel). Observe the
transfer curve which is called the Hysteresis curve.
8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:
a) Hardware Implementation
b) Simulation
Case 1: UTP =_____V, LTP = ______V
Case 2: UTP =_____V, LTP = ______V
9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a)

1. Vin-p =_________ V
2. Input period T =________ mS
3. UTP = _________ V
4. LTP =__________ V
b)
5. +Vsat =___________V
6. Vsat =_________ V
Case 1: UTP= ___________V, LTP=
Case 2: UTP =
V , LTP =
10. FORMULA / CALCULATIONS:
UTP(Upper Trip Point) is the point in the raising part of input waveform, at which the
output voltage changes state . LTP (Lower Trip Point) is the point in the falling part
of the input waveform, at which the output changes state. The above state change
of output occurs when the input voltage crosses V ref
UTP = BVsat
LTP = -BVsat
Where B is called the feedback fraction. It is the part of the output voltage fed back
to the input (pin 3)
B = R2/ (R1+R2)(by potential divider principle)
+Vsat : It is the output voltage. Ideally it is either +V cc or VEE respectively.
(Practically it will be a little less than this value)
Let us design an inverting Schmitt trigger for a UTP =+1V and LTP = -1V
Let VCC = +12V (= +Vsat)
VEE= -12V (= -Vsat) , R2 =1K
We know UTP = +BVsat , ie 1V= (R 2 /(R1 + R2))12V

ie 1 = 1K/ (R1 + 1K )* 12
R1 + 1K =12K
R1=12K -1K = 11K
The above design will set an LTP =

-1V 11. GRAPHS / OUTPUTS:
12. RESULTS & CONCLUSIONS:

a)The difference between UTP and LTP is defined as
Hysteresis is: H=UTP LTP =_______V - V = __________V
13. LEARNING OUTCOMES :
Hence from this experiment we can conclude that Opamp Schmitt trigger circuit
converts sine wave to square wave for a given threshold voltage.
Simulation results of Op Amp Schmitt trigger circuit matches with practical values.
14. APPLICATION AREAS:
Function Generator.
Noise immunity and Oscillator.
15. REMARKS::
1. EXPERIMENT NO: 2
2. TITLE: RELAXATION OSCILLATOR
To learn about the rectangular waveform generator circuit and understand its working.
To learn to implement a rectangular waveform generator using a simulation package.
4. AIM:
To design and implement a rectangular waveform generator(op-amp relaxation
oscillator) for a given frequency.
To implement a rectangular waveform generator (Op-amp relaxation oscillator)
using a simulation package, and observe the change in frequency when all the
resistors values are doubled
5.
MATERIAL / EQUIPMENT REQUIRED:
S. No
Specification/No
Quantity
Op-Amp
uA741
Resistor
1K,10K, 1.8K
1 each
Capacitor
0.1u
Regulated Power Supply
CRO
As the name indicates, here there is no input signal, but circuit produces a square
wave output that swings between +Vsat and Vsat. The capacitor charges through the
feedback resistor R, exponentially towards +Vsat. But capacitor voltage never reaches
+Vsat because the voltage crosses the UTP. When this happens the output wave
switches to Vsat. With the output now in negative saturation, the capacitor discharges.
When the capacitor voltage crosses through zero, the capacitor starts charging
negatively toward Vsat.When the capacitor voltage crosses the LTP, output switches
back to +Vsat. The above events repeat, resulting in rectangular output.
1. Check all the components
2. Rig-up the circuit according to the circuit diagram.
3. Apply +Vcc of say 15V and VEE of -15V.
4. Connect the CRO channel-1 across the capacitor and channel-2 across the output.
5. Observe the output rectangular waveform and capacitor waveform.
6.Calculate the period of the waveform, T.
7. Note down the out put voltage (+Vsat and Vsat) and UTP and LTP
voltages. (Observed Vsat will be < +Vcc and | - Vsat | < | -V EE |)
8. Draw the graph of the output waveform and the capacitor voltage waveform.
8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION

EQUATION: a) Hardware Implementation
b) Simulation
Case 1: for the original circuit
Case 2: Circuit with all resistors doubled
9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

a)
i) Period, T =
ms
ii) +Vsat =
V
iii) -Vsat = V
iv) UTP = +
V
v) LTP = V
b)
Case 1: Period of the output waveform =
___________ms Frequency f = ___________Hz
Case 2: With all resistors doubled:

Period of the output waveform =____________ms
Frequency f = ___________Hz
10.
FORMULA / CALCULATIONS:
11. The output is a rectangular wave with a duty cycle of 50 %. (i.e., high duration
= low duration). The period of the output wave is given by,
Let us choose R1= 1.8K.

The maximum voltage across the capacitor is the UTP and minimum
voltage across the capacitor is the LTP.
UTP = +BVsat and LTP = -BVsat
The output waveform swings between +Vsat and

Vsat) 11. GRAPHS / OUTPUTS:
Frequency of output waveform =1/T =

Frequency of output waveform in simulation=1/T =
Hz
Hz

From this experiment we can conclude that relaxation oscillator can be used to
generate rectangular waveforms of desired frequency.
Relaxation oscillator circuit can be simulated using PSPICE simulator and the
results are matching with the practical values.

Voltage controlled oscillators (VCOs)
Switching power supplies.

Dual -slope analog to digital converters.
function generators.
14. REMARKS::
1. EXPERIMENT NO: 03
2. TITLE: ASTABLE MULTIVIBRATOR
To learn about the astable multivibrator circuit using 555 timer for a given frequency
and duty cycle.
4. AIM:
To design and implement an Astable multivibrator using 555 timer, for a given
frequency and duty cycle.
5.
MATERIAL / EQUIPMENT REQUIRED:
S. No
Specification/No
Quantity
Timer
NE 555
Resistor
3.3K, 6.8K
1 each
Capacitor
0.1u, 0.01u
1 each
DC Regulated Power Supply
CRO
Multivibrator is a form of oscillator, which has a non-sinusoidal output. The
output waveform is rectangular. When 555 timer is used as astable multivibrator,
it has no stable states, which means it cannot remain indefinitely in either state.
This results in rectangular output.
The multivibrators are classified as:
Astable or free running Multivibrator: It alternates automatically between two
states (low and high for a rectangular output) and remains in each state for a
time dependent upon the circuit constants. It is just an oscillator as it requires
no external pulse for its operation.
Monostable or one shot Multivibrator: It has one stable state and one quasi stable
state. The application of an input pulse triggers the circuit time constants. After a
period of time determined by the time constant, the circuit returns to its initial stable
state. The process is repeated upon the application of each trigger pulse.
Bistable Multivibrators on other hand have both stable states. It requires the
application of an external triggering pulse to change the output from one
state to other. After the output has changed its state, it remains in that state
until the application of next trigger pulse.
1. All the components are tested.
2. Circuit is rigged up according to the circuit diagram.
3. Connect CRO-CH1 to pin no.6 (or 2) and CH2 to pin no.3 (Vout) of the 555.
4. Apply a Vcc of +10V.
5. Observe the capacitor voltage waveform at pin no.6. Observe the output
waveform at pin no.3.
6. Note down the period, pulse width, UTP, LTP and V H values.
7. Plot the graph of output waveform and capacitor voltage waveform. (UTP= 2/3 Vcc, LTP
8.
= 1/3 Vcc, as per theory)

BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:
9.
OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:
1.
2.
3.
3.
4.
5.
Period,T = _________ms
Therefore frequency, f =_________Hz
Pulse width, W =___________ms
Duty cycle, D = W/T = ________%
UTP =_________V
LTP=_________V
6. High level of output, VH =__________Volts. (Low level is zero volts).

When 555 timer IC is connected to run as an Astable multivibrator, it gives
rectangular output. Let T be the period of the output waveform. Then duration of T
during which output is high,
11. GRAPHS / OUTPUTS:

The various values are as expected. Frequency of output waveform =
Hz.
Duty cycle = ___________%
From this experiment we can conclude that square waveforms of desired
frequency can be generated using 555 timer based astable multivibrator.
Multivibrator.
Embedded Applications.
15. RESULT:
2. TITLE: ADDERS AND SUBTRACTORS
To realize the half adder circuits using basic gates.
To realize the half substractor circuits using basic gates.
To realize the full adder circuits using basic gates.

To realize the full substractor circuits using basic gates.
4. AIM:
To realize Half Adder and Full Adder using Basic gates.
To realize Half Substractor and Full Substractor using Basic gates.
IC7404,7408,7432.
Patch Cords, IC Trainer Kit.
Adder circuit is a combinational digital circuit that is used for adding two numbers. A
typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by
C) as the output. Adder circuits are of two types: Half adder ad Full adder.
Half-Adder: A combinational logic circuit that performs the addition of two data bits,
A and B, is called a half-adder. Addition will result in two output bits; one of which is
the sum bit, S, and the other is the carry bit, C.
Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder.
Subtractor is the one which used to subtract two binary number(digit) and provides
Difference and Borrow as a output.In digital electronics we have two types of
subtractor. Half Subtractor and Full Subtractor.
Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit
from another single bit binary digit.
Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary digit is
known as Full Subtractor.Adder circuit is a combinational digital circuit that is used for
adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry
bit (denoted by C) as the output. Adder circuits are of two types: Half adder ad Full adder.
Half-Adder: A combinational logic circuit that performs the addition of two data bits,
A and B, is called a half-adder. Addition will result in two output bits; one of which is
the sum bit, S, and the other is the carry bit, C.
Full-Adder: The half-adder does not take the carry bit from its previous stage into account.
This carry bit from its previous stage is called carry-in bit. A combinational logic circuit that
adds two data bits, A and B, and a carry-in bit, Cin , is called a full-adder.
Subtractor is the one which used to subtract two binary number(digit) and provides
Difference and Borrow as a output.In digital electronics we have two types of
subtractor. Half Subtractor and Full Subtractor.
Half Subtractor :Half Subtractor is used for subtracting one single bit binary digit
from another single bit binary digit.
Full Subtractor : A logic Circuit Which is used for Subtracting Three Single bit Binary
digit is known as Full Subtractor.
Make connections as shown in the circuit diagram.
Verify the Truth Table and observe the outputs.
IC 7404 PIN DIAGRAM
IC 7408 PIN DIAGRAM
Diffe
renc
e=a
b+a
b
Borr
ow
= a
b
Difference = a b c + a b c + a b c + a b c
Borrow = a c + a b + b c
N/A
N/A
The truth table of half adder, half subtractor, full adder and full subtractor is verified.
Students will be able to design half adder, half subtractor, full adder and full
subtractor using basic gates.
Used in the design of ripple counters.
Half adders can be used to design full adders.
15. REMARKS::
2. TITLE: EVM & 8:1 MUX
To learn about various applications of multiplexer.
To learn and understand the working of IC 74151.
To learn to realize any function using Multiplexer.
To develop a Verilog code for an 8:1 Multiplexer using dataflow modeling in Xilinx
simulator.
4. AIM:
To simplify 4 variable logic expression, simplify it using Entered Variable Map and
realize the simplified logic expression using 8:1 Multiplexer IC.
To develop the Verilog / VHDL code for an 8:1 multiplexer, simulate and verify its
working.
IC 74151, IC 7404
Patch Cords & IC Trainer Kit
PC with Windows XP, XILINX software.
Multiplexer means many into one. A multiplexer is a circuit with many inputs,
but only one output. By using control signals, we can connect any input to the
output. Hence, it is also known as Data Selector.
Map Entered Variable
Rules for entering values in a MEV K-map:

Rule
No.
1
2
3
7
8.
9
MEV f
Entry in MEV
Map
0
1
0
1
0
1
1
0
Comments
If function equals 0 for both values of MEV, enter
0
1
MEV
-----MEV
0
1
1
0 in appropriate cell of MEV Map.

If function equals 1 for both values of MEV, enter 1.
If function equals MEV enter MEV
If the function is compliment of MEV, enter MEV.
If function equals don't care for both values of MEV, enter .
Iff = 0 for MEV= 0 and f=0 for MEV=1, enter 0.
Iff = 0 for MEV= 0 and f=- for MEV=l, enter 0.
Iff = for MEV= 0 and f=1 for MEV=1, enter 1.
Iff = 1 for MEV= 0 and f=- for MEV= , enter .
Assume that the following 4-variable Boolean function is to be implemented using

8:1 multiplexer IC 74151.
Y = F(A,B,C,D) = (0,1,2,4,5,6,8,9,12,13,14).
Entered Variable Map Simplification and the simplified expression is shown below:
The Entered Variable Map Truth-Table corresponding to the above expression is shown below:
IC 74151 is an 8-channel digital multiplexer having 8- data inputs D0D7, three select
lines (MSB)ABC(LSB) and two complementary outputs designated as Y and Y. IC
7404 contains 6-inverters. IC 74151 and IC 7404 are inserted into the separate sockets
in the digital trainer. In IC 74151 Pin 16 is Vcc and Pin 8 is Ground. In IC 7404 in 14 is
Vcc and Pin 7 is Ground. Vcc pins of both the ICs are connected to +5V dc power
source pin. Ground pins of both the ICs are connected the Ground points in the trainer.
The circuit is rigged up as shown in the following diagram.
Inputs D0 through D7 are connected as shown in the diagram and as required by the
function to be implemented. Output Y (Pin 5) is connected to LED. To enable the IC 74151,
Pin 7 (Enable Pin) which is active low is connected to GND. Additional input D (LSB)
derived from a switch is connected to Pin 1 of IC 7404. Pin 2 (output) of IC 7404 is D and
hence connected to Pin 3, Pin 1 and Pin 12 of IC 74151constituting D1, D3, and D7
respectively. Pin 14 (D5) of IC 74151 is grounded remaining D input pins to the Vcc.
Inputs ABCD are varied by making the corresponding switches ON or OFF,

according to the truth table below and the output observed in the LED (ON =1; OFF = 0) is
verified for correctness.
Pin Diagram:
IC 74151 (8:1 MUX)
Circuit Diagram:
IC 7404(NOT Gate)
b) Simulation
module
Library IEEE;
Use IEEE.STD_Logic_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity mux8 is
Port(I:in std_Logic_vector(7 downto 0);
Sel: in std_logic_vector (2 downto 0);
Zout: out std_logic_vector);
End mux8;
Architecture Behavioral of mux8 is
Begin
Process(sel)
Begin begin
case sel is
when 000=>Zout<= I(0); when 001 =>Zout<= I(1); when 010 =>Zout<=I(2);
when 011 =>Zout<=I(3); when 100 =>Zout<=I(4); when 101 =>Zout<=I(5);
when 110 =>Zout<= I(6); when 111 =>Zout<= I(7); when others=>null;
end case;
end process;
end behavioral;

N/A

A four-variable logic expression is simplified using entered variable map and is
verified using 8:1 multiplexer.
We can conclude that using an Entered variable map a four variable logic
expression can be simplified so that it can be implemented using an 8:1 Multiplexer.
Thus it can also be concluded that a multiplexer sometimes works as an universal
logic circuit because a 2 nto1 multiplexer can be used as a design solution for any
n variable truth table.
Programmable Logic Devices.
Multiplexing.
Digital Subscriber Line Access Multiplexer.
15. RESULT:
2. TITLE: Code Converters
To learn the importance of non-weighted code.
To learn to generate gray code.
4. AIM:
Design and implement code converter I)Binary to Gray II)Gray to Binary Code
using basic gates.
IC 7404 1, IC 7432 2, IC 7411 2 or IC 7486 2
Binary Codes: A symbolic representation of data/ information is called code. The
base or radix of the binary number is 2. Hence, it has two independent symbols.
The symbols used are 0 and 1. A binary digit is called as a bit. A binary number
consists of sequence of bits, each of which is either a 0 or 1. Each bit carries a
weight based on its position relative to the binary point. The weight of each bit
position is one power of 2 greater than the weight of the position to its immediate
right. e. g. of binary number is 100011 which is equivalent to decimal number 35.
Gray Codes: It is a non-weighted code; therefore, it is not a suitable for arithmetic
operations. It is a cyclic code because successive code words in this code differ in
one bit position only i.e. it is a unit distance code.
Applications of Gray Code:

In instrumentation and data acquisition system where linear or angular
displacement is measured.
In shaft encoders, input-output devices, A/D converters and the other peripheral equipment.
Code Converters: The availability of a large variety of codes for the same discrete
elements of information results in the use of different codes by different digital
systems. It is some time necessary to use the output of one system as the input to
the other. The conversion circuit must be inserted between the two systems if each
uses different codes for the same information. Thus a code converter is a circuit
that makes the two systems compatible even though each uses the different code.
Check all the components for their working.
Insert the appropriate IC into the IC base.
Make connections as shown in the circuit diagram.
Verify the Truth Table and observe the outputs
IC 7411 Pin Diagram
IC 7486 Pin Diagram
Binary to Gray code converter
BOOLEAN EXPRESSIONS:
G3=B3
G2=B3B2 = B3B2 + B3B2
G1=B1B2 = B1B2 + B1B2
G0=B1B0 = B1B0 + B1B0
Gray to binary code converter
or
BOOLEAN
EXPRESSIONS: B3 = G3
B2 = G3G2 = G3G2 + G3G2
B1 = G3G2G1 = G3(G2G1 + G2G1)
= G3(G2G1 + G2G1)' + G3(G2G1 + G2G1)
= G3(G2 G1 + G2G1) + G3(G2G1 + G2G1)
= G3G2 G1+ G3G2G1+ G3G2G1+G3

G2G1 B0=G3G2G1G0

N/A
N/A
Binary to gray code conversion and vice versa is realized using basic gates.
Binary to gray code conversion and vice versa is implemented using basic gates.
Code conversion.
Encoding and decoding.
15. REMARKS::
2. TITLE: PARITY GENERATOR AND CHECKER
To implement parity generator and parity checker using basic gates.
4. AIM:
Design and verify the Truth Table of 3-bit Parity Generator and 4-bit Parity
Checker using basic Logic Gates with an even parity bit.
IC7404 1, IC7411 2, IC7432 2 or
IC7486 1
Trainer kit, patch cords.
Parity Generator: It is combinational circuit that accepts an n-1 bit stream data and
generates the additional bit that is to be transmitted with the bit stream. This
additional or extra bit is termed as a parity bit.
In even parity bit scheme, the parity bit is 0 if there are even number of 1s in the
data stream and the parity bit is 1 if there are odd number of 1s in the data stream.
In odd parity bit scheme, the parity bit is 1 if there are even number of 1s in the
data stream and the parity bit is 0 if there are odd number of 1s in the data stream.
Let us discuss both even and odd parity generators.
Parity Check: It is a logic circuit that checks for possible errors in the transmission.
This circuit can be an even parity checker or odd parity checker depending on the
type of parity generated at the transmission end. When this circuit is used as even
parity checker, the number of input bits must always be even.
When a parity error occurs, the sum even output goes low and sum odd output goes
high. If this logic circuit is used as an odd parity checker, the number of input bits should be
odd, but if an error occurs the sum odd output goes low and sum even output goes high.

Make the connections according to the design and verify the truth table.
Parity Generator with even parity bit:
Parity Checker with even parity bit:
Parity Checker with even parity bit using XOR gates:

N/A
N/A
3-bit Parity generater and 4-bit parity checker using even parity is implemented
using basic gates. And truth table is verified.
Able to implement parity generator and parity checker using basic gates.
Error detection and correction.
15. REMARKS::
2. TITLE: MASTER-SLAVE JK FLIP-FLOP
To learn about various applications of flip flops.
To learn and understand the working of J-K Master Slave Flip flop.
To develop Verilog/VHDL code for positive edge triggered D Flip-Flop using
behavioral modeling in Xlinx simulator.
4. AIM:
To study the truth table of J-K Master Slave flip flop and verify the same.
To develop Verilog/VHDL code for positive edge triggered D Flip-Flop and simulate
its working.
IC 7410
2
IC 7400
2
A flip-flop is a circuit that can maintain a binary state until directed by an input signal
to switch states. JK flip-flop is the most generally used flip-flop, which is edge
triggered and has got two data inputs J & K, and a clock input.
Normal data inputs to a flip-flop are referred to as synchronous inputs, because
they effect the output in steps synchronous with the clock signal.
Preset and Clear are asynchronous inputs, because they can set / reset the flip-flop
regardless of the status of clock. When Preset is activated, the flip-flop will be set
and when Clear is activated, the flip-flop will be reset. Preset and Clear find use
when multiple flip-flops are ganged together to perform a function.
In Master-Slave JK flip-flop, two flip-flops are arranged such that, when the clock
pulse enables the first (the Master) latch, it disables the second (the Slave) latch.
When the clock changes the state again (on its falling edge), the output of the
Master latch is transferred to the Slave latch.
The output of MS JK flip-flop is: Qnext = JQ + KQ
NOTE: A group of flip-flops sensitive to pulse duration is a latch. E.g.: 7475, a 4-bit latch.
A group of flip-flops sensitive to pulse transition is a register. E.g.: 74175, a 4-bit register.

Flip-flop is a sequential circuit used as memory element in other sequential circuits
as it is capable of storing a single bit of information. Every flip-flop has two
complementary outputs (Q and Q). Numbers of inputs to a JK flip-flop is 2 and are
usually designated as J and K. The circuit does not respond to the change in the
inputs unless an additional input called the clock input is applied.
NAND gates of both the 3-input and 2-input ICs are connected as shown below. It is
ensured that the Vcc and GNDs of both the ICs are connected to +5V dc power source and
Ground points respectively in the trainer. Outputs Q and Q are connected to the LEDs.
Inputs J and K are connected to the switches and the CP input is connected to
the monopulser slot in the trainer.
Initially J=0 and K = 0. Observe the Q. If it is 0, apply the clock pulse. Otherwise
make clear LOW (to make Q=0) and again HIGH (for normal operation) and then
apply the clock pulse. Observe the output listed in the column captioned Q(t+1).
If Q=1 is to be established, make preset LOW (to make Q=1) and again HIGH
(for normal operation).
Likewise obtain all the input combinations according the sequence in the table
and verify corresponding outputs.
Pin Diagram:
IC 7400(2-input NAND Gate)
IC 7410 (3-input NAND)
Circuit Diagram:
b) Simulation : Entity dff isPort(d,clk:in std_logic;

Q:inout std_logic;
Qb:out std_logic);
End dff;
Architecture behavioral of dff is
Begin
process(clk)
Begin
If rising_edge(clk) then
Q<=d;
Endif;
End process;
Qb<=not Q;
End behavioral;

a)
10. FORMULA / CALCULATIONS: N/A


The J-K Master / Slave Flip Flop is designed using NAND gates and its truth table
is verified.
The master slave flip flop is used as a solution to the race around problem in flip flops.
Data Storage
Data Transfer
Counter, Registers
Frequency Division.
15. REMARKS::
2. TITLE: SYNCHRONOUS UP-COUNTER
To learn about synchronous Counter and its application.
To learn the design and the working of synchronous counter.
To develop Verilog/VHDL code for mod-8 up counter using behavioral modeling in
Xilinx simulator.
4. AIM:
To Design and implement mod n (n<8) synchronous up-counter using J-K Flip Flop.
To develop Verilog/VHDL code for mod-8 up counter and simulate its working.
IC 7476
2
IC 7408
1
Patch Cords & IC Trainer Kit,
A Counter is a sequential circuit that goes through a prescribed sequence of states
up on application of input pulse. Counter are in two categories
Ripple Counter (Asynchronous Counter) consists of a series connection of
complementing flip-flops (T / JK type), with the output of each flip-flop connected
to the clock pulse input of the next higher order flip-flop. The flip-flop holding the
LSB receives the clock pulses.
Synchronous Counter the input pulses / clock pulses are applied to all clock
pulse inputs of all the flip-flops simultaneously.
The ripple counter requires a finite amount of time for each flip flop to change state.
This problem can be solved by using a synchronous parallel counter where every
flip flop is triggered in synchronism with the clock, and all the output which are
scheduled to change do so simultaneously.
The counter progresses counting upwards in a natural binary sequence from count 000 to
count 100 advancing count with every negative clock transition and get back to 000 after
this cycle.
The counter with n flip-flops has maximum mod number 2n. For example, 3-bit
binary counter is a mod 8 counter. This basic counter can be modified to produce
MOD numbers less than 2n by allowing the counter to skip states those are not
normally part of counting sequence.
MOD-5 synchronous counter is designed below using JK flip-flops and the circuit is
implemented as shown in the circuit diagram. A timing diagram is also constructed below.
Number of Flip-flops required = 3 as 3 is the minimum number for which 5<8. Let
the inputs of the three Flip-flops be JA, KA JB, KB, JC, KC. Let the normal outputs
be QA, QB, QC and the complementary outputs be QA, QB, QC.
Preset and Clear are the active low direct inputs (asynchronous inputs) to set or
reset the counter (means to set or reset all the flip-flops contained in the counter)
before to the application of the clock pulse to obtain the next state of the counter.
The Characteristic table is useful for analysis and defining operation of flip-flops.
The characteristic table of JK flip-flop is given below.
But during design, we normally know the transition from the present state to the
next state, called Transition table. The transition table is derived using the truth
table. Truth table is constructed using the given counter.
Here, given counter is mod-5. i.e., the given sequence is: 0, 1, 2, 3, 4, 0, . . .
First draw the State Diagram:
Then construct the expected Truth table:
From the truth table, construct Transition table.
Expected Truth table
Transition table of Mod-5 Counter
Now, construct the

Excitation table of
JK flip-flop using the
State
diagram
/
Characteristic table
of JK flip flop. A
table that lists the
required inputs for a
given change of
state
is
called
Excitation table.
Now by using the

excitation table and
the transition table,
evaluate the flip-flop
inputs as shown
below.
Go
for
K-Map
simplification,
and
after
K-Map
simplification,
expressions for the
flip-flop inputs are as
shown below:
Having obtained the combinational expressions for the flip-flop inputs to ensure the
desired next state transitions at the corresponding outputs, the following circuit
diagram is rigged up.
Two 7476 JK Flip-flop ICs are required as one IC contains only two JK flip-flops. Vcc and
GND of both the ICs are connected. Outputs QA(LSB), QB, and QC(MSB) are connected
to LEDs. Preset and Clear are the direct inputs connected to the switches. All the flip-flops
driven by the same clock pulse, establishes the concept of synchronous counter. Clock
input may be supplied with monopulser or continuous clock generator.

Pin Diagram:
IC 7476 (J K Flip Flop)
Circuit Diagram:
IC 7408(2-input AND Gate)
b)Entity mod-8 is
Port(rst,clk,en:in std_logic);
Q:inout std_logic_vector(3 downto 0));
End mod-8;
Architecture behavioral of mod-8 is
Begin
Process(clk,rst) is
Begin
If rst=1 then q<=0000
Else if rising_edge(clk) then
If en=1 then
Q<=q+1;
Endif;
Endif;
If q=1000 then q<=0000;endif;endif;endprocess; end behavioral;

N/A
N/A
a)
b)

The mod-n synchronous counter is successfully implemented by using the JK Flip Flop.
Using the JK Flipflops a mod-n synchronous counter can be implemented thereby
allowing to generate a count sequence that is desired.
Data Storage
Data Transfer
Frequency Division.
15. REMARKS:
2. TITLE: ASYNCHRONOUS COUNTER
To learn about asynchronous counter and decade counter.
To understand the working of mod-n asynchronous counter using decade counter.
4. AIM:
Design and implement an asynchronous counter using decade counter IC to count
up from 0 to n (n<=9) and demonstrate on 7-segment display (using IC-7447).
IC 7490
1
IC 7411
1
IC 7447
1
A Counter is a sequential circuit that goes through a prescribed sequence of states
up on application of input pulse. Counter are in two categories
Ripple Counter (Asynchronous Counter) consists of a series connection of
complementing flip-flops (T / JK type), with the output of each flip-flop connected
to the clock pulse input of the next higher order flip-flop. The flip-flop holding the
LSB receives the clock pulses.
Synchronous Counter the input pulses / clock pulses are applied to all clock
pulse inputs of all the flip-flops simultaneously.
A counter is a device which stores (and sometimes displays) the number of times a
particular event or process has occurred, often in relationship to a clock signal. In
asynchronous counter a clock signal is provided for one flip-flop and its output is
provided as clock source for next flip-flop. The output of asynchronous counter is
not synchronized with clock signal.
A decade counter follows a sequence of 10 states and returns to zero after the count of
nine. Such a counter must have at least 4 flip flops to represent each decimal digit
since a decimal digit is represented by a binary code with at least 4 bits.

Explained along with the circuit diagram.
Pin Diagram:
IC 7490 (Decade counter)
Internal Diagram of 7490
IC 7447
Function Table of 7490
IC 7411 (3-input AND Gate)
Circuit Diagram:
Function Table:

Given along with the circuit diagram.
N/A
N/A
An asynchronous counter using a decade counter is designed
and the truth table is verified for the same.
By using a decade counter we can obtain an appropriate
decimal number
Binary Coded Decimal.
Finite State Machines.
15. REMARKS:
Study Experiment
12. To study 4-bit ALU using IC-74181.
The 74181 is a 7400 series medium-scale integration (MSI) TTL

integrated circuit, containing the equivalent of 75 logic gates [2] and most
commonly packaged as a 24-pin DIP. The 4-bit wide ALU can perform
all the traditional add / subtract / decrement operations with or without
carry, as well as AND / NAND, OR / NOR, XOR, and shift. Many
variations of these basic functions are available, for a total of 16
arithmetic and 16 logical operations on two four-bit words. Multiply and
divide functions are not provided but can be performed in multiple steps
using the shift and add or subtract functions. Shift is not an explicit
function but can be derived from several available functions including
(A+B) plus A, A plus AB.
Figure 1: Pin out Diagram of TC 74181
As seen in figure-2, the ALU has two 4-bit input lines A3-A0, B3-B0, a
4-bit function select lines S3-S0, one mode select line M that is used to
select ALU for either arithmetic or the logical function. It has four output
lines f3-f0, carry-in Cn is used in cascade mode.
Figure 2: The combinational logic circuitry of the 74181

integrated circuit
Figure 3: Function Table of IC 74181
VIVA QUESTIONS
1. What is Schmitt Trigger?

2. Explain the working of Schmitt trigger.
3. Define the term U.T.P and L.T.P?
4. Define Dead band or Dead zone.
5. Mention the applications of Schmitt Trigger.
6. Why this circuit is named as Relaxation oscillator?
7. What is an oscillator?
8. What are the different types of oscillators?
9. Explain the working of the relaxation oscillator.
10. Define a multivibrator?
11. What are the different types of Multivibrators?
12. Explain the working of astable multivibrator.
13. Define duty cycle?
14. What is the necessity of the diode in the circuit shown of a astable
multivibrator?
15. Explain the operation of a 555 timer IC.
16. What is a multiplexer?
17. What is the advantage of using VEM Technique?
18. What is the importance of Enable Pin?
19. Differentiate between a MUX and a Decoder?
20. What is the importance of select line in a MUX?
21. How to decide the number of Select lines for any MUX?
22. Differentiate between a latch and a Flip-Flop.
23. What are the different types of flip-flops? Explain by showing the truth
table?
24. What is Race-around problem? How can you rectify it?
25. Differentiate between Sequential and Combinational circuits.
26. Explain the working of a MS-JK flip-flop.
27. What are the difference between +ve edge triggered and ve edge
triggered circuit?
28. What is a counter?
29. Differentiate between synchronous and asynchronous counters.
30. What types of flip-flops can be used to implement the memory

elements of a counter?
31. Explain the use of PRESET and CLEAR pins in flip-flop.
32. What are registers?
33. What are shift registers?
34. What are the different types of shift registers?
35. Differentiate between SIOP, PISO, PIPO and SISO.
36. Why it is called as decade counter?
37. Explain the pins of 7490 IC.
38. Explain about arithmetic basic building blocks.
39. Define parity generator and parity checker.
40. Define magnitude comparator.

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1.

sets of UTP and LTP values.

DC Regulated Power Supply

Case 2: UTP =_____V, LTP = ______V

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE: a)

We know UTP = +BVsat , ie 1V= (R 2 /(R1 + R2))12V

The above design will set an LTP =

12. RESULTS & CONCLUSIONS:

Regulated Power Supply

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION

Case 2: Circuit with all resistors doubled

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

Case 2: With all resistors doubled:

Let us choose R1= 1.8K.

The output waveform swings between +Vsat and

12. RESULTS & CONCLUSIONS:

Frequency of output waveform =1/T =

13. LEARNING OUTCOMES :

14. APPLICATION AREAS:

Switching power supplies.

DC Regulated Power Supply

= 1/3 Vcc, as per theory)

OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

6. High level of output, VH =__________Volts. (Low level is zero volts).

11. GRAPHS / OUTPUTS:

12. RESULTS & CONCLUSIONS:

To realize the full adder circuits using basic gates.

IC 7404 PIN DIAGRAM

IC 7408 PIN DIAGRAM

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

7. PROCEDURE / PROGRAMME / ACTIVITY:

0 in appropriate cell of MEV Map.

Assume that the following 4-variable Boolean function is to be implemented using

Inputs ABCD are varied by making the corresponding switches ON or OFF,

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

10. FORMULA / CALCULATIONS:

12. RESULTS & CONCLUSIONS:

Applications of Gray Code:

IC 7486 Pin Diagram

Binary to Gray code converter

Gray to binary code converter

= G3G2 G1+ G3G2G1+ G3G2G1+G3

10. FORMULA / CALCULATIONS:

7. PROCEDURE / PROGRAMME / ACTIVITY:

Parity Checker with even parity bit:

Parity Checker with even parity bit using XOR gates:

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

10. FORMULA / CALCULATIONS:

The output of MS JK flip-flop is: Qnext = JQ + KQ

7. PROCEDURE / PROGRAMME / ACTIVITY:

b) Simulation : Entity dff isPort(d,clk:in std_logic;

9. OBSERVATION TABLE / LOOKUP TABLE / TRUTH TABLE:

10. FORMULA / CALCULATIONS: N/A

12. RESULTS & CONCLUSIONS:

First draw the State Diagram:

Then construct the expected Truth table:

From the truth table, construct Transition table.

Expected Truth table

Transition table of Mod-5 Counter

Now, construct the

Now by using the

8. BLOCK / CIRCUIT / MODEL DIAGRAM / REACTION EQUATION:

IC 7476 (J K Flip Flop)

Case 2: UTP =_V, LTP = __V