EECS 579 Project

Compare ATPG Programs

Synopsys TetraMAX vs.
Mentor Graphics Tessent
Guanhao Qiao

Yunyi Zhang

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Motivation
General Introduction
Synthesis and DFT Design Flow
Scan Chain Insertion

Test Results Comparison

Summary and Future Works

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Motivation
high performance and optimal ATPG program
becomes more important for large ICs with high
testing cost
Better ATPG can improve the test efficiency and
gain more accurate testing results

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General Introduction:

Synopsys Tools-- TetraMAX

TetraMAX is an automatic test pattern generation
(ATPG) tool that generates test patterns with maximum
test coverage and minimum test vectors for different
types of design. It is capable with designs of up to
millions of gates.

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General Introduction:

Mentor Graphics Tools-- Tessent

Mentor Graphics is used during a typical ASIC top-down
design flow using a structured DFT strategy
Products: FastScan, TestKompress, Diagnosis, IJTAG,
DesignEditor and Scan (formerly DFTAdvisor)
Tessent Scan (formerly DFTAdvisor) is used to insert
scan chain (basically replacing FF with scan FF)
Fastscan is used to do ATPG and fault simulation.

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Synthesis and DFT Design Flow

Cell

Libraries

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Basic ATPG Design Flow [1]

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Scan Chain Insertion [1]

Replace DFF by mux-DFF.

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Scan_in
Combinational Logic

Combinational Logic

Combinational Logic

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Scan Chain Operation

Scan_out

PO

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Benchmark Circuits

ISCAS 85
ISCAS 89
ITC 99 / ISCAS 99
74X-series

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Sequential Test for Stuck-At-Fault:

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ISCAS 89: Total Faults and Total Patterns

Total Faults
140000
120000
100000
80000

TetraMAX

60000

FastScan

40000
20000
0
s298

s5378

s38417

s38584

Total Patterns
1400
1200
1000
800
600
400
200
0

TetraMAX
FastScan

s298

s5378

s38417

s38584

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ISCAS 89: Test and Fault Coverage

Test Coverage
200.00%
100.00%
0.00%

TetraMAX
FastScan
s298

s5378

s38417

s38584

Fault Coverage
102.00%
100.00%
98.00%
96.00%
94.00%
92.00%

TetraMAX
FastScan
s298

s5378

s38417

s38584

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ISCAS 89: Process CPU time

Process CPU time (sec)
12
10

8
TetraMAX
FastScan

6
4
2
0
s298

s5378 s38417 s38584

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Combinational Test for Stuck-At-Fault:

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Total Faults and Total Patterns

Total Faults
20000
15000
TetraMAX

10000

FastScan

5000
0
c5315

c6288

74182

74283

Total Patterns
160

140
120
100
80

TetraMAX

60

FastScan

40
20
0
c5315

c6288

74182

74283

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Test and Fault Coverage

Test Coverage
100.50%
100.00%
99.50%
99.00%

TetraMAX
FastScan
c5315

c6288

74182

74283

Fault Coverage
100.50%
100.00%

TetraMAX
FastScan

99.50%
99.00%
c5315

c6288

74182

74283

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Process CPU time

Process CPU time (sec)
14
12
10
8

TetraMAX
FastScan

6
4
2
0
c5315

c6288

74182

74283

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Transition Fault Model (c6288):

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Transition Fault Model Comparison (c6288):

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IDDQ Fault Model: (c6288.v)

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IDDQ Fault Model Comparison: (c6288.v)

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Transition/IDDQ Fault Model Comparison:

FastScan has more total faults,
Higher Test coverage, but lower Fault coverage.
With less test patterns.

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SCOAP: 74182

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SCOAP: 74182

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Fault Simulation Results: 74182

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Conclusion
ATPG

TetraMAX

FastScan

Com. Seq. Com. Seq.

Test Coverage

Fault Coverage

CPU times

Total Faults

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ATPG

TetraMAX

FastScan

Synthesis and DFT

Design Parameter

Fault Models

Fault Simulation

SCOAP

Documentation

GUI Interface

Ease to Use

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Future Works
SimVision [3] can run NC-Verilog and test the
patterns out against the synthesized design.
SimVision can also generate simvision waveforms
for those test patterns.
Explore path delay faults, and bridging faults.

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Questions?

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Reference
[1]
TetraMAX ATPG User Guide, Vers. H-2013.03SP1, Synopsys Inc, Apr 2013.
[2]
Tessent Shell User's Manual, Vers. 2013.3,
Mentor Graphics Corporation, Sep 2013.
[3]
SimVision Command Language Reference, Vers.
8.2, Cadence Design Systems Inc, Jun 2009.

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Acknowledgement

Dr. John Hayes,

Joel VanLaven (DCO),

Te-Hsuan, Chen

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Future Works
SimVision [3] can run NC-Verilog and test the
patterns out against the synthesized design.
This idea is to use these patterns against a
fabricated chip, and see if there are any defects.
SimVision can also generate simvision waveforms
for those test patterns. If there is a defect/error, the
designer will found it on the waveforms.
Explore path delay faults, and bridging faults.