A microprocessor needs to be interfaced to memories for program and data storage and I/O devices for the purpose of communicating with the environment. 2. What are the types of incompatibilities which arise between two devices when interfaced?
3. What is meant by address space and address space partitioning?
4. What are the different types of address spaces?
The two types of address spaces are the memory and the Input/Output address space. 5. How will you partition an address space of 64K for EPROM, RAM and I/O devices?
6. What is Memory mapped I/O and I/O mapped I/O?
7. What are the different means of decoding an address?
8. What do you mean by bus contention? How will you resolve it? If the architecture of the microprocessor has only a single line control and the data output lines are tied together and accesses the same data bus, then during data transfer, bus contention occurs. This problem is resolved by using a two line control architecture ie chip enable(CE) and output enable(OE) lines.
9. What are the different access times required for an EPROM?
The different access times required for an EPROM are tacc (Access time), tce(time delay for chip enable) toe (time delay for output enable) and tdf ( time for output disable to output float). 10.What is the instruction used to transfer data from MP to an I/O register using I/O mapped I/O?
The OUT instruction is used to transfer data from Microprocessor to the
register in the I/O device. The IN instruction is used to transfer data from I/O device to Microprocessor. 11.What is meant by handshaking?
12.What is serial data transfer and what are its advantages?
13.What is the broad classification of interfacing devices?
Interfacing devices are classified into two different types: 1. General purpose peripherals These are devices that perform a specific task but may be used for interfacing a variety of I/O devices to the p. 2. Special purpose peripherals - These are devices that may be used for interfacing a p to a specific type of I/O device. Eg: Programmable Keyboard and display interface. 14.What is software and hardware polling? The different ways by which the ILS ( Interrupt level subroutine) can determine the interrupting device is known as device polling.
15.How will the processor handle multiple interrupts on a single level?
16.What do you mean by TRAP? What is its significance?
The primary requirement for the implementation of multiple interrupt levels is that the p must have several interrupt inputs. One of the interrupt inputs in 8085 is called the TRAP. It has the highest priority and is normally used to indicate some emergency condition. 17.What is an ILS ( Interrupt level service) subroutine? Branching to the interrupt processing routine after executing the current instruction is known as Interrupt level subroutine. The purpose of ILS is to determine the device that has interrupted. 18.What do you mean by cycle stealing?
19.What is Burst mode data transfer in Microprocessors?
20.What do you mean by masking? What is its significance?
Masking in the 8085 is when certain interrupts are disabled, or masked, by instruction execution during multiple interrupt request. The significance is to prevent the occurrence of all interrupt requests at a time. TRAP is not maskable. INTR, RST7.5, RST6.5, and RST5.5 are maskable as a group with the EI and DI instructions. 21.What are the functions of RIM and SIM instructions? The interrupt Mask may be read using a RIM (Read Interrupt Mask) instruction in 8085. The SIM instruction is used to set or reset interrupt masks . It sets the masks to the bit values of the corresponding bits in the Accumulator. 22. What do you understand by Priority of interrupt levels? What is meant by priority of devices? Priority of interrupt levels is the priority assigned to the interrupt pins INTR, RST7.5, RST6.5, and RST5.5 and TRAP. The highest priority is given to TRAP, then RST7.5, RST6.5, and RST5.5. Priority of the devices means when multiple DMA requests are made by the devices, the I/O device which has the highest priority is granted the request and it makes use of the buses. This priority is assigned by the manufacturer. 23. Why should a DMA request have higher priority than other interrupts? On what basis should the priorities be assigned to the devices on the DMA channel?
When a DMA request is made, the HOLD goes high indicating that the MP will complete its execution of the current instruction and then process any other interrupt. This is because the HOLD is given the highest priority. The I/O devices are assigned priority based on its speed of operation. 24. Why the number of out ports in the peripheral-mapped I/O is restricted to 256 ports? The number of output ports in the peripheral I/O is restricted to 256 ports because the operand of the OUT instruction is 8-bits; it can have only 256 combinations. 25. If an input and output port can have the same 8-bit address how does the 8085 differentiate between the ports? The 8085 differentiates between the input and output ports of the same address by the control signal. The input port requires the RD and the output port requires the WR signal.
