Unit -1

1. Compare pmos and nmos

2. Compare enhancement and depletion mode
3. What is accumulation mode
4. What is depletion mode
5. What is inversion mode
6. Write the equation of threshold voltage
7. What is Noise margin and write the types
8. What is demarcation line
9. What is lambda rule
10. What is micron rule
Unit -2
1. Define Elmore delay model
2. Write the properties of Elmore delay model
3. Define absolute delay
4. Define linear (effort and electrical delay) model
5. What is mean by Power dissipation
6. Method to reduce dynamic and static power dissipation
7. Properties of estimate of resistance
8. Cross talk and their properties
9. Define victim and aggressor
10. Define reliability
Unit -3
1. Write the Classification of cmos circuit
2. Write the properties of static cmos logic
3. What is Bubble pushing
4. What is Pseudo nmos logic
5. Advantage and disadvantage of pseudo logic
6. What is Dynamic logic
7. Advantage and disadvantages of dynamic logic
8. Domino logic
9. Write the Properties of domino logic
10. What is Clock skew
16 mark
1. Static logic
2. Problem based static(AOI OR OAI)
3. I) CVSL
ii) Dual rail domino logic
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ii) CPL
iv) keeper circuit
v) CMOS TG and CPL
4. I) latch and flip flop
ii) Resettable latch and flip flop
iv)enable latch and flip flop
v) pulsed latchs
vi) Differential and TSPC latches
5. Explain concept of synchronizers
6. Explain the concept of arbiter

Unit -4
2 mark
1. Need for testing
2. Different level of testing
3. Types of testing
4. Characterization testing
5. Production testing
6. Functional testing
7. Manufacturing testing
8. Defect, error and fault
9. S A 0
10. S A 1
11. Short circuit fault
12. Open circuit fault
13. Controllability and observability
14. ATPG
15. D algorithm
16. Statistical fault analysis
17. DFT
18. Types of DFT
19. AD HOC tesing
20. Scan design rules in testing DFT method
21. LSSD
22. Advantage in LSSD
23. Advantages of built in self test
24. BILBO
25. Pseudo random testing
26. TAP
27. Boundary scan
28. Regression testing
29. Types of fault simulation
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16 mark
1.
2.
3.
4.
5.

Types of testing
Scan design techniques
Built in self test
Boundary scan or system level scan test
Explain manufacturing test principles

Unit- 5
2 marks
1. Dataflow
2. Behavioral
3. Gate level
4. What is verilog HDL
5. Design methodology
6. VLSI design flow
7. What is test bench
8. Types of gate delay
9. What is continuous assignment statement
10. Types of operators
16 mark
1.
2.
3.
4.

Operators
Blocking and non blocking statement
Timing control and delay in verilog
Explain procedural constriction, initial statement and always statement.

B.E/B.Tech Degree Examination,November/December 2009.

Seventh Semester
Electronics and Communication Engineering
EC 1401-VLSI DESIGN
(Common to B.E.(Part-Time) Sixth Semester Regulation 2005)
(Regulation 2004)

Part A-(10*2=20 marks)

1.What are the different MOS layers?
2.What are the two types of layout design rules?
3.Define rise time and fall time.
4.What is a pull down device?
5.What are the difference between task and function?
6.What is the difference between === and == ?
7.What is CBIC ?
8.Draw an assert high switch condition if input = 0 and input =1.
9.What do you mean by DFT?
10.Draw the boundary scan input logic diagram.
Part B - (5*16=80 marks)
11.a) Discuss the steps involved in IC fabrication process.(16)
Or
b) Describe n-well process in detail.(16)

12.a)i)Explain the DC characteristics of CMOS inverter with neat sketch.(8)

ii)Explain channel length modulation and body effect.(8)
Or
b)i)Explain the different regions of operation in a MOS transistor.(10)
ii)Write a note on MOS models.(6)

13.a)Explain in detail any five operators used in HDL .(16)

Or
b)i)Write the verilog code for 4 bit ripple carry full adder.(10)
ii)Give the structural description for priority encoder using verilog.(6)

14.a)Explain in detail the sequence of steps to design an ASIC.(16)

Or
b)Describe in detail the chip with programmable logic structures.(16)
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15.a)Explain in detail Scan Based Test Techniques.(16)

Or
b)Discuss the three main design strategies for testability.(16)