Beruflich Dokumente
Kultur Dokumente
3672
Storage Control Unit
Theory of Operations Manual
3672.21-00
3672.21-0001
5,
j, D 4065
PREFACE
This manual provides the Memorex Field Engineer (FE) with detailed operating theory about the
3672 Storage Control Unit, used in 3672-based disc storage subsystems with the 3673 Disc Drive
Controller and 3670/3675 Disc Drive Modules. It is intended for use by the FE during training as
essential course material, and during servicing as an aid in identifying equipment difficulties. The
manual consists of six sections:
Section 1 -
Describes briefly the overall functions performed by the 3672 Storage Control
Unit and the 3672-based subsystem.
Section 2 -
Section 3 -
Section 4 -
Section 5 -
Describes operation of the 650 Flexible Disc File, used to store operating and
diagnostic microprograms executed by the 3672.
Section 6 -
Maximum benefit of this manual is achieved when used with th,e 3672 Storage Control Unit Logic
Diagram Manual PIN 308312. The alphanumeric numbers which appear in each functional block
of the block diagrams in Section 6 refer to corresponding pages of logic in the Logic Diagram
Manual.
Other manuals that support the 3672 Storage Control Unit which may be of use to the FE are listed
below:
3672.22-00 - 3672 Storage Control Unit Installation Manual
3672.20-00 -
3672.50-01 - 3672 Storage Control Unit Microdiagnostics Reference Manual (two volumes)
TABLE OF CONTENTS
Section
I
3672.21 -0001-10175
Page
GENERAL DESCRIPTION
1-1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.7.1
1.7.2
1.7.3
1.8
1-1
1-1
1-1
1-1
1-3
1-3
1-3
1-3
1-4
1-4
1-6
SCOPE
SUBSYSTEM CHARACTERISTICS
STANDARD FEATURES
OPTIONAL FEATURES
COMPATIBILTY
SPECIFICATIONS SUMMARY
UNIT CHARACTERISTICS
3672 Storage Control Unit
3673 Disc Drive Controller
3670 (3675) Disc Drive Module
DATA INTERFACE REQUIREMENTS
COMMANDS
2-1
2.1
2.2
2.3
2.3.1
2.3.2
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-1
2-3
2-3
2-4
2-4
2-4
2-4
2-4
2-4
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-5
2-7
2-7
2.3.3
2.3.4
2.3.5
2.3.5.1
2.3.5.2
2.3.5.3
2.3.5.4
2.3.5.5
2.3.6
2.4
2.4.1
2.4.1.1
2.4.1.2
2.4.1.3
2.4.1.4
2.4.1.5
2.4.2
GENERAL
COMMAND SUMMARY
INSTRUCTION AND WORD FORMAT
Introduction
1/0 Instructions
START 1/0
START 1/0 FAST RELEASE
TEST I/O
HALT 1/0
HALT DEVICE
Channel Address Word
Channel Command Word
Channel Status Word
Status Presentation
Initial Status
Ending Status
Pending Status
Contingent Connection
Program Status Word
CONTROL COMMANDS
Operational Block Diagram
System
System Interface
Storage Control Unit
Drive Controller
Disc Drive Module
Command Descriptions
NO-OP
SEEK
Section
Page
SEEK CYLINDER
SEEK HEAD
SPACE COUNT
RECALIBRATE
RESTORE
SET FILE MASK
DIAGNOSTIC LOAD
DIAGNOSTIC WRITE'
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.6.1
2.5.6.2
2.5.6.3
2.5.6.4
2.5.6.5
2.5.6.6
2.6
2.6.1
2.6.1.1
2.6.1.2
2.6.1.3
2.6.1.4
2.6.1.5
2.6.1.6
2.6.1.7
2.6.1.8
2.6.2
SENSE COMMANDS
Sense Byte Information
Sense Control Block
Sense Byte Bit Definitions
Assembling Sense Bytes 8 through 23
Command Descriptions
SENSE 1/0
TEST I/O
READ AND RESET BUFFERED LOG
READ DIAGNOSTIC STATUS 1
DEVICE RESERVE
DEVICE RELEASE
Transfer In-Line Diagnostics to SCU
Introduction
System
Channel
Channel Interface
Storage Control Unit (SCU)
Control Storage
READ COMMANDS
Operation Block Diagram
System
Channel
Channel Interface
Microprocessor
Controller
Read Circuit
Read/Write Head
Pack
Command Descriptions
READ DATA
READ KEY AND DA1A
READ COUNT, KEY, AND DATA
READ RECORD ZERO
READ COUNT
READ HOME ADDRESS
READ IPL
READ SECTOR
2-8
2-8
2-9
2-10
2-11
2-12
2-14
2-15
2-16
2-16
2-16
2-16
2-16
2-16
2-21
2-22
2-23
2-24
2-25
2-25
2-26
2-26
2-26
2-26
2-26
2-26
2-26
2-27
2-27
2-27
2-27
2-27
2-27
2-27
2-27
2-27
2-27
2-27
2-28
2-28
2-29
2-32
2-32
2-33
2-36
2-36
Page
Section
2.6.2
2.6.4
2.6.4.1
2.6.4.2
2.6.4.3
2.6.4.4
2.6.4.5
2.6.4.6
2.6.4.7
2.6.4.8
2.7
2.7.1
2.7.1.1
2.7.1.2
2.7.1.3
2.7.1.4
2.7.1.5
2.7.1.6
2.7.1.7
2.7.1.8
2.7.2
~.7.3
2.8
2.9
2.10
2.11
2.111
2.11.1.1
2.11.1.2
2.11.1.3
2.11.1.4
2.11.1.5
2.11.2
2.11.3
2.11.4
2.11.5
2.11.6
2-38
2-38
2-38
2-38
2-38
2-38
2-38
2-38
2-38
2-38
2-42
2-42
2-42
2-42
2-42
2-42
2-43
2-42
2-42
2-42
2-44
2-43
2-43
2-46
2-47
2-48
2-49
2-50
2-51
2-54
2-54
2-56
2-56
2-57
2-59
2-59
2-60
2-62
2-63
2-64
2-74
2-64
2-64
2-64
2-66
2-64
2-64
2-64
2-64
2-64
2-64
Section
Page
2.11.7
2.11.8
2.12
2.12.1
2.12.2
2.12.3
2.12.4
2.13
2.14
2.14.1
2.14.2
2.14.3
2.15
GENERAL
CHANNEL INTERFACE LINES DESCRIPTION
Inbound Lines
Outbound Lines
INTERFACE SEQUENCES
Overall Descriptions
Initial Selection Sequence
Data Transmission Sequence
Ending Sequence
SCU Busy Response
SCU-Initiated Sequence
Immediate Command Sequence
Initial Selection Sequence
Simplified Sequence
Detailed Sequence
Ending Sequence
Simplified Sequence
Detailed Sequence
Polling Sequence and Status Presentation
Simplified Sequence
Detailed Sequence
CHANNEL OPERATION
Selector Channel Operation
Block Multiplexer Operation
Introduction
Rotational Position Sensing
Disconnected Command Chaining
Multiplexer Channel Operation
SEQUENCE CONTROLS
Command Chaining
Data Chaining
Branching in Channel Programs
Unit Selection and Device Addressing
Stack Status
2-64
2-64
2-77
2-77
2-77
2-77
2-78
2-79
2-80
2-80
2-80
2-80
2-81
3-1
3-1
3-2
3-2
3-2
3-4
3-4
3-4
3-4
3-4
3-4
3-4
3-4
3-4
3-4
3-6
3-6
3-6
3-7
3-7
3-7
3-7
3-8
3-8
3-8
3-8
3-8
3-8
3-8
3-13
3-13
3-13
3-13
3-13
3-13
vi
Section
Page
3.5.6
3.57
3.5.8
3.5.9
3.5.10
3.5.11
3.5.12
3.5.13
3.5.14
3.5.15
3.5.16
3.5.17
3.6
3.6.1
3.6.2
3.6.2.1
3.6.2.2
3.6.2.3
3.6.2.4
3.6.2.5
3.6.2.6
3.6.2.7
3.7
3.7.1
3.7.2
3.7.3
3.8
3.8.1
3.8.2
3.9
3.9.1
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.11.6
3.12
3.12.1
3.12.2
3.12.2.1
3.12.2.2
3.12.2.3
3.12.2.4
3.12.2.5
3.12.3
3.12.3.1
3672.21-0001-10175
Suppress Status
Disconnect In
Interface Disconnect
Selective Reset
Command Retry
Proceed
Stop (or Truncation)
Suppress Data
Data Acceptance
Data Ready
Status Acceptance
System Reset
STATUS CONDITIONS
Overview
Description of Status Conditions
Status Modifier
Control Unit End
Busy
Channel End
Device End
Unit Check
Unit Exception
SENSE CONDITIONS
Overview
Conditions Indicated by Bits of Sense Byte 0
Conditions Indicated by Bits of Sense Bytes 1 through 23
READ DATA
Description
Flow Diagram
WRITE DATA TRANSFER
Description
Flow Diagram
SCU-INITIATED CHECK 1 ERROR CONTROL
SEQUENCE (pOLLING). SIMPLIFIED
MULTICHANNEL SWITCH OPERATION
Channel Selection Switch
Instantaneous Connection
Long Connection
Device Status
Addressing
Resets
2860 SELECTOR CHANNEL ATTACHMENT FEATURE
Description
Functional Characteristics
General
Channel Commands
Disconnected Command Chaining
Error Recovery
Non-RPS Mode Operation
1/0 Programming
Channel Programs
3-13
3-13
3-13
3-13
3-14
3-14
3-14
3-14
3-14
3-14
3-14
3-14
3-15
3-15
3-15
3-15
3-15
3-15
3-15
3-15
3-16
3-16
3-17
3-17
3-17
3-17
3-18
3-18
3-19
3-23
3-23
3-24
3-29
3-30
3-30
3-30
3-30
3-30
3-30
3-30
3-32
3-32
3-32
3-32
3-33
3-34
3-34
3-35
3-35
3-35
Section
Page
I
4
3.12.3.2
3.12.3.3
MICROPROGRAM
4.1
4.1.1
4.1.2
4.1.3
4.1.3.1
4.1.3.2
4.1.3.3
4.1.3.4
4.1.4
4.1.5
4.2
4.2.1
4.2.2
4.2.3
5
MICROINSTRUCTION
General
Microinstruction Word Description
Microinstruction Format
Format 0 Microinstructions
Format 1 Microinstructions
Format 2 Microinstructions
Format 3 Microinstructions
Microinstruction Field Definitions
Field Translation
MICROPROGRAM
Microprogram Block Format
Example Microprogram
Microprogram Routine .organization
5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.3.2
5.4.3.2
5.4.4
5.4.4.1
5.4.4.2
5.4.4.3
5.4.5
5.4.5.1
5.4.5.2
5.4.5.3
5.5
5.5.1
5.5.2
5.5.3
GENERAL DESCRIPTION
SPECIFICATIONS
Machine Characteristics
Operating Capabilities
Power Requirements
SPECIAL PRECAUTIONS
Cartridge Loading
Disc Interchangeability
Physical Damage
Safety
PRINCIPLES OF OPERATION
General Operation
Functional Assemblies
Logic and Analog Functional Descriptions
Control and Status Logic
Read Logic
Functional Operation
Initialization Phase
Track Access Phase
Read Phase
Interface Signal Description
Control
Data
Power
CONTROL CIRCUITRY DESCRIPTION
Functional Description
Printed Circuit Board
Harness Assembly
3-35
3-35
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-1
4-5
4-5
4-5
4-5
5-1
5-1
5-2
5-2
5-2
5-2
5-3
5-3
5-3
5-3
5-3
5-4
5-4
5-5
5-6
5-6
5-6
5-6
5-6
5-6
5-7
5-7
5-8
5-9
5-9
5-10
5-10
5-10
5-10
vii
Section
Page
6.1
6.2
6.2.1
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.2.4
6.2.2.5
6.2.3
6.2.3.1
6.2.3.2
6.2.3.3
6.2.4
6.2.4.1
6.2.4.2
6.3
6.3.1
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.3
6.3.3.1
6.3.3.2
6.3.3.3
6.3.3.4
6.3.3.5
6.3.4
GENERAL DESCRIPTION
CHANNEL INTERFACE DESCRIPTION
General
Logic Description
Address Compare Logic
Select Logic
Priority Logic
Multiplexer IDemultiplexer Circuits
Registers
Data Transfer Organization
General
Read Operations
Write Operations
Channel Interface Branch Conditions
Channel Buffer Ready (CBR)
Queue Empty
MICROPROCESSOR DESCRIPTION
Microprocessor General Description
Microinstructions
Descriptions and Formats
Microinstruction Field Translation and Branching
Microinstruction Execution Example
Writable Control Storage
General
Reading From WCS
Writing Into WCS
Error Correction Code
WCS Expansion
Data Paths
6-1
6-2
6-2
6-2
6-2
6-2
6-2
6-2
6-2
6-2
6-5
6-5
6-5
6-5
6-6
6-6
6-6
6-7
6-7
6-7
6-7
6-7
6-8
6-8
6-8
6-8
6-9
6-9
6-12
6-12
Section
Page
6.3.4.1
6.3.4.2
6.3.4.3
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.3.5.4
6.3.5.5
6.3.6
6.3.6.1
6.3.6.2
6.3.6.3
6.3.7
6.4
6.4.1
6.4.2
6.4.2.1
6.4.2.2
6.4.3
6.5
6.5.1
6.5.2
6.6
6.6.1
6.6.2
6.6.3
6.6.4
Buses
Registers
Arithmetic Logic Unit
Buffer Storage
General
Description
Buffer Control Commands
Error Correction Code
Buffer Storage Allocation
Flexible Disc Interface
General
Functional Description
IPL Flow Chart
Microprocessor Timing
CONTROLLER INTERFACE
General
Interface Signals
SCU to Controller Signals
Controller to SCU Signals
Register Definitions
FE INTERFACE
General
Functional Description
CHECK-l ERRORS
Error Detection and Sequences
Machine Check (MCK) Register
Check-l Error Display
Reset of Check-l Error Conditions
GLOSSARY OF TERMS
6-12
6-14
6-16
6-16
6-16
6-16
6-18
6-18
6-19
6-19
6-19
6-19
6-23
6-23
6-30
6-30
6-30
6-31
6-31
6-31
6-33
6-33
6-33
6-34
6-34
6-34
6-34
6-34
G-l
viii
LIST OF ILLUSTRATIONS
Figure
1-1
1-2
1-3
2-1
2-1A
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-28
2-29
2-30
2-3.1
2-32
2-33
2-34
2-35
2-36
2-37
2-38
2-39
2-40
3672.21-0001-10 '75
Page
Figure
1-2
1-3
1-5
2-5
2-5A
2-7
2-7
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-21
2-22
2-23
2-24
2-25
2-26
2-27
2-30
2-34
2-37
2-39
2-40
2-41
2-42
2-44
2-47
2-48
2-49
2-50
2-51
2-53
2-55
2-41
2-42
2-43
2-44
2-45
2-58
2-60
2-62
2-63
2-65
2-66
2-68
I
I
2-46
2-47
2-48
2-49
2-50
2-51
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
6-1
6-2
6-3
Page
Command Retry, Alternate Track
Command Retry, Data and Command Overruns
Command Retry, Padding
Command Retry, Write Offset
Command Retry, Invalid Count Field Sync Detected and
Index Detected in Data Field
Read/Set Sector Operation
Track Sector Layout
Typical Track Field Layout
Multitrack Operation
Overflow Record Operation
Multichannel Operation Block Diagram
Serial Connection of SELECT IN/SELECT OUT
Selector Channel Operation. Data Transfer Sequences
Selector Channel Operation, Miscellaneous Sequences
Disc Track Sector Format
Disconnect Command Chaining Block Diagram and Examples
Block Multiplexer Channel Operation (1 of 2)
Read Data Transfer Block Diagram
Read Data Transfer Flow Diagram (1 of 3)
Write Data Transfer Block Diagram
Write Data Transfer Flow Diagram (1 of 4)
Check-l Error Controlling Sequence Flowchart and Logic Diagram
Multi-Channel Switching Logic
Set RPS Flow Diagram
Microinstruction Formats
Microinstruction Expansion
Microprogram Block Formats
Microprogram Format Example
Microprogram Routine Organization
Memorex 650 Flexible Disc File
Flexible Disc Cartridge
Cartridge Loading
Flexible Disc File/Microprocessor Interface
Flexible Disc File Functional Block Diagram
Head Loading Mechanical Assembly
Disc Cartridge and Disc Configuration
Initialization Sequence
Read Sequence
Read Data Waveforms
Flexible Disc File Interface Diagram
Control Circuitry Block Diagram
Flexible Disc File PCB
3672 SCU Block Diagram
Channel Interface Block Diagram
Read Data Transfer Block Diagram
2-70
2-72
2-74
2-74
2-75
2-77
2-78
2-78
2-79
2-80
2-81
3-3
3-5
3-9
3-10
3-10
3-11
3-18
3-20
3-23
3-25
3-29
3-31
3-33
4-2
4-4
4-6
4-7
4-8
5-1
5-1
5-3
5-4
5-5
5-5
5-5
5-6
5-7
5-7
5-8
5-10
5-10
6-1
6-3
6-5
ix
Figure
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
Figure
Page
Write Data Transfer Block Diagram
Microprocessor Block Diagram
Microinstruction Expansion
Microinstruction Translation
Branch Multiplexing Circuits
Microinstruction Execution Example
WCS Block Diagram
RAM Board Column Select
WCS Extension Block Diagram
Microprocessor Buses and Registers
Buses and ALU Block Diagram
Buffer Storage Block Diagram
6-6
6-7
6-7
6-8
6-9
6-10
6-11
6-12
6 e 12
6-13
6-17
6-18
6-16
6-16A
6-17
6-18
6-19
6-20
6-21
6-22
6-23
6-24
6-25
6-26
6-26
Page
Buffer Storage Allocation and Contents
Buffer Storage Byte Definitions
Flexible Disc Interface Block Diagram
FD Track Format
IPL Flow Chart
Microprocessor Timing Logic
Nominal Microprocessor Timing
Detailed Microprocessor Clock Timing
Detailed Microprocessor SCU Addressing and ALU Path Timing
Controller Interface Block Diagram
Storage Control Interface Line Drivers and Receivers
SCU to Controller Interface Timing
Controller to SCU Interface Timing (Data Transfers)
6-20
6-20A
6-21
6-23
6-24
6-26
6-27
6-28
6-29
6-30
6-30
6-31
6-31
LIST OF TABLES
Table
Page
Table
2-1
2-2
2-3
2-4
2-5
2-6
4-1
5-1
5-2
2-2
2-16
2-17
2-18
2-19
2-81
4-3
5-8
5-8
5-3
5-4
Command Summary
Sense Control Block
Sense Byte 0-7 Bit Definitions
Message Table Formats
Sense Bytes 8-23 Bit Definitions
Device Reserve/Release Command Functions
Microinstruction Field Definitions
Input Control Signals
Output Control Signals
3672.21-0001-10175
6-'
6-2
6-3
6-4
6-5
6-6
6-7
Page
Data Signals
Power Requirements
WCS ECC Matrix
Example Data Word Applied to WCS ECC
Check-1 Multiplex Error Conditions
Buffer Storage ECC Matrix
Example Data Word Applied to Buffer Storage ECC Matrix
FDF Multiplexer Output Bits
ECR Bits
5-9
5-9
6-14
6-14
6-16
6-19
6-19
6-23
6-32
1.1 SCOPE
This manual contains operating principles for the
MEMOREX 3672 Storage Control Unit (SCU), which
functions as the primary controlling element in the
MEMOREX 3672-based Disc Storage Subsystem. Since
the SCU exercises primary control in the Subsystem and
participates in all Subsystem operations, this section of
the manual will. describe pertinent characteristics of the
complete 3672-based Subsystem, with particular details
about the 3672 SCU in the following sections.
3672.21-0001-10/75
Usage/Error Recording
Error Correction
Program Compatibility
Error Recovery
The Subsystem receives, decodes, and interprets
commands from the IBM System/360 (with Block
Multiplexer) or 370 channel. It responds to the same
set of (CCWs) used in IBM programs to operate the
3330 Facility.
Data Protection
To protect data, the operator can inhibit write commands by utilizing a READ-ONLY switch on each
drive.
System Disabling
The operator can easily take the 3672-based Subsystem offline (for diagnostic testing or maintenance)
Four-Channel Switch
The four-channel switch is identical to the twochannel switch in operation; however. four independent channels may be connected to the 3672 SCU.
These four independent channels may be connected
with one to four separate CPUs.
Operator/Diagnostic Console
To facilitate operator monitoring and FE maintenance.
each drive within the module employs a separate
Operator /Diagnostic console.
Three-Channel Switch
The three-channel switch is identical to the twochannel switch in operation. except that three independent channels may be connected to the 3672
SCU. The three independent channels may be connected with one to three separate CPUs.
Microprogramming
Two-Channel Switch
The two-channel switch provides the capability for the
3672 SCU to be shared by two IBM System/360 or
370 Block Multiplexer Channels. The two channels
may be attached to either the same or different CPu;;. ~
Individual drives attached to the 3672 SCU may be ---reserved for the exclusive use of either of the
channels.
Drive Addressing
Priority
The Memorex FE can assign a priority to each 3672
SCU and its address.
Record Overflow
Tag/Untag Switch
This switch is utilized on SCUs equipped with one of
the multiple channel switch features. When the
switch is in the TAG position. each channel must
accept the Device End Signal resulting from a pack
change or a unit plug change before the channel can
1-1
1-2
IBM
SYS 360
SYS 370
WCS Expansion
J+--'-----.
3672
SCU
19
Track Capacity
13,030 bytes
Cylinder Capacity
247,570 bytes
Pack Capacity
Module Capacity
Power Options
A subsystem can be supplied to operate from a threephase 2081230 Vac 60 Hz or 220/380 Vac 50 Hz
power source.
1.5 COMPATIBILITY
UP TO
4 CON
TROLLERS
PER SCU
UP TO
L_-"
4 DDM,
(8 DRIVES,
PER CON
TROLLER
LI _ _
10
No of Recording Surfaces
CTLI
CHNL
""'-1
32-Spindle Feature
Average Latency
8.33 msec
7 msec (maximum)
50 msec
27 msec
806,000 bytes/sec
1-3
3672.21-0001-10/75
4. Miscellaneous Errors
Overflow Record
Multitrack Operation
On Read or Search commands the operation will
become a multitrack operation if bit 0 of the respective
command is a 1. This allows an entire cylinder to be
searched with one command.
c. Command Overrun - If during command chaining the channel fails to meet the real-time
chaining constraint of the Subsystem. the SCU
will initiate a retry of the failing command.
If during data transfer the
d. Data Overrun channel fails to meet the real-time requirements of the Subsystem. the SCU will
initiate a retry of the failing command.
The SCU contains counters which enable it to maintain a statistical log of the usage and error occurrences for each drive in the Subsystem. The usage
counters count the total number of access motions
and the total number of data bytes transferred to the
channel. The error counter is an accumulation of the
total number of correctable or uncorrectable Read
errors and Seek errors. The counter data is periodically transferred to the channel for system logging.
Error Correction
The error correction function provided in the 3672based Subsystem allows the SCU to detect errors and
correct these errors through the use of Command
Retry. The correction of a failing command through
Command Retry is used for the following errors:
1. If the data is determined to be uncorrectable (i.e.,
the error exceeds the correction code capability),
the channel is signalled and the command may be
retried under control of the channel.
2. If the data error is correctable and it occurs in the
data fiele;! of a record, the SCU passes on to the
channel the information necessary to correct the
data.
3. If the data error is correctable and occurs in the
Home Address, Count or Key fields. the SCU
corrects the data which is being held in a buffer
Diagnostics
The control unit contains microprograms which are
used for online, inline, and offline servicing of the
SCU, Controllers. and DDMs. When the FE inserts the
service module plug into one of the drives. the drive
becomes offline to the operating system and online to
the control unit. Using the proper Memorex diagnostic
programs, diagnostics can then be run and error
messages displayed via the USing system. Diagnostics
Select a head.
1-4
......
FLEXIBLE DISC
ADDRESS BUS
MEMORY OUT BuS
~
~~
CONTROLS ..
.. FD ADDRESS BUS
~
.~
~~
BRANCH
FLEX DISC
INTERFACE
CONTROL STORAGE
CONTROL CI RCUITS
.i~
FLEX
DISC
DRIVE
CONTROLS
I
I
I
I
D
BUS
REGISTER
SR
REGISTER
I
I
I
"'"
.4 ~
.. WRITE BUS
CONTROL STORAGE
(MEMORY)
INCR
REGISTfR
~,
~r
TOA/F
MUl TlPLEXER
FE PANEL
'~D2
f-----
....
.......
FE CONTROLS
-..
.. SW!.',
~
MICROPROGRAM DATA
FLOW CONTROLS
f - -...
---
-- -- ------
..
CTl CONTROLS
TO BRANCH
CONTROLS
4~
.. ~
DATA FROM
BO. CHF CI
BRANCH
CONDITIONS
....
CONTROL" ....
--..
CONTROLLER
INTERFACE
I
CTl DO BUS
CONTROLLER/DRIVE
INTERFACE
AND CONTROLS
III
....
BRANCH
CONDIT,O'<S
I~
I'
READ/WRITE
(SERDES)
.4~
READ
I
STORAGE CONTROL UNIT
HEAD
POSITIONING
po
01 BUS
3673
.~
CONTROLLER
SERVO
PULSES
SERVO PULSES
I
I
I
I
3672
...
ORDER
DECODE
I
1--- - - - - -
I
I
I
CHANNEL
INTERFACE
1~
...
BUS :-
DRIVE DO BUS
~ DRIVE
DATA TO
BI. CT. CHC
REGISTERS
--
..
~RIVE OR~ER
.
..
... INDEX
r""
_..J
DRIVE CONTROLS
I
TO BRANCH
CONTROLS
I
I
REGISTE R ..
R/W
CONTROL
~Ir
WRITE DATA ..
..,..
WRITE
I
I
HEAD
MOTION
~r
......
DISC
PACK
READ/WRITE
CONTROLS
.... READ DATA
.....
3670/3675
DISC DRIVE
1-5
Actuator
An electromagnetic actuator moves the carriage
assembly to any of 411 (815) cylinder positions.
Carriage Assembly
The carriage assembly consists of 1 9 Read/Write
heads and one servo head mounted on a carriage.
1-6
SECTION 2. COMMANDS
2.1 GENERAL
This section defines and discusses the commands per
formed by the 3672 SCU during execution of liD
instructions. The section is divided roughly into two
halves. The first half contains instruction and command
word formats, followed by a detailed description of each
command in both narrative and flow diagram form. The
second half discusses command-related hardware
operations, such as command retry, rotational position
sensing, and overflow records.
IS
14 15
as follows
16
(NOT USED)
OP
19
20
B,
D,
0-7
8-14
Not Used.
15
Start liD
Start liD Fast Release
Test liD
Halt liD
Halt Device
Channel Address Word
Channel Command Word
Channel Status Word
Program Status Word
Must be zero.
21-23
24-27
START 1/0
The Start I/O instruction initiates an I/O operation upon
detection that the addressed channel, SCU, and drive are
available.
16-20
2.3.1 Introduction
Not Used
31
0-1 5
OP (Operation Code)
16-19
TEST 1/0
20-31
0, (Displacement)
An immediate field added to the contents of the
register at B, to develop bits 16-31 of a 32-bit
result. This result identifies the channel and
device addressed by the instruction and has the
following format
Halt liD
The Halt I/O instruction terminates the operation in
progress at the channel
HALT DEVICE
0
15
(NOT
USED)
16
20
00000
21
23
CHNL
ADDR
24
27
SCU
ADDR
28
31
DEV
ADDR
3
KEY
0000
31
8
COMMAND ADDRESS
2-1
TABLE 2-1
COMMAND SUMMARY
HEX CODE
COMMAND GROUPINGS
CONTROL
COMMAND NAME
I
SENSE
READ
WRITE
SEARCH
SENSE COMMANDS determine the status of the Subsystem and identify the specific
nature of any errors or unusual conditions that have occurred.
WRITE COMMANDS transfer information from the system main storage to the
SCU for recording on a disc pack. While
writing a record on a disc track, the
Controller appends the appropriate correction code bytes to each record area.
Update Write Commands (nonformatting) operate on previously formatted tracks to update existing
records.
Formatting Write Commands initialize
tracks and records, and establish the
length of the areas within each
record.
SEARCH COMMANDS transfer a specific number of bytes from system main storage to
the SCU. While executing a command, the channel operates in the Write mode while the
_disc storage operates in the Read mode. Incoming data from main storage is compared
'With outgoing data from disc storage. When search criteria specified in the command are
satisfied. the status modifier bit is set. This bit causes the channel to skip the next CCW
in the chain and fetch the next command from main storage. Each search command
operates on one record at a time. To search another record, the command must
be reissued.
tSet RPS command is valid only if the 2860 Attachment Feature is installed. See paragraph 3.12.
3672.21-0001-10/75
NO-OPeration
SEEK
SEEK CYLINDER
SEEK HEAD
SPACE COUNT
RECALIBRATE
RESTORE
SET FILE MASK
SET SECTOR
DIAGNOSTIC LOAD
DIAGNOSTIC WRITE
SET RPS t
03
07
OB
lB
OF
13
17
lF
23
53
73
2F
SENSE I/O
READ AND RESET BUFFERED LOG
READ DIAGNOSTIC STATUS 1
DEVICE RESERVE
DEVICE RELEASE
04
A4
44
84
94
READ
READ
READ
READ
READ
READ
READ
READ
READ COMMANDS transfer information from a disc drive to the system CPU. All
except Read IPL and Read Sector may operate on overflow records and in multitrack
as well as singletrack mode. On all read commands. the SCU examines correction code
bytes to check 'the validity of each record area, and adds a parity bit to each byte.
--i{
DATA
KEY AND DATA
COUNT. KEY. AND DATA
RO
COUNT
HOME ADDRESS
IPL
SECTOR
WRITE DATA
06
BIN (PACK)
86
BE
9E
96
92
9A
-B9
Bl
01
F1
A9
C9
E9
----..
I
I
00
0OOO-019A
.-3670
0OOO-032E
.-3675
00 100-12
05
001 10
01 1 15 1 19 1 11
vlv
vi
V
V
\lJ
07 1 OB 11B
1-../
NONE PERMITTED
vlv
vlvlv Iv
V I V Iv
I V Iv
Iv
I
NONE PERMITTED
19
29/A9*
~V
0
00
HEAD
HEX CODES OF
DRIVE ADDRESS BYTES
CYLINDER
MASK
BYTE BITS
39
31
51
71
29
49
69
~ WRITE
22
SEARCH
SEARCH
SEARCH
SEARCH
SEARCH
SEARCH
SEARCH
...
WRITE RO
WRITE HOME ADDRESS
ERASE
...
OE
lE
16
12
1A
02
05
00
10
01
15
19
11
SUMMARY INFORMATION
31/Bl*
39/B9*
V
V
vi
vi
V
10
V
NOT REQUIRED
STATUS
BYTE
1
BITS SET IF
SEARCH CRITERIA ARE SATISFIED
CSW
NAME
BIT
33
STATUS MODIFIER
36
CHANNEL END
37
DEVICE END
2-2
0-3
0-7
4-7
8-31
Command Address
Designates the location of the first CCW in
main storage.
XXXX XXll
XXXX Xl00
XXXX XXl0
XXXX XXOl
XXXX XOOl
37-39
40-47
Not Used.
48-63
Count
Specifies the number of eight-bit byte locations
in main storage area designated by the data
address.
CD (Chain Data)
When set to 1, specifies chaining of data.
33
8-31
Command Address
An address that is eight positions higher than
the address of the last CCW used.
32
Attention-not used.
33
Status Modifier
Set for three conditions (1) Whenever a Search
IDIKey High, Search IDIKey Equal, or Search
IDIKey Equal or High command has been
executed and the search criteria satisfied; (2)
With Busy bit to indicate SCU Busy, or (3) With
Unit Check and Channel End to indicate retry
status.
Data Address
Specifies the location of a two-byte address in
main storage. This is the address of the area
associated with data transfer operations.
32
Must be zero.
36
Must be zero.
Control
Sense
Read
Write
Search
4-7
34
35
34
31
32
39 40
47
48
0000
COMMAND
ADDRESS
DEV
STATUS
CHNL
STATUS
COUNT
37
CMD
CODE
31
32
33
34
35
DATA
ADDRESS
CD
CC
SLI
SKIP
FLAG
FLAGS
36 3739 40 47 48 63
PCI
000
(NOT
COUNT
USED)
35
Device End
Indicates that an access mechanism is free to
be used.
Channel End
63
Busy
Indicates that the selected drive is busy. In
conjunction with bit 33, indicates the SCU is
busy.
36
0
SCU End
Skip Flag
When set to 1, specifies suppression of a
transfer of information to main storage during a
Read or Sense operation. Checking takes place
as though the information has been placed in
0-3
38
Unit Check
Set whenever an unusual or error condition is
detected.
2-3
39
40-47
Unit Exception
48-63
40:
41:
42:
43.
44:
45:
46:
47'
Program-Controlled Interruption
Incorrect Length
Program Check
Protection Check
Channel Data Check
Channel Control Check
Interface Control Check
Chaining Check
Count
The residual byte count from the last CCW
used.
0-7
In
System Mask
8-11
0: Channel 0 Mask
1: Channel 1 Mask
2: Channel 2 Mask
3: Channel 3 Mask
4: Channel 4 Mask
5: Channel 5 Mask
6: Channel 6 Mask
7: External Mask
12
Must be zero.
13
14
W (Wait State)
15
P (Problem State)
16-31
32-33
34-35
CC (Condition Code)
36-39
SYSTEM
MASK
811 121315 16
KEY
M.
W.
P.
31 ~233 3435 36 39 40
INTRPT
CODE
ILC
CC
Bit
Bit
Bit
Bit
63
PROG INSTRUCTION
ADDRESS
MASt<
40-63
36:
37:
38:
39:
Instruction Address
2-4
2.4.1.1 SYSTEM
The CPU executes a Start liD instruction. Channel
Address Word (CAW) specifies the main storage location
of the first Channel Command Word (CCW). The SCU and
drive to be used are specified by the Start liD
instruction
SYSTEM
(CENTRAL
PROCESSING
UNIT)
..
SYSTEM
INTERFACE
ICHNL AND
CTRLS)
INTERFACE
L - -
- -
!....--!
SE~
f,lPROG
r--MODULE STATUS
It.FORMATION
CONTROLLER
~c;-- ~I
I
I --1
-
PROCESSOR
--
~A~
ZON-:;:-RDLt7R 1
1
INTERFACE...J
L.. -
the
head-arm
..
BUS OUT
.. BUS IN
TAG OUT
DATA
---.,
IL _
INTERIOR
FNOT~~~~~:ANEL
___
_ _ _ _ _IFEI
_
Head Access
assembly
Control
Storage that contains
a Writable
microprogram routines that define the data handling and drive control.
r ~H:N~L- ~
Mechanism l moves
...JI
TAG IN
.-
370
2-5
302
ALLOW CHANNEL
DISABLES IF
NO OUTSTANDING
DRIVE INTS
FOR CHANNELS
YES
302
SCAN BUFFER
FOR ANY
STATIC
INTERRUPTS
CALCULATE
ADDRESS OF
POLLED
DEVICE
302
UPDATE DE
READIES IF
REQUIRED
SET
SUPPRESSIBLE
REQUEST IN IF
ANY STATIC
INTERRUPTS
NO
RAISE
REOUEST
IN
302
302
"OR" CU END
IN ENDING
STATUS IF
REOUIRED
302
POLL DRIVES
FOR
INTERRUPTS
SET CUE
INDICATOR
PRESENT
CU BUSY
STATUS
302
"OR" CU END
IN ENDING
STATUS IF
REQUIRED
303
SET
NONSUPPRESSIBLE
REQ IN IF ANY
DYNAMIC
INTERRUPTS
FETCH
DDW 0 AND 1
NO
YES
303
YES
RESET
INDEX
YES
303
SET UP
STRING POINTER
IN
ROI7
080
3672.21-0001-10175
2-SA
303
303
FETCH
CHANNEL
INTERRUPT
WORD
SET JlPROG
DETECTED
ERROR
SET NOT
SINGLE STRING
SELECTION,
/1PROG DETECTED
ERROR
RESET
INDEX
SET BUSY
IN DRIVE
STATUS
CLEAR
DRIVE
STATUS
303
OBTAIN STATUS
FROM DRIVE
AND STORE IN
S~LECT
DEVICE
G7
303
INITIALIZE
CMD OUT TIMER.
RAISE OP IN
AND ADRS IN
SET IlPROG
DETECTED
FRROR
PRUPAGAT~
SELECT
OUT
SET "LONG
BUSY ON
r:HNL INIT
INDICATOR
3672.21-0001-10/75
2-58
CLEAR
CHANNEL
COMMAND
00 NOT
SET NEW
COMMAND
IN R3/B
FETCH
SCB
303
YES
RESET RETRY
IN PROGRESS
AND DEF/ALT
NO
SET
LOCK
CHANNEL
SWITCH
MAKE RESERVE
OR RELEASE
CMOS LOOK
LIKE SENSE
CMD
YES
303
303
SET DE
STATUS
SET UC
STATUS
3672.21-0001-10/75
2-5C
V
L'"
303
SET
FORMAT 2,
MESSAGE 0
SET LONG
CONNECT
FOR THIS
INTERFACE
FETCH USAGE
COUNTER
FOR THIS
STRING
303
READ 3/6
CODE
FROM DRIVE
YES
303
READ DEVICE
TYPE AND
CAR/CHAR
ENABLE
CHECK-2
303
SET
FORMAT 6,
MESSAGE 0
303
SET
FORMAT 2,
MESSAGE 0
FETCH ERROR
LOG BLOCK
303
SET
INTERVENTION
REQUIRED
SET
ENVIRONMENTAL
DATA
PRESENT
3672.21-0001-10175
2-5D
YES
YES
303
YES
SET
PRIME
DEVICE
INTERRUPT
SET
EQUIPMENT
CHECK,
PERM ERROR
303
SET
STACK AT DEVICE
AND
UNTtMED
303
303
SET
FORMAT 1,
MESSAGE 5
SET
SIP
303
SET
EQUIP CHECK,
WRONG CCW
NO
303
RESET
POLL ENABLES
ON OTHER
CHANNELS
YES
YES
307
304
306
11
3672.21-0001-10/75
2-5E
303
303
SEl
CHAINING
AND
UNTIMED
SET
DE
OWED
YES
YES
303
303
INITIALIZE
CMD OUT TIMER.
RAISE OP IN
AND ADRS IN
RESET
RETRY
PARAMETERS
YES
'OR" BUSY
INTO
STATUS
SET
BUSY
SET
ASSIGN AND
RESET PE'S
ON OTHER CHNLS
303
SET
DEVICl
BUSY
STATUS
DROP
ADRS IN
12
3672.21-0001-10 75
2-5F
NO-OP
Command Code 03 (hex)
(Figure 2-2)
INITIAL STATUS-Channel
presented
End
and
Device
End
SEEK
Command Code 07 (hex)
(Figure 2-3)
(HEX)
CYLINDER
BIN
HEAD
BYTE
0
BYTE
1
BYTE
2
BYTE
3
BYTE
4
BYTE
3670
00
00
00
00
00
01
00 TO FF
00 TO 9A
00
00
00 TO 12
00 TO 12
3675
00
00
00
00
00
00
00
00
00
01
02
03
00
00
00
00
TO
TO
TO
TO
00
00
00
00
00
00
00
00
FF
FF
FF
2E
TO
TO
TO
TO
12
12
12
12
SPECIAL REQUIREMENTS-
2-6
This command requires the Seek Address to be transferred to the SCU. The
SCU selects the Controller and drive
and transfers Seek Control information
to the drive. The drive controls the
movement of the access to the new
position.
SEEK CYL
Seek Cylinder command is the same
as Seek command.
SEEK HEAD
Seek Head is the same as the Seek
command except only the head address is changed.
SEEK ADDRESS
RST TRK
ORIENTATION
05F
306
BIB
C I C
3670
ZEROS
0-410
ZERO
0-lB
I SCU
3675
ZEROS
0-814
ZERO
0-18
II
r--
- -*,
RECONNECTS
TO CHANNEL
(IF BLOCK MUX
CHANNEL)
L ____ ...I
PRESENT
CHNL END AND
DEVICE END
TO CHNL
306
SCU SENDS
'DEVICE END
.TO CHNL
DRV SENDS
SEEK COMPLETE
TO SCU
306
306
. RST SEEK
COMPLETE
INTERRUPT
3672.21-0001-10175
It
I
I
307,302
2-7
SEEK CYLINDER
Command Code 08 (hex)
(Figure 2-3)
BIN
HEAD
BYTE
0
BYTE
1
BYTE
2
BYTE
3
BYTE
4
BYTE
5
3670
00
00
00
00
00
01
00 TO FF
00 TO 9A
00
00
00 TO 12
00 TO 12
3675
00
00
00
00
00
00
00
00
00
01
02
03
00
00
00
00
TO
TO
TO
TO
00
00
00
00
00
00
00
00
FF
FF
FF
2E
TO
TO
TO
TO
12
12
12
12
(Figure 2-3)
SEEK HEAD
Command Code 1 B (hex)
BIN
HEAD
BYTE
0
BYTE
1
BYTE
2
BYTE
3
BYTE
4
BYTE
5
3670
00
00
00
00
00
01
00 TO FF
00 TO 9A
00
00
00 TO 12
00 TO 12
3675
00
00
00
00
00
00
00
00
00
01
02
03
00
00
00
00
00
00
00
00
00
00
00
00
TO
TO
TO
TO
FF
FF
FF
2E
TO
TO
TO
TO
12
12
12
12
proper head.
INITIAL STATUS-Normally zero.
SPECIAL REOUIREMENTS-
SPECIAL REOUIREMENTS-
2-8
SPACE COUNT
Command Code OF (hex)
(Figure 2-4)
COUNT-Must be three or greater to transfer the requisite three bytes. If count is than three, the specified
number of bytes is transferred and the value of the
nontransferred bytes is assumed to be zero
CHAINING REQUIREMENTS
304
~--
SPAC'COUNT
The data is used on the next command
to define the key and data length
because they could not be read fr'Jm
the count field. If the number of bytes
is less than 3. the succeeding counts
are set to zero.
037 (041)
LOCATE START
OF NEXT CNT FLO
037 (060)
037 (060)
SET END OF CNT
FLO ORIENTATION
FOR USE WITH
NEXT CMD
306
PRESENT CHNL
END AND DEVICE
END STATUS
TO CHNL
307 302
3672.21-0001-10175
2-9
RECALIBRATE
Command Code 13 (hex)
(Figure 2-5)
3---
306
A'CAUBAAT>
r--SCU- - -*'
I
I
DISCONNECTS
FROM CHANNEL
(IF
It
I
~~~~~E~)UX I
L _ _ _ ...;,..J
MOVE ACCESS
IN REVERSE TO
CYL 000
032 (03E)
TO CONTROLLER
032 (03E)
START ACCESS
MOVEMENT IN
REVERSE
DIRECTION
DRV SENDS
AnENTION
TO SCU
SEND REZERO
TO CONTROLLER
.-- --,
SCU RECONNECTS
TO CHANNEL
(IF ~~~~~E~)UX
It
I
I
L ____ ..J
YES
306
306
SCU SENDS
DEVICE END
TO CHNL
SCU SENDS
CHNL END AND
DEVICE END
TO CHANNEL
307. 302
3672.21 -0001-10175
2-10
RESTORE
(Figure 2-6)
RESTORE
304
RESET
TRACK
ORIENTATION
304 (05F)
PRESENT ZERO
STATUS TO CHNl
306
307.302
3672.21-0001-10175
2-11
(Figure 2-7)
-c
the
type
of
Write
and
Seek
SET
FILE MASK
306
036
Bit
5 6 7
a
a
a
[TI0
a a a a a a a
0
0
0 a 0 0 a
a 0 0 0 0 0
a a 0 a 1 a a
0 a a 1 a a 0
a a a 1 1 a 0
0 0 a 0 0 0 0
a 0 a 0 0 1 o
a 0 a 0 a 0
a 0 a 0 0 0 o
01
1
1 1
0
0
a
a
a
0
0
rn
1
Function:
Inhibit write HA and write RO.
Inhibit all write commands.
Inhibit all format write commands.
Permit all write commands.
Permit all seek commands.
Permit seek cylinder and seek head.
Permit seek head.
Inhibit all seek commands and head switching.
Inhibit diagnostic write command.
Permit diagnostic write commands.
Not PCI fetch mode.
PCI fetch mode. (The storage control presents UNIT CHECK if command retry is
used to recover from ECC uncorrectable data errors.)
306
SEND CHNL END
ANO DEVICE END
TO CHNL
307.302
Set to zero.
2-12
SET SECTOR
C,lllll11,lI1d C"dt' 23 (hex)
(Figure 2-8)
SET SECTOR
038 (03C)
RECEIVE SCTR
NO. BYTE
FROM CHNL
COUNT-One.
SPECIAL REQUIREMENTS-
CHNL RESPONSE
303
PROCESS ANY
DRV INTS
038 (031)
SCU compensates the sector
value to ensure that
reconnection occurs at
proper value.
-----..
306
r--
--.,
: SCU DISCONNECTS II
I FROM CHANNEL I
L__
__..J
in-
3672.21-0001-10/75
2-13
DIAGNOSTIC LOAD
Command Code 53 (hex)
(Figure 2-9)
HEX 53
COUNT-One.
INITIAL STATUS-Normally zero.
NO
SPECIAL REQUIREMENTS
0123467
NO
PRESENT CE
ENDING STATUS
TO CHNL
RAISE REQUEST-IN
TO PRESENT DE
STATUS TO CHNL
2-14
DIAGNOSTIC WRITE
Command Code 73 (hex)
(Figure 2-10)
---1. __
H_E_X_7_3_ _
PRESENT
CE STATUS
TO CHNL
EXECUTE DIAG
AND ASSEMBLE
RSLTS
RAISE REQUESTIN
TO PRESENT DE
STATUS TO CHNL
2-15
1.
BIT
SENSE BYTES
1 1 1 2
3 1 4 I 5
I6
7 I 8
I9
1 10 1 11 112 1 13 1 14 1 15 1 16 117 I 18
j.--
J 19 120 1 21 J 22 J 23
--
SENSE CODE
FORMATIMESSAGE
Write Inhibit
Bits 0 through 3
are decoded into
formats 0 through 6.
Formats 0 through 6
are defined as follows:
0 Message Only
1 Device Errors
2 SCU Errors
3 Selective Reset
4 ECC Uncorrectable
5 ECC Correctable
6 Usage/Error Count
Operation Incomplete
Correctable
Bit
Arrangement:
01
10
11
00
f--
6
7
o and bit 0
of byte 1
Byte Number:
0
1
Bit Position
in Byte
Bits 4 through 7
are decoded into
Message 0 through C.
The meaning of the
message depends upon
the format decoded.
2-16
SENSE BYTE 13
Contents of DO Register
SENSE BYTE 14
FORMAT 1-DISC DRIVE EQUIPMENT CHECK
Contents of 01 Register
Bit 1
.,,0
Bit
2
Bit 3
Bit 4
Bit 5
Bit
Bit 7
01
:::~
2
3
4
5
6
7
}
01
Index error
Offset active
Seek Incomplete
Seek complete
Online
Attention
Busy
Record ready
Bit 1
Bit
Bit
Bit
Bit
4
5
6
7
0'
Not used
DiagnostiC 4
Diagnostic 2
Diagnostic 1
Not used
Mode 4
Mode 2
Mode 1
ORDER 2C
120
DO
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
Monitor
state
state
state
state
state
state
state
state
8
7
6
5
4
3
2
1
CE program ,t()[l
Not used
Interface check
Monitor check
Not used
Drive command reJect
0
1
2
3
4
5
6
7
0'
ORDER = 04
DO = 104
0
1
2
3
4
5
6
7
Not used
Write parity error
Read parity error
Bit ring error
Write compensation error
Data transfer control error
Missing PLO pulses
VFO phase error
ORDER 2C
DO = '10
Select lock
Not used
Abnormal stop
Not used
Servo disable
Seek not enabled
Not servo data
Even cylinder
ORDER 04
DO' '02
1
2
3
4
5
6
7
SENSE BYTE 13
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
0
1
2
3
4
5
6
7
Write Overrun
ACWrite
Write Fail
Subtractor Fail
Multi Write
Multi Head
35V Reg. Fail
Multi Write Data (3670)
Pad Unsafe (3675)
SENSE BYTE 14
ORDER = 2E
DO = 112
Contents of 01 Register
SENSE BYTE 15
Contents of CO Register
SENSE BYTES 16-21
SET TO ZERO
DRIVE INOP 3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Write Offset
Write & No Fine Track
Read & Write
Short Write
AC Write S.S.
Add Mark S.S.
Sink Fail
Not used
1
2
3
4
5
6
7
ORDER 2C
DO = 108
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100-1111
Controller check
MICROSelect active chec~
PROGRAM
GENERATED
01 check
Reserved
following errors:'
Not used
Tag valid missing (read. write)
Normal end check end missing (control)
Normal end miSSing (control)
No index after 40 ms or solid index
Unexpected status with check end
Controller selection address check
Preselection check
Zero pattern alignment check
Repetitive command overrun
Drive interrupt during busy
Drive status not as expected after
Seek or Set Sector command
Not used
SENSE BYTE 8
ORDER = 2E
DO = 113
Bit 1
Bit 2
'"0
Bit
Bit 1
Bit 2
Bit 3
Bits 4-7 define the
MCM = 138
Contents of DO Register
SENSE BYTE 21
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
MCM" 28
SENSE BYTE 11
SENSE BYTE 12
SET TO ZERO
Contents of CO Register
ORDER 24
DO = 100
.,0
Bit 2
.0< 3
STATUS BYTE 15
Bit
Bit
Bit
BII
Bit
Bit
0
1
2
3
4
5
6
7
SENSE BYTE 10
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
Bit
MCK
Bit 1
Bit 2
'0<
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
ECR
MCM = 108
.,,' ~
Bit
Bit
Bit
Bit
Bit
Bit
2
3
4
5
6
7
MCK
Bit
"" ~
2
3
4
5
6
7
ECR
01 Buffer Check
Select Active Check
Not Used
CE Alert
Channel Buffer Read Check
Channel AIC Interface Check
Channel BID Interface Check
Channel Transfer Error
1
2
3
4
MCM = 103
Failing
Failing
Failing
Failing
Failing
Failing
Failing
Failing
Address
Address
Address
Address
Address
Address
Address
Address
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
5
6
7
8
9
10
11
12
MCM = 104
SENSE BYTE 10
Bit
Bit
Bit
Bit
Bit
Bit
SENSE BYTE 9
Selective Reset
Single Buffer Error
Single WCS Error
Failing Address Bit
Failing Address Bit
Failing Address Bit
Failing AddreSS Bit
Failing Address Bit
Bit 1
Bit 2
,"0
MCM = 118
Bit
Bit
Bit
Bit
Bit
3
4
5
6
7
MCK
Not Used
Multi-WCS Error
A-Bus
B-Bus
T-Bus
Branch
IMPL
ALU
MCM = 110
2-19
SENSE BYTE 11
~O:
Bit
Bit
Bit
Bit
Bit
Bit
Bit
1
2
3
4
5
6
7
MCK
BR Multiplex Error
PS Error
OP Code Translation Error
Subroutine Error
WCS Error
Multiplexer Buffer Error
Buffer ECC Error
8uffer Write T-8us Error
Bit I
Bit 2
~"45
Bit
Bit
8,t
Bit
. Me<
6
7
Failing
Failing
Failing
Failing
Faoling
Failing
Falling
Failing
PI
P2
P3
P4
P5
P6
P7
P8
SENSE BYTE 14
Conents of RWC Register
MCK
DRIVE
DATA
WORD 4
SENSE BYTE 13
1
2
3
4
5
6
7
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bot
Bit
Bit
MCM,102
, .I
BUFFER
LOC L
13B
MCM = 101
,... ~
DRIVE
DATA
WORD 3
SENSE BYTE 12
1-
}RO;C
Bits 0 and 1
Bits 2-7
MCM = 105
SENSE BYTES 16-21
SET TO ZERO
}~ ~;E3R
:\
BUFFER
LOC
137
BUFFER
LOC
12E
SENSE BYTE 18
Bits 1-7
If zero. bytes 20-23 contain channel A and B information; if one. channel C and D information.
Not Used
f-
DRIVE
DATA
WORD 5
BUFFER
12D
Bit 0
BUFFER
LOC 13
BYTE 2
LOC
BUFFER
LOC 13
BYTE 3
}
BYTES
OAND
SENSE BYTE 15
1
BUFFER
LOC
Contain high. middle. and low error pattern bytes used for error correction function.
127 AND
128
SENSE BYTE 23
Bits 0-6
Bit 7
Not used-set to 0
Channel truncation
2-20
SENSE 110
Command Code 04 (hex)
(Figure 2-12)
COUNT---24
SENSE I/O
YES
014 (OIA)
306
PRESENT
CE, DE TO
CHANNEL
307,302
3672.21 -0001-10175
2-21
TeST I/O
Command Code 00 (hex)
(Figure 2 -13)
FLAGS-Not used.
COUNT -1.
3--
TEST I/O
NOTE
This command is a system instruction,
not a CCW. The subsystem treats the
command as an immediate comm'and.
One status byte is returned, to the
system.
306
PRESENT STATUS
TOCHNL
306
PRESENT ZERO
STATUS TO CHNL
307
3672.21-0001-10/75
2-22
(Figure 2-14)
COUNT-24.
3-
014 (07C)
SET UP SENSE INFO IN
BUFFER LOCATION
/0120. SET SCB AS
FOLLOWS:
A. FMT = 6
B. MSG = 0
C. ENVIRONMENTAL
DATA PRESENT
014 (alA)
XFER SENSE BYTES.
STORED IN BUFFER
LOCATION 120125.
TO CHNL UNTIL ALL
ARE TAKEN OR
TRUNCATION OCCURS.
ZERO OUT SENSE
AREA DURING XFER.
306
PRESENT CEo DE
GO TO
RESELECTION
ROUTINE
307
3672.21-0001 -10175
2-23
(Figure 2-15)
REQUIREMENTS-Diagnostic Load or
Write. must precede Read Diagnostic Status 1;
16 bytes of data are transferred from buffer
the SCU which normally contain the error
NO
NO
XFER 16 BYTES
OF ERROR CODE
TO CHNL
XFER
668 BYTES
TO CHNL
SET CE AND
DE STATUS
2-24
DEVICE RESERVE
Command Code B4 (hex)
(Figure 2-16)
24
HEX B4
RESERVE
FROM INITIAL
SELECTION
304
DEVICE RESERVE
84, DEVICE
RELEASE 94
HEX 94
RELEASE
YES
304
NO (RELEASE CMD)
DEVICE RELEASE
Command Code 94 (hex)
(Figure 2-16)
078
011
RELEASE
DEVICE
RESERVE
DEVICE
COUNT-24.
INITIAL STATUS-Normally zero.
SET UNIT
CHK IN
CHNL STATUS
SEND 24
SENSE BYTES
306
307,302
2-25
2.5.6.2 SYSTEM
STATUS AND
ERROR MESSAGE
..... DATA
....
CHANNEL
INTERFACE
CHANNEL
......
........
2.5.6.3 CHANNEL
ADDRESS COMMAND
AND DIAGNOSTIC
PROGRAM DATA
SYSTEM
.......
.....
....
SCU
I.....
DIAGNOSTIC
PROGRAM
DATA IN
~. DIAGNOSTIC
PROGRAMC ONTROl
OUT
1,
ADDRESS
CONTROl~
CONTROL STORAGE
2-26
2.6.1.1 SYSTEM
The system executes the Start 110 instruction which
addresses a channel command word (CCW) containing a
read command.
USING SYSTEM
IIF
I
I
I
I
READ
DATA
CONTROL
CHNL
CHANNEL
SYSTEM
I
I
L __
Transfers status
Microprocessor.
the
selected
drive
to
the
2.6.1.S PACK
I
I
I
SCU
CHANNEL
INTERFACE
_ I TAG IN
-I
MICROPROCESSOR
READ
DATA
AND
STATUS
IIF
-CONTROLLER
I
I
1
: I INDEX
------I
I
SERVO
TRACK
.J>ATA
I READ CONTROL
-I
__ I SER RD DATA I
: 1PLO
I
,'"
I
I
I BUS OUT 1
,I BUS IN
-I
I-----~ISCDRI~------I
I
I
..
..
CTL
I
I
READ
DATA
CONTROL
1
READ
DATA
AND
STATUS
of
I
I
READ
DATA
CONTROL 1
_I
READ
DATA
AND
STATUS
2.6.1.4 MICROPROCESSOR
The Read Count, Key, and Data; Read Key and Data; and
Read Data commands can operate on overflow records.
I
I
2.6.1.2 CHANNEL
DEVICE STATUS
READ
CIRCUIT
READ
DATA
--
SERVO
TRACK
_DATA
READ/WRITE
HEAD
I
I
PACK
READ
DATA
--
L ________________
2-27
READ DATA
(Figure 2-19)
(Figure 2-19)
2-28
(Figure 2-19)
NDEX
~
~
TRANSFERRED ON COMMAND
r-
Gl[]OME G21 COUNT IG2[JEY G2EJATA G31 COUNT IG2[JEY G21 DATA IG3
D~~A G4~NDEX
~
RECORD
I.---
k=
RO F I E L D - - - J
RI F I E L D d
(AND ALL OTHERS FOLLOWING)
~~~T
II I I I I I I I I
F
~::r-T
KL
DL
DL
EC
II"L..
2BYTE HD ADRS
KEY LENGTH
RECORD
2-29
307. 302
307.302
045 (04D)
306
RlAD DATA
READ KEY
AND DATA
Hf AD AND CHECK
U:C: fOR KEY FLD
044 (041)
IF NOT ORIENTED
TO RN FIELD.
CLOCK OVER
APPROPRIATE
FIELDS
NOTE
NOTE
306
044 (05F)
LOAD TAGS TO
RD DATA FIELD
AND GIVE CORRECT
XFER LGTH TO
CONTROLLER
IF NOT ORIENTED
TO RN FIELD,
CLOCK OVER
APPROPRIATE
FIELDS
044 (04D)
045 (05F)
READ DATA FLD
AND XFER DATA
TO CHNL
LOAD TAGS TO
RD KEY FIELD
AND GIVE CORRECT
XFER LGTH TO
CONTROLLER
045 (04D)
READ KEY FLD
AND XFER DATA
TO CHNL
Figure 2-19. Read Data, Read Key and Data, and Read Count. Key, and Data Flow Diagrams (1 of 2)
2-30
307 302
NOTE
This command transfers the count, key.
and data fields of the next field (except
ROlon the track
READ COUNT.
KEY. AND
DATA
HEX 1E OR BE
042 (041)
IF NOT DATA
ORIENTED.
ORIENT TO
NEXT DATA FLO
042 (05F)
LOAD TAGS TO
RD COUNT FIELD
AND GIVE CORR
XFER LGTH TO
CONTROLLER
042 (040)
READ AND XFER
eNT AREAS TO
CHNl: CC. HH.
R. KL. AND DL
042 (040)
SAVE KL AND DL
BYTES
042 (040)
YES
071
Figure 2-19. Read Data. Read Key and Data. and Read Count. Key. and Data Flow Diagrams (2 of 2)
3672.21-0001-10/75
2-31
(Figure 2-20)
(Figure 2-20)
Transfers the eight bytes (CC, HH. R. KL, and DL) of the
next count area encountered on the track (excluding RO)
from the disc drive to main storage.
COUNT-Eight.
INITIAL STATUS-Normally zero.
SPECIAL
CHARACTERISTICS-Command
execution
begins immediately if Read RO is chained from a Search
Home Address or Read Home Address. In these cases,
the SCU will not search for index.
~~UE~T
READ COUNT
Command Code: 12 (hex) single track
92 (hex) multi-track
I I I I I II I I I
r
FL T
--r
I
DL
DL
EC
2-BYTE HD ADRS
KEY LENGTH
RECORD
~~UE~T
II I I I II I II I
F
FL T
--r
I
KL
DL
DL
EC
I I
T - s J E ERR CORR
2-SYTE CYL ADRS
DATA LENGTH
2-BYTE HD ADRS
KEY LENGTH
RECORD
2-32
(Figure 2-20)
2-33
042 (040)
NOTE
YES
HEX 12 OR 92
042 (041)
NOTE
This command transfers the contents of
RO (count, key, and data) field to the
system.
READ
RECORD ZERO
HEX 16 OR 96
IF NOT DATA
ORIENTED.
ORIENT TO
FIRST DATA
FIELD
LOAD TAGS TO RD
KEY FIELD AND
GIVE CORRECT
XFER LGTH TO
CONTROLLER
045 (040)
042 (05F)
044 (040)
YES
045 (040)
ORIENT TO
INDX AND
CLOCK HA
LOAD TAG TO
RD COUNT
FIELD AND GIVE
CORRECT XFER
LGTH TO
CONTROLLER
042 (040)
READ AND XFER
CNT AREAS TO
CHNL: CC. HH,
R. KL, AND DL
YES
042 (040)
YES
LOAD TAGS TO
RD DATA FIELD
AND GIVE
CORRECT XFER
LGTH TO
CONTROLLER
306
NO
044 (040)
071
306
(SEE FIGURE 2-38)
306
Figure 2-20. Read Record Zero, Read Count. and Read Home Address Flow Diagram (1 of 2)
2-34
NOTE
HEX lA OR 9A
READ
HOME ADDRESS
041 (04A)
GET INDEX
ORIENTATION
041 (040)
041 (05F)
LOAD TAGS TO RD
HA FIELD AND
GIVE CORRECT
XFER LGTH TO
CONTROLLER
041 (040)
RD HA FLO FROM
CONTROLLER AND
XFER TO CHNL:
FLAG. CC. HH
071
SEND CHNL END
AND DEVICE END
TO CHNL
(SEE FIGURE 2-38)
306
Figure 2-20. Read Record Zero. Read Count. and Read Home Address Flow Diagram (2 of 2)
2-35
3672.21-0001-10/75
READ IPL
Command Code 02 (hex)
(Figure 2-21)
READ SECTOR
Command Code 22 (hex)
(Figure 2-21)
~'-------------v'----------~
NDEX Gl~OME
~
~
D~~A G4~NDEX
~
RECORD
I - - - R O FIELD----l
~RI FIELD~
(AND ALL OTHERS FOLLOWING)
Gl
2-36
s~1
044 (041)
ORIENT TO Rl
KEY FIELD
(HA AND RO
FIELDS ARE
SKIPPED AND Rl
IS READ)
START 1/0
FORCED IN CPU
LOAD TAGS TO RD
DATA FIELD AND
GIVE CORRECT
XFER LGTH TO
CONTROLLER
044 (OSF)
=:]---
304
READ SECTOR
048 (03B)
READ SCTR NO.
FROM THE DRV
TO THE SCU
044 (040)
READ DATA AND
XFER DATA FLO
TO CHNL
INITIAL
SELECTION
Th,s command causes the data field of
R1 on track zero, head zero of the
selected Drive, to be transferred by the
SCU to the uSing system. This data is
ThIS command IS normally set up by
IPL button. but may be Start I/O
InstructIon. If in a chain It must not be
preceded by a Set File Mask command,
or command IS rejected.
048
044 (040)
~~~:::~I~t~~:~!~Ou;~~~ ;~~~~~a~~f:~
is completed.
- - - j ---
04B
SET SECT NO
TO 0 IF IN 0 OR
1 RANGE. SUBT 1
IF IN LOW SIDE
OF SECTOR
READ IPL
306
047 i03E)
YES
Control Unit issues recalibrate to dnve
Instead of seek
SEEK TO CYL 00
AND HEAD 00
044 (04F)
PRESENT CHNL
END AND DEVICE
END TO THE CHNL
RESTART OPER
(NO ERR CORR
PROC IN USING
SYSTEM)
306
2-37
3672 .21 -0001- 10/75
2.6.4.2 SYSTEM
2.6.4.3 CHANNEL
Transfers
storage.
diagnostic
from
subsystem
to
system
2-38
~
I
SELECTED TO
CHANNEL.
LOCK CHANNEL
SWITCH IS ON
CHC BIT 4
CONTROLLER
RAISES TAG
VALID, INDICAT
ING THAT IT WILL
PERFORM THE MINIORDER
DATA BYTES
STORED IN R03
REG. AS THEY
ARE RECEIVED
FROM THE CONTROLLER
RAISE OPERATE
UP AND
UNSQUELCH
READ HEAD TO
CONTROLLER
ORDER SENT
TO CONTROLLER
(READ-Gl, ETC.)
CO=/SE
00=/47
I
ALL BYTES READ
WHEN DATA
TRANSFER
COUNTER DECRE
MENTS TO 0 &
INTERRUPT CONDITION OCCURS
I
DROP CHANNEL
TRANSFER AND
CHECK FOR
ERRORS FROM
DRIVE CHC BIT
FIRST SYNC IN
RECEIVED FROM
CONTROLLER.
REFER TO READ
LOOP SUBROUTINE,
FIGURE 2-23
IF NO CHNL
BUFFER READY
CHNL TRUNCATION INDICATED IN
FIELD CONTROL
BYTE
PRESENT ENDING
STATUS
INITIAL STATUS
SENT TO
CHANNEL
CT=/14
BI=IOO
(STATUS)
~ CO ~
CONTROLLER
CONTROL AND
STATUS DATA
I~---=---------,
TO SYSTEM
CHANNEL
I
I
rn
I
CONTROL AND
STATUS DATA
DRIVE
SCU
. . - DI
2-39
~----8DE
HA.CNT.KEY --8DC
------l
CNT=/E8
CIBUF=R03.INC)
Bl-073-2-- 800
STORE 4 BYTES IN
BUFFER LOCATION
FROM RTN O4C
PROCESS.RO
.------8EO
-BIDBR+INTi
+"0
B4-081l--8DF
WAIT FOR & THEN
SET RO '0 ~ FIRST
DATA BYTE
BIINT)
NO.OBR
B5-OB4-1--921
BR IF NO DBR.
81=R3
-BICBR)
TRUNC.B.3
B3-078-2--8EB
XFER BYTE TO CHNL
BR IF NO CBR
TRUNC. B. 3 - - 8EB
CLOCK. RO--8FO
.------8Fl
BYTE.O - - - 8 E l
}--+--+-+---'~BI RO
-BICBR)
TRUNC.B.C
F2-056-1--8EC
SEND DATA 8YTE TO
CYNL BR IF NO CBR
CHCo 08
RC=DI
BIBR5)
CLOCK.RO
D3-ll0-1--BFO
SET TRUNCATED',
BR IF CHNL INT
B(lNT)
ALL. DONE
D4-l20-2--BF9
DROP CHNL XFER.BR
WHEN DTC=O
BIUNCOND)
BYTE.O
D5-122-1--8El
DATA BYTE INTO
ROiO
PROCESS.Rl-8El
.------8E3
RI=DI
CNT E8
-BIDBR+INT)
B(lNT)
NO.DBR
F4-091-2-- 921
BR IF NO D8R
-./0
F3-088-1--8E2
WAIT FOR & THEN
SET Rl ,0 - NEXT
, DATA BYTE
BIBR1)
SC=O.WAIT
C7--138-2-- 936
BR IF DTC = O.
INORMAL EXIT)
G 58FA
=:J------DA
BIADR=SR)
C8-140-2
SET 'NO D8R' ERROR
RETURN ...
04006 B1
TRUNC. B. 0--8EC
0400602
B18R5)
CLOCK.Rl
H3-ll2-l--8F2
SET 'TRUNCATED
BR IF CHNL INT
r-----8F3
RI=DI
8IUNCOND)
BYTE. 1
J5-126-1--BE4
DATA BYTE INTO
R1 0
2-40
DIAGNOSTIC
DATA
DIAGNOSTIC
DATA
ADDRESS DATA
COMMAND DATA
--
SYSTEM
STATUS AND
DIAGNOSTIC DATA
CHANNEL
CHANNEL
CONTROLS
SERVO CONTROL
READC ONTROL
POWER ON CONTROL
STORAGE
CONTROL UNIT
(SCU)
DIAGNOSTIC
DATA IN
ADDRESS
CONTROL
SERVO DRIVE
CONTROL STORAGE
2-41
2.7.1.5 CONTROLLER
2.7.1.4 MICROPROCESSOR
The following text is keyed to the Write Operation block
diagram shown in Figure 2-25.
2.7.1.1 SYSTEM
'2.7.1.8 PACK
2.7.1.2 CHANNEL
The channel executes the CCW to transfer the write
command to the SCU.
l~sl-m,
SYSTEM -
;';;-IT-;- -
-l
~~6A
IIF
1 WRITE
BUS OUT
CTL
IIF
WRITE
DATA
DATA
CHNL I s C U - - - - - - - - - - - - - - - - 1
CONTROL
- - - - - - - - - . INFO
,r----'
l~c~I~---------------1
WRITE
DATA
(SERIAL)
I
I
WRITE
DATA
WRITE
DATA
PLO
BUS IN
CONTROLLER
SYSTEM
CHANNEL
CHAN~,EL
DEVICE
STATUS
INFO
INTERFACE
DEVICE
STATUS
INFO
I
I1_ _ _ _ _ _ _ _ _ _ _ _
L __________ _
TAG OUT
INDEX
WRITE
CONTROL
TAG IN
STATUS
MICROPROCESSOR
_____ J
L ___ ..JI
WRITE
CIRCUITS
SERVO
TRACK
DATA
READ/WRITE
HEAD
SERVO
TRACK
DATA
I1_ _ _ _ _ _ - - - - - - - - -
PACK
____ _
2-42
WRITE DATA
Command Code 05 (hex)
(Figure 2-26)
Channel End and Device End are presented after the ECC
bytes have been written for the data area.
DATA ADDRESS-Specifies main storage location of
data used to update record.
(Figure 2-26)
Performs record updating after track formatting. Execution of command causes specified data in main storage to
be written in key and data areas of selected record.
Number of bytes written is specified in the CCW count
field. It may be less than the key length (KL) and data
length (DL) specified in the formatted record.
~~E~T
I I I I I I I I I I
F
KL
T --rI. I
FL
2BYTE CYL ADRS
2BYTE HD ADRS
DL
DL
EC
RECORD
~~E~T
I I I I I I I I I I
F
T --rI
FL
2BYTE CYL ADRS
KL
I I
DL
DL
EC
2BYTE HD ADRS
KEY LENGTH
RECORD
2-43
(Figure 2-26)
TRANSFERRED ON COMMAN0-1
r::l
r::l 0 0 0 BOD
~G1L:JG~c:rl~:JG2CJG3
COUNT
R~i~D
DATA
G2LJG2CJG3
r::l
G4'V
~RIFIELDd
/..--ROFIELD----l
~~~T
I I I I I I I I I I I
T ---rI I I
F
KL
DL
DL
EC
FL
T , ' B J E ERR CORR
2BYTE CYL ADRS
DATA LENGTH
2BYTE HD ADRS
KEY LENGTH
RECORD
244
FROM
CMD 7.11
Chained from a Search Equal I D com
mand.
FROM
(2 OF 21
FROM
FIGURE 229
306
~-
WRITE KEY
--
L-_A_N_D"""'T"DA_T_A_~
Write number of
bytes given in count
062 (06D)
RECEIVE RESPONSE
FROM CONTROLLER
TO SHOW
COMPLETION
YES
062 (05F)
Write 1 Byte SCU+OEV
address and 46
bytes of zeros
LOAD TAGS TO
WR G2 AND GIVE
CORR XFER LGTH
TO CONTROLLER
FO DATA FIELD
CONTROLLER
CONTINUES
TO WR ZEROS IN
G4; SCU BUSY
TO ALL CHNL I/Fs
302
062 (06D)
TO
(2 OF 2)
mand.
062 (06D)
L-_W_R_IT. ,E~D_A_T_A_
... --
RECEIVE RESPONSE
FROM CONTROLLER
TO'SHOW
COMPLETION
BRING DOWN
OPERATE TAG
306
Figure 2-26. Write Count, Key, and Data; Write Key and Data; and Write Data Flow Diagrams (1 of 2)
3672.21.-0001-10/75
2-45
FROM
FIGURES
2-27.2-28.2-30
062 (060)
READ CC. HH. R#.
KL. AND DL FROM
CHNL AND SEND
TO CONTROLLER
062 (06D)
Chained from a Write RO; Write Count.
Key. and Data; Erase; or a.successful
Search Equal 10 or Search Equal Key
command
FROM
(1 OF 2)
A
RECEIVE RESPONSE
FROM CONTROLLER
TO SHOW
COMPLETION
_ _ _ _H_E_X_ID_I- -
-;
WRITE COUNT.
KEY. AND DATA
---r-_...
......
I
The Write Count. Key. and Data command writes a record (count. key. and
data) on the disc and track selected
by the system. Write CKD must be
chained from a Write RD. successful
Search Equal ID. or Search Equal Key
command
I
I
_ _ _ ...J
LD TAGS TO
WR G2 AND GIVE
CORR XFER LGTH
TO CONTROLLER
FOR RN KEY FIELD
LD TAGS TO
WR G3 AND GIVE
CORR XFER LGTH
TO CONTROLLER
FOR CNT FIELD
TO
TO
(1 OF 2)
(1 OF 2)
Figure 2-26. Write Count. Key. and Data; Write Key and Data; and Write Data Flow Diagrams (2 of 2)
3672.21 -0001-1.0/75
2-46
(Figure 2-27)
=:]
HEX 01
WRITE SPECIAL
- - - - - - __
_ C_O_U_N_T.,'_K_E_Y_'
ANO DATA
NO
TRANSFERRED ON COMMAND
~ml~~I~I~B~~B~~~I~B~~B~~~~~~
"
"
~
~
~
RECORD
I.----ROFIELO-..l
SET OVERFLOW
BIT IN BUFFER
TO WRITE
OVERFL9W REC
~RIFIELD~
lAND ALL OTHERS FOLLOWING)
TO
. FIGURE
FL
~
I I I
2-26
Figure 2-27. Write Special Count, Key, and Data Flow Diagram
3672.21-0001-10/75
2-47
(Figure 2-28)
=:J----
DECODE
COMMAND
AS WRITE
RECORD ZERO
NO
304
SET UNIT CK IN
STAT BYTE & CMD
REJ IN SENSE DATA
LOAD TAGS TO
WR G2 AND GIVE
CORR XFER LGTH
TO CONTROLLER
FOR COUNT FIELD
TO
FIGURE
2-26
~~E~TIFICIII
IIKLIDLIDLIECI
T -rI I
FL
T , . B J e ERR CORR
2BYTE CYL ADRS
DATA LENGTH
2BYTE HO ADRS
KEY LENGTH
RECORD
2-48
(Figure 2-29)
DECODE CMD
AS WRT HOME
ADDR
Channel End and Device End are presented after the ECC
bytes have been written for the data area.
WAIT FOR
INDEX
--, r
~Gll ~D~E
061 (05F)
TRANSFERRED ON COMMAND
IG21 COUNT I G 2 E J G 2 E J
G3
1 COUNT I G 2 E J G 2 E J G 3
I i '
~ROFIElD
Gl
----l ~THERS
RrFIELD~
DATA
OF
G4
LAST
RECORD
~
INDEX
PT
LOAD TAGS TO
WR G1 AND GIVE
CORR XFER LGTH
TO CONTROLLER
061 (060'
FOLLOWING
TO
FIGURE 2-26
3672.21 -0001-10175
2-49
ERASE
Command Code 11 (hex)
(Figure 2-29)
In
CHAINING REQUIREMENTS-
3----
ERASE
NO
LO TAGS TO ERASE
G3 (WR o's TO INDEX)
AND GIVE CORR
XFER LGTH TO
CONTROLLER
TO
FIGURE
2-26
Gl
2-50
r-----..,
TURN ON
CHC BITS 0,1
TO PLACE CHNL
INTERFACE
IN WRT MODE
SERVICE OUT /
DATA OUT FROM
CHNL SIGNALS
CHNL INTERFACE
THAT A BYTE
IS ON BUS OUT
/lPROG MOVES BO
TO DO
FOR INPUT TO
CONTROLLER
TURN ON CO 0
TO SEL DRV
CHNL INTERFACE
PLACES BYTE IN
CHNL BUFFER REG
SYNC IN RECEIVED
FROM CONTROLLER,
DO VALIDATED BY
SYNC OUT
SERDES SIGNALS
-; THAT IT IS READY
I WITH B(DBR)
NO
I
I
L _____ .J
YES
NO
IF BO REG IS FREE
BYTE IS XFERD
FROM BUFFER
TO 80 AND
B(CBR) IS
TURNED ON
LOAD TAGS TO WR
FIELD AND GIVE
CORRECT XFER
LGTH TO
CONTROLLER
CHNL INTERFACE
ASKS FOR NEW
BYTE BY RAISING
SERVICE IN:
DATA IN
r----.,
_ -I microprogram that
a byte IS in BO I
I Register,
I
L _ _ _ _ ...J
SET DBR TO
INDICATE THAT
DO IS READY
FOR NEW LOAD
r-----,
- 1 :~~f:ra a~~ea~:t~:~ I
I on BO Register I
L- _ _ _ _
..J
2-51
CONTROLLER
,------------,
I
B
CONTROL
AND STATUS
DATA
up the drive
I
I
CUDI
I
I
FROM SYSTEM
CHANNEL
I
I
SCU
I
I
I
I
I
I
I
I
CONTROL
AND STATUS
DATA
DRIVE
I
SERDES
VFO
SERIAL WRITE
DATA
I
I
I
I
I
I
I
L _________ --.J
2-52
C C H H - - - - 1Bl
.----_ _ _ _ 1B2
CNT=/BO
C(RESET.DBR)
-B(CBR)
OVER. TRO
2-103-2--1C9
SET LARGE TIMER
BR IF OVERRUN
RO=BO GO
BYTE.0---1B3
B(INT)
DONE-l
B5-106-3--1 BF
READ BUS OUT
OVER. T R O - - 1 C9
GO = 100
C(CH.FREEZE)
-B(lNT)
BYTE.O
C3-157-2--1B3
GO FOR WRrlNG O'S
BR IF NOT DONE
FREEZE CH TRXF
lB6
SOME.ENTRY-1B4
Rl=/oo
-B(CBR)
OVER.TRl
E2-110-2-- lC6
ZERO Rl IC FOR TRN
IS CH READY!
-B(DBR.INT)
*+/0
F6-114-3-- lB6
LOAD DO FOR BUF/W
OVER.TR1-- lC6
GO=/oo
C(CH.FREEZE)
-B(lNT)
BYTE. 1
G3-- 148-2--1 B6
GO FOR WRT ZERO
BR IF NOT DONE
2-53
(Figure 2-33)
will
not
cross
NDEX Gl~OME
~
PT
ADR
I - - - - - - R O FIELD-----I
D~~A G4~NOEX
LAST
RECORD
PT
~RI FIELD~
lAND ALL OTHERS FOLLOWING)
2-54
051
READ C, C, H, H
BYTES FROM
DRIVE & CHNL &
COMPARE
::1--
HEx:l
SEARCH HOME
ADDRESS EQUAL
POST TYPE
OF ERROR
SET CONTROLLER
TO READ MODE
051
051 (04E)
READ ID BYTE
FROM DRIVE
051 (04F)
SET CHNL END,
DEVICE END, &
STATUS MODIFIER
ENDING STATUS
CHECK FOR
MORE ERRORS
DURING SEARCH
SET NO RECORD
FOUND IN
SENSE CONTROL
BLOCK
306
051 (04F)
YES
SET EOC
IN SENSE
CONTROL BLOCK
SET CHNL
INTERFACE
TO READ
MODE
051
READ CAR, HAR,
FLAG BYTES
FROM DRIVE
SET HOME
ADDRESS PREREQUISITE IN
R3/9 TO ALLOW
CtlAINED WRITES
306
306
3672.21-0001-10175
2-55
(Figure 2-34)
SEARCH 10 EQUAL
Command Code: 31 (hex) single track
81 (hex) multi-track
R.
FLAGS-Used at discretion of the programmer.
COUNT-Should be five. If count is greater than five, only
the first five bytes from main storage are compared.
Channel End and Device End are presented to terminate
the command, and status modifier is presented if the
comparison was equal.
~ 10 SEARCHED
Fie
----.J
I I I II I I I
c
(Figure 2-34)
R.
FLAGS-Used at discretion of the programmer.
COUNT-Should be five. If count is greater than five, only
the first five bytes from main storage are compared.
Channel End and Device End are presented to terminate
the command, and status modifier is presented if the
track ID was high.
If count is less than five, a comparison of main storage
and track data continues until the CCW count is zero.
Channel End and Device End are presented to the
channel when the ID and correction code bytes are read
and checked. Status modifier is presented if the search
on the short field is satisfied.
INITIAL STATUS-NormallY zero.
I - 10 SEARCHED ~
I
ON COMMAND
I
ON COMMAND
SEARCH 10 HI~H
Command Code: 51 (hex) single track
D1 (hex) multi-track
KL
DL
DL
EC
2-56
(Figure 2-34)
t-I
10 SEARCHED
ON COMMAND
--.j
I I I I I I I I I I
F
c:v
NDEX
~
G'~OME
~
I----
RO FIELD-----...l
(11
~i7
KL
COU~T
DL
DL
EC
IG2GEY G2BATA G3
D~~A G4~NDEX
~
RECORD
~ FIELD~
RI
,AND ALL OTHERS FOLLOWINGI
2-57
051
HEX 31.51
71
HEX BI. DI.
FI
SET DRIVE
CNTLR INTERFACE TO READ
MODE
SEARCH
ID ROUTINE
(EO, HI, EO, AND
HI)
051
051
SET NO RECORD
FOUND IN
SENSE CONTROL
BLOCK
SET END
OF CYLINDER IN SENSE
READ 10 BYTE
FROM DRIVE
051 (04F)
SET CHNL END,
DEVICE END. AND
UNIT CHECK
GET ORIENTED
TO NEXT GAP
2 OR 3
SET CHNL
INTERFACE TO
WRITE MODE
GAP 3
GAP 2
306
051
NO
051
SEND READ
GAP 3 TAG TO
DRIVE CNTLR.
SEND READ
GAP 2 TAG TO
DRIVE CNTLR.
SET SEARCH 10
PREREOUISITE IN
R3/9 TO ALLOW
CHAINED WRITES
051 (04E)
051
051
ERRORS
POST TYPE
OF ERROR
CHECK FOR
MORE ERRORS
DURING SEARCH
051
READ C, C, H, H, &
REC NO. FROM
DRIVE AND CHNL
AND COMPARE .
306
Figure 2-34. Search 10 Equal, Search 10 High, and Search 10 Equal or High Flow Diagram
2-58
(Figure 2-35)
(Figure 2-35)
SEARCHED ON COMMAND
r=:-tJ~::lG21
'V
LJ
I
0
~~~ G4~
RECORD
I
ROFIELD----..l
~RIFIELD~
I---(AND ALL OTHERS FOLLOWING)
2-59
(Figure 2-35)
2-60
051
052 (06DI
69
HEX A9, C9,
E9
CLOCK
NEXT DATA
FIELD
SEARCH
KEY ROUTINE
(EQ, HI, EQ & HI)
SET SEARCH
KEY PREREQUISITE IN R3/9
POST TYPE
OF ERROR
052 (04E)
052
SET DRIVE CNTRL
TO READ MODE
AND CHNL IIF TO
WRT MODE
052
YES
CHECK FOR
MORE ERRORS
DURING SEARCH
052
READ 10 BYTE
FROM DRIVE
GET ORIENTATION
TO NEXT COUNT
FIELD (EXCLUDING
ROi
YES
051 (04F)
052 (041)
READ 10, CAR
HAR, FLAG, C, C,
H, H, R, KL, DL,
DL BYTES FROM
DRIVE AND STORE
IN BUFFER
052
SEND READ
GAP 2 TAG
TO DRIVE
CONTROLLER
306
READ NO OF KEY
BYTES AS
SPECIFIED BY
KEY LENGTH IN
R1/C
052
COMPARE KEY
BYTES FROM
DRIVE AND FROM
CHNL
SET END OF
CYLINDER
IN SENSE
SET NO RECORD
FOUND IN
SENSE CONTROL
BLOCK
051 (04F!
Figure 2-35. Search Key Equal. Search Key High. and Search Key Equal or High Flow Diagram
2-61
07C
PERFORM
CONTROLLER AND
DRIVE RESET
AS IF SELECTED
ASSEMBLE
SENSE BYTES
8 THROUGH 23
(PARAGRAPH 2.5.3)
INITIALIZE SENSE
CONTROL BLOCK TO
SHOW UNIT CHECK
IS OUTSTANDING
FOR SELECTIVE
RESET
07C
BRANCH TO
BASIC
WAIT LOOP
302
':l~7?
? Lnnn1 _10/7'"
2-62
YES
301 (03BI
RESET
CHECK 1
AND
CHECK 2
ERRORS
RESET INDEX
AND
SELECT
DRIVE
301
OR' BSDA
OF THIS DRIVE
INTO ACCUM
DER REG
301 (03B)
RESET INTS AND
CONTROL RST
BOTH CNTRLR
AND DRIVE
301
SET POLL
ENABLES IN
CHNL INT WORD
FOR OTHER
3 CHNLS
301
301
SET DER'S
IN CHNL INT
WORD FOR
OTHER 3 CHNLS
RESET DEO'S
FOR
RESETIING
CHNLS
301
301
301
CLEAR
SCRATCH PAD
PAGES
O-F
STORE DDW 0
AND DDW 1
BACK IN
BUFFER
DECREMENT
STRING
POINTER
301
301
GET
DRIVE
STATUS
DROP
DRIVE
SELECTION
DECREMENT
LOGICAL DRV
ADRS TO SET
ADRS = 7
DECREMENT
BSDA
3672.21 -0001-10175
2-63
2.11.1.3 AM CHECK
An AM Check is executed when the Address Mark is
missed on retry. The Address Mark error is uncorrectable. The sequence of the AM Check is the same as that
given for an uncorrectable error of a Read operation that
does not occur in a subsequent overflow segment.
2-64
071
DECODE ECC
POLYNOMIAL TO
DETERMINE
CORR PTIRN
AND DSPLCMT
SET CHNL
FREEZE AND
RESET CHNL
TRANSFER
SET
FORMAT/MESSAGE
IN SCB
SET SCB =
OP INCOMPLETE
AND
CORRECTABLE
RESET
CORRECTABLE
INDICATOR
IN SCB
SET SCB =
CORRECTABLE
071
071
071
071
071 (030)
RESET
BUFFER VALID
FOR HA, CNT,
OR KEY FIELDS
UPDATE ORIENT
REG TO REFLECT
FIELD THAT WAS
IN ERROR
RESET
R/W
CONTROL
071
071 (07G)
SET
UNCORRECTABLE
INDICA TOR AND
RESET
TRUNCATION
SET
FORMAT
= 150
UPI;>ATE
RETRY
COUNTERS
SET
CORRECTABLE
IN SCB
071
SET
COUNT
ORIENTATIO(l;
PRESENT
RETRY
STATUS
SET
FORMAT
40
071 (07E)
071
SET
DATA FIELD
IN SCB
PERFORM
OFFSET
PROCESSING
CORRECT
BUFFER
071
SET
"DOUBLE
ORIENT"
071 (07A)
SET
OP INCOMPLETE
IN SCB
SET
KEY FIELD
IN SCB
071 (03H)
GET
RETRY
SECTOR
071 (07A)
PRESENT
RETRY
STATUS
071 (07H)
LOG
ERROR
071
071 (07H)
PERFORM
LOGGING
IF
REQUIRED
PRESENT
UC ON INITIAL
STATUS OF
RETRIED CMD
071 (076)
PERFORM
ORIEIlIJATION
TO RETRY
CMD
071
SET
COUNT FIELD
IN SCB
In
2-65
073 (07G,
YES
INCREMENT
SEEK RETRY
COUNT
073
073 (07AI
SCB=/5700
OP INCOMPL
PRESENT
RETRY STATUS
073 (07AI
SENSE CTRL
BLK=/031A.
EQUIPMENT
CHECK. SEEK
ERROR. AND
PERMANENT
ERROR
r--- ---,
I
SCU
It
~
I
_ __ J
DISCONNECTS
I FROM CHANNEL
L___
073 (03E)
073 (07B)
STATUS"CE.
DE.AND UC
RECALIBRATE
START
073 (03GI
BIT SIGNIFICANT POLL FOR
DRV INTRPT
306
RST
INTRPT
073 (03A)
SEEK TO
PROPER TRACK
073 (03G)
BIT SIGNIFICANT POLL FOR
DRVINTRPT
YES
(1
TO
(2 OF 2)
TO
(2 OF 2)
of 2)
2-66
FROM
(1 OF 2)
..
073 (078)
PRESENT UNTIMED
INITSTATUS=O
. REQUEST
RECONNECTION
073 (078)
r-- --,
I
I
scu
RECONNECTS
TO CHANNEL
L.__
It
I
I
073 (078)
PRESENT
DEVICE END
073 (078)
073 (03G)
SET
ZEROTRK
ORIENTATION
073 (03G)
SCB=/OB1C
EQUIPMENT
CHECK FMT 1
NO INTRPT
FROM DRV
I
~
073 (03G
078
REQUEST
RECONNECTION
073 (071)
ORIENTTO
INDX AND
SET INDX
ORIENTATION
(1FROM
OF 2)
SAVE
CUDI STATE
CONTROL
RESET
TO DRIVE
__..J
078
SAVE
CUDI STATE
073 (03G)
CONTROL
RESET
SELECTION
TO DRIVE
078
PRESENT
DEVICE END
078
073
SCB=/OB1B
EQUIPMENT
CHECK FMTl
SEEK INCOMPL
ON RETRY
CHAINED
RESELECTION
CHAINED
RESELECTION
073 (078)
073 (078)
RETRY
CMD CHECK
RETRY
CMDCHECK
073 (078)
INIT STATUS =
UNIT CHECK
I
END STATUS
306
2-67
074 (07AI
074
SCB=/OOOB
CMD REJECT
FMTO
IMPROPER
ALTTRK
POINTER
PRESENT
RETRY STATUS
074 (306,
078
r-- - - ,
I
scu
DISCONNECTS
FROM CHANNEL
SCB=/5700
OP INCOMPL
FROM
(2 OF 2)
I t
SCU
RECONNECTS
TO CHANNEL
L _ _ _ _ .J
074 (041)
074
STATUS=CE,
DE,AND UC
r--
--1
I
__J
078
I SCU RECONNECTS I
GET RO
COUNT
ORIENTATION
TO CHANNEL
L__
078
YES
PRESENT
DEVICE END
078
SEEK TO
ALTERNATIVE
CHAINED
RESELECTION
306
074 (03G)
BIT SIGNIFI
CANT POLL FOR
DRV INTRPT
PRESENT
UNIT CHECK
FOR
INITIAL STATUS
TO
(2 OF 2)
3672.21-0001-10/75
2-68
074 (03G)
TIME OUT
FORINTRPT
OF 780 MSEC
RST INTRPT
074 (03G)
SAVE CUDI
STATE
074 (07B)
REOUEST
RECONNECT
r-I
I
I
SAVE
CUDI STATE
074 (03G)
CONTROL
RESET
TO DRIVE
-- ....
SCU RECONNECTS
TO CHANNEL
(ON INTERRUpn
L ____
074 (03G)
It
I
074 (03G)
CONTROL
RESET
TO DRIVE
074
SCB=/OB1B
EOUIPMENT
CHECK FMT1
SEEK INCOMPL
ON RETRY
074 (07B)
PRESENT
DEVICE END
074
SCB=/OB1C
EQUIPMENT
CHECK FMT 1
NOINTRPT
FROM DRV
074 (07B)
CHAINED
RESELECTION
074 (07B)
074 (05F)
PRESENT ZERO
INITSTATUS
TO
RETRY
CMD CHECK
074
(1 OF 2)
GETINDX
ORIENTATION
3672.21-0001-10175
2-69
074 (07A)
PRESENT RETRY
STATUS
NO
074 (041)
r-- --.,
I
scu
I DISCONNECTS I
I FROM CHANNEL I
L _ _ _ _ .J
GET RO
COUNT
ORIENTATION
074
074
GETRO
COUNT
INCREMENT
HEAD
ARGUMENT
NO
NO
074
SCB=/08OB
CMDREJECT
FMTO
IMPROPER
ALTTRK
POINTER
074
074
074
SCB=/5200
OP INCOMPL
END OF CYL
SET
HEAD ZERO
SCB=/5700
OP INCOMPL
SET HEAD=
HAR+l
078
NO
1>74 (03A)
SEEK (TO
DEFECTIVE
SCB=/1200
END OF CYL
+1)
306
If 2B60 Attachment Feature installed. See paragraph 3.12.
TO
(2 Of 2)
TO
(2 OF 2)
2-70
SAVE
CUDI STATE
SAVE
CUDI STATE
074 (03G)
CONTROL
RESET
TO DRIVE
CONTROL
RESET
TO DRIVE
RST INTRPT
074 (07B)
074
074
SCB={OB1B
EQUIPMENT
CHECK FMT 1
SEEK INCOMPL
ON RETRY
SCB={OB1C
EQUIPMENT
CHECK FMT 1
NO INTRPT
FROM DRV
FROM
(1 OF 2)
074 (03G)
074 (03G)
REQUEST
RECONNECTION
r--
078
I .
I
REQUEST
RECONNECTION
.-I
I
I
--...,
SCU RECONNECTS
TO CHANNEL
(ON INTERRUpn
L...__
I t
I
I
__.J
074 (078)
--,
SCU RECONNECTS
TO CHANNEL
(ON INTERRUPT)
I t
RETRY
CMDCHECK
L- _ _ _ _ ..J
PRESENT
DEVICE END
074 (078)
PRESENT
INITSTATUS
OF ZERO
074
078
078
PRESENT
DEVICE END
074 (05F)
078
PRESENT
UNIT CHECK
INITSTATUS
CHAINED
RESELECTION
GET INDX
ORIENTATION
074 (078)
078
RETRY
CMDCHECK
CHAINED
RESELECTION
306
2-71
3672.21-0001-10/75
075 (07B)
PRESENT
DEVICE
END
075 (07B)
075 (07G)
INCREMENT
DATA OVERRUN
RETRY
COUNTER
SET SCB
PERMANENT
DATA OVERRUN
ERROR
078
YES
CHAINED
RES ELECTION .
075 (07A)
RETRY
CMD
CHECK
PRESENT
RETRY
STATUS
STATUS =
CEo DE. AND UC
075
SET SCB
OVERRUN
075 (05F)
I
306
SCU - - - ,
DISCONNECTS
FROM
CHANNEL
II
t
PRESENT
ZERO INIT
STATUS
----1
L_
PAD
TO
INDEX
075 (071)
ORIENT
TO
COARSE
SECTOR
r-I
INCREMENT
DATA
OVERRUN
COUNTER
075 (07B)
FINE
TRACK
ORIENTATION
--,
SCU
RECONNECTS
AT COARSE
SECTOR
L_
I
I
_--'
2-72
..
_-
--
_._---,
YES
SET
CMD OVERRUN
ON STD IN
R2IB
NO
SET DOUBLE
ORIENT TO
OBTAIN NEXT FLD
SET
COUNT
ORIENT
075
RST
CURRENT
SECTOR
FROZEN
PAD
TO
INDEX
075 (07G)
PAD UNTIL
INDEX
AND READ
Gl AGAIN
INCREMENT
CMD
OVERRUN
COUNT
I
I
'-------.~
3672.21-0001-10175
2-73
076
RESET
CURRENT
SECTOR
FROZEN
048 (03D)
WAIT
100 pSEC
FOR INDEX
TO COME UP
PRESENT
RETRY
STATUS
ARM
PADDING
077
RESET
INDEX PASSED
INDICATOR
048 (07A)
076 (07B)
PRESENT
RETRY STATUS
077 (04A)
WAIT
48 MSEC
FOR INDEX
PRESENT
RETRY
STATUS
077 (07B)
04B
r-scu
DISCONNECTS
FROM CHANNEL
CHAINED
RESELECTION
PRESENT
DEVICE END
076 (07B)
--1
I
L.-. _
RESET
FMT WRITE
IN
PROGRESS
r-- ---,
I SCU RECONNECTS I
I TO CHANNEL I
I (ON INTERRUPT) I
L ____ ...I
I
I
I
CHAINED
RESELECTION
_ _ ....
076 (03J)
076 (07B)
READ TARGET
CTRL RSTOFFSET
RETRY
CMDCHECK
077 (07B)
04B
076 (07D)
READ
DEVICE
STATUS
PRESENT
ZERO
INITIAL
STATUS
SET UP INDICS
TO TREAT
DE AS A
DCC
076 (05F)
COARSE SCTR
ORIENTATION
PERSENT
ZEROINIT
STATUS
076 (031)
REQUEST
RECONNECT
AT COARSE
SCTR
076 (071)
FINE TRK
ORIENTATION
306
2-74
Index occurred prior to third ECC byte of Count field and after the Lock
VFO to Data Point in the gap preceding the Count field. This is caused by
writing CKD near index or when the write turnoff glitch under index
looks like a valid count field sync byte and happens to occur the correct
distance from the previous data field. The error occurs on the subsequent
read. When this error is detected, ECC is not processed.
072 (07A)
PR ESENT
RETR Y STATUS
r-I
I
I t
I
..... -- T--~
TA RGET
072 (07B)
RETRY
CMDCHECK
seTR SET TO
zERO
072 (07D)
072 (04A)
ORIENTTO
INDX. DO
NOT RST INDX
CO ARSE
SCTR
ORIE NTATION
072 (07B)
RE-ENTER CMD)
REC ONNECT
AT COARSE
SCTR
1.. __ ,
II SCU RE CONNECTS:
I
L.. _ _ ____ .J
:
072 (07B)
CHAINED
RESELECTION
072
r--
072 (07B)
PRESENT
DEVICE END
1__ -,
SCU
DISC ONNECTS
FROM CHANNEL
. . - Index occurred between the Lock to VFO Point and the Source ID Byte of
the Data field because the Data field is being clocked at a virtual position
offset to provide more channel turnaround in Gap 2 and the offset virtual
data field overlaps index.
TOC HANNEL
(ON IN TERRUPT)
t
t
In
Figure 2-45. Command Retry, Invalid Count Field Sync Detected and Index Detected in Data Field
3672.21-0001-10175
2-75
3672.21-0001-10175
2-76
OEVICE END
RECORD READ
OR WRITE
I nit i al Selection
Channel End
Disconnect
reselection delay.
revolutions.
read or written.
2-77
123
124
125
126
127
2-7R
IS
a "1".
YES
(SEE PARAGRAPHS
2.6 AND 2.8)
YES
WAIT FOR
INDX
INCR HAR
TO DRVAND
KEEP INDX
ORIENTATION
YES
SET END
OF CYL
SENSE
2-79
Search 10 (RO)
2.14.2 Formatting
2.14.1 Introduction
These segments are written using Write Special Count.
Key, and Data commands. The sequence IS as follows
(letters refer to corresponding tracks of the record):
Overflow Records allow logical data records longer than
one track to be read or written on the disc. Format
writing of an overflow record is controlled by the using
system. Read and nonformatting write operations are
controlled by the SCU.
Search 10 (RO)
Write CKD (4th segment)
2.14.3 Processing
Search 10 (R1)
Write Special CKD (1 st segment)
Seek Head (next track)
Search 10 (RO)
.tl
INOEX
R2-0 (SEGMENT 11
ffi
r-
~~
+[HAl R R B ~IONAL~------------------------------------------------------------------------------------------_,
EJ I
+
R1-0 (SEGMENT 21
, [HAl B
BIT 4 = 1
----------------------------~----------------------------_,
R~,~B OPTIONAL~-----------------------------8 I
__
R1-0 (SEGMENT 31
BIT 4 = 0
OPTIONAL~----------------------------------------.......------...,
R1-0 (SEGMENT 41
OPTIONAL,,-____________________________- ,
R2':"O
2-80
COMMAND
HEX
CODE
Device
Reserve
B4
Device
Release
94
FUNCTION
1
2.
3.
1.
2.
3.
ERROR TYPE
--
--
STORAGE CONTR
MICROPROCESSOR
CONTROLLER INTERFACE
L=d====d=
I
L
---r- -
CONTROLLER
--
.-------------~
CPU
DISC DRIVE
MODULE 3
DISC DRIVE
MODULE 4
PHYSICAL
ADDRESS
110001
PHYSICALa
~l~~~lESS~
101010
DRIVE D
PHYSICAL
ADDRESS
100011
~
~
t.J ______ ~
I
I
1_
DRIVE G
DRIVE E
PHYSICAL~
ADDRESS
i
~
DISC DRIVE
MODULE 1
DRIVE C
PHYSICALti}
ADDRESS
111000
DRIVE B
DISC DRIVE
MODULE 2
I
DRIVE A
CHANNEL A
CHANNEL INTERFACE
I
I
I
-1-
-- -
i
DRIVE F
PHYSICAL~
ADDRESS
011100
___
I
I
.1..~
PHYSICAL~
ADDRESS
001110
r--'-----,
DRIVE H
PHYSICAL~
I
ADDRESS
000111
______ L--1
2-81
II
3.1 GENERAL
This section describes the I/O interface between the
System/370 channel and the 3672 Storage Control Unit
(SCU). In general, this interface is characterized by the
following features:
P.O. 1,2,3,4,5,6,7
Provides for common connection and communication between an IBM System/370 block
multiplex channel and SCU.
II
1\'f
SYSTEM
370
V
~
I\J
I\r
vi
,J
-\
-V
-\
SCAN CONTROLS IN
SELECT IN
REOUEST IN
l;t
TAG IN LINES'
ADDRESS IN
STATUS IN
SERVICE IN
DATA IN
CHANNEL
BUS IN LINES:
NINE BIT POSITIONS
-I
SPECIAL CONTROLS IN
METERING IN
MARK IN 0
-\
vi
3-1
during read and sense operations when information is available on the Bus In lines.
during write and control operations when information is required on the Bus Out lines.
Status In
Signal STATUS IN informs the channel when the
selected SCU has placed status information on the Bus In
lines. The channel responds by raising SERVICE OUT
(accept) or COMMAND OUT (stack). STATUS IN remains
up until an outbound tag is generated, or until SELECT
OUT drops in an SCU busy sequence. STATUS IN must
drop so that the responding outbound tag may drop. It
cannot be up concurrently with any other inbound tag.
Service In
Signal SERVICE IN informs the channel when the
selected SCUis ready to transmit or receive a byte of
information. It remains up until the channel responds by
raising SERVICE OUT or COMMAND OUT or, during an
interface disconnect sequence, by ADDRESS OUT. The
conditions for generating SERVICE IN are as follows:
If the sequence meets the service requirements, REQUEST IN falls not more than 250 nanoseconds after
OPERATIONAL IN goes low. If the request for status
presentation is suppressible, REQUEST IN does not
remain up when SUPPRESS OUT is up. During a
suppressible operation, REQUEST IN falls at the SCU
within 1.5 microseconds after the rise of SUPPRESS OUT
at the SCU.
Data In
Operational In
during read and sense operations when information is available on the Bus In lines.
during write and control operations when information is required on the Bus Out lines.
Address In
Signal ADDRESS IN informs the channel when the
address of the currently selected SCU and disc drive has
been placed on the Bus In lines. The channel responds by
raising COMMAND OUT. The ADDRESS IN signal
remains up until COMMAND OUT is generated and must
drop so that COMMAND OUT may drop. It cannot be up
concurrently with any other inbound tag.
Select In
Signal SELECT IN extends the SELECT OUT signal from
the jumper in the terminator block to the channel. It
provides a return path to the channel for the SELECT
OUT signal.
Request In
Signal REQUEST IN indicates that the SCU is requesting
a selection sequence to present status information.
When OPERATIONAL IN rises, REQUEST IN is dropped
unless
Metering In
Signal METERING IN is transmitted over a line from all
attached SCUs and is used to condition the CPU meter
for operation. METERING IN rises and falls concurrently
with OPERATIONAL IN for any interface signaling sequence. METERING IN is not raised during the following
conditions:
between generation of Device End and acceptance of the next command during chaining,
Mark In 0
Signal MARK IN 0 is used as a marker tag to indicate that
the SCU is requesting command retry. Associated with
MARK IN 0 is the retry status. MARK IN 0 is up when
OPERATIONAL IN is up. Retry status is associated with
MARK IN O.
Address Out
Signal ADDRESS OUT informs the SCU to decode the
SCU and disc drive address on the Bus Out lines. Except
in an SCU busy sequence, the SCU responds when
recognizing the address by raising OPERATIONAL IN
when SELECT OUT rises with ADDRESS OUT still up.
ADDRESS OUT rises not less than 250 nanoseconds
after the SCU and disc drive address have been placed on
the Bus Out lines. ADDRESS OUT must be down for not
less than 250 nanoseconds before being raised for disc
drive selection. Selection of the SCU is cancelled if
ADDRESS OUT drops before SELECT OUT rises.
Except for a disconnect sequence, ADDRESS OUT must
rise only when SELECT OUT, HOLD OUT, SELECT IN,
STATUS IN, and OPERATIONAL IN are down. If HOLD
OUT is down and ADDRESS OUT rises, or ADDRESS
OUT is up and HOLD OUT drops, the SCU will drop its
OPERATIONAL IN and thereby disconnect from the
interface. ADDRESS OUT must remain up until
3-2
Command Out
Service Out
Signal SERVICE OUT IS issued to the selected SCU in
response to a SERVICE IN or STATUS IN signal from the
SCU. SERVICE OUT indicates to the selected SCU that
the channel has accepted the information on the Bus In
lines or has provided the data requested by SERVICE IN
on the Bus Out lines.
Metering Out
Signal METERING OUT is transmitted over a line from
the channel to all attached SCUs. It is used to condition
all other meters in the SCUs and disc drive modules. It is
raised whenever the CPU customer meter is recording
time. (The 3672 SCU does not use METERING OUT.)
3-3
The following two paragraphs describe the initial selection of an SCU, controller, and disc drive in terms of the
operations performed jointly by the channel and SCU to
effect the selection. Paragraph 3.3.2.1 is a simplified
description of the sequence, discussing' operation of the
channel and SCU only. Paragraph 3.3.2.2 discusses the
initial selection in greater detail by including channel
interface and microprogram operations.
the
the
adthe
3-4
\11Ilfll SS ,lUI
HlllO tlUI
SflEl'10UT
--::S
REQUEST IN
---:5
SELECT IN
--5
OPERATIONAL IN
ADDRESS IN
COMMAND OUT
STATUS IN
---s
SERVICE OUT
--S
I
SERVICE IN
~--~r----~f5~1----+-------~>
I
I
,5 I
CEo DE STATUS
~--~'~----~5~
BUS IN (9 LlNESI
~~----------~
SUPPRESS OUT
--4~5----------------------~5)'~----~~'---~
"mAC
"'''n''~
55 L '
STOP
L !~~~~~ED
STATUS PRESENTED
NOTE
DELAY
..
DATA TRANSMISSION
NORMAL
INPUT
OPERAT(ON
(CHANNEL
-------------t~~1
DELAY
ENDING SEQUENCE
CHE~KING
3-5
(C)
(C)
(CI)
(C)
(M)
(CI)
(C)
(CI)
(C)
IC)
(CI)
(CI)
(M)
(C)
(SCU)
(C)
(M)
(SCU)
The following list of events provides a detailed description of the initial selection sequence. Abbreviations are
as. follows: channel (C), channel interface (CI), and
microprogram (M). Registers listed are described in detail
in Section 6.
(C)
(C)
-OR-*
(SC,U)
(C)
(C)
Channel drops SERVICE OUT (chaining is indicated by SUPPRESS OUT being up).
(SCU)
operation.
3-6
(CI)
(C)
(SCU)
(C)
(SCU)
(CI)
(CI)
(CI)
(CI)
(CI)
(CI)
(C)
(CI)
(CI)
(CI)
(M)
(CI)
and
(CI)
(CI)
(CI)
Drop STATUS IN
(C)
(M)
COMMAND
drops
(CI)
(C)
(M)
Channel
OUT.
Microprogram
mand Out bit.
drive status
Register bit 5
Microprogram recognizes B(lND branch condition, resets CT Register bit 0 (Request In).
and sets CT Register bit 4 (Address In) and
bit 3 (Operational In). Place appropriate
device address in Bus In (BI) Register
(CI)
(M)
(C)
Microprogram recognizes setting of Command Out bit and resets CT Register bit 4
(Address In).
(CI)
Channel raises
HOLD OUT.
(M)
The following list of events provides a detailed description of the polling sequence and status presentation.
Abbreviations are as follows: channel (C). channel
interface (CI). and microprogram (M). Registers listed are
described in Section 6.
(C)
Channel stores status. raises SERVICE OUT. and drops SELECT OUT
and HOLD OUT.
.
(C)
(M)
(SCU)
(CI)
(SCU)
(CI)
(C)
(SCU)
(C)
Microprogram resets CT
Register bit 3 (Operational In).
(CI)
Truncation will set B(lNT) branch condition in microprocessor.
(M)
(C)
(M)
(C)
(C)
3-7
heads In approximately 130 microseconds Track formatting is unchanged but each record has a sector number
as well as a record address. There are 128 sectors per
track on the 367X drive, with each sector allocated a
unique sector number (00-7F hexadecimal). See Figure
3-4
The SCU can determine the sector currently under the
Read/Write heads of each of its drives. A sector counter
is contained in each drive. The counter is incremented
once every sector time period (approximately 130
microseconds) and set to zero each time the index
marker passes under the heads. The sector in which a
record falls is a function of the length of all records that
precede it and of its sequential position on the track.
Therefore, the sector location can be calculated for fixedlength records and a sector number allocated.
Two disc commands are provided for use with rotational
position sensing: Set Sector and Read Sector. Set Sector
used in conjunction with the block multiplexer channel
permits a single command-chained channel program to
be initiated for each disc operation that frees the channel
and SCU during rotational pOSitioning operations. If the
sector address of a record is known or can be calculated,
a Set Sector command can be included in the disc
channel program to cause the SCU to look for the
designated sector. Once the SCU accepts the sector
number, both the SCU and the channel disconnect are
available for another liD operation.
The Read Sector command is useful for sequential disc
processing and for write verification. When chained from
a Read, Write, or Search command, Read Sector provides
the sector number required to access the record processed by the previous CCW. This sector number can be used
to reposition the track to verify the record just written or
to read or write the next sequential record.
3.4.2.3 DISCONNECTED COMMAND CHAINING
Disconnected Command Chaining (also referred to as
multiple requesting) is used for the following purposes:
3-8
r----------------------------~5>~f--------------------------~il~--------------------~f5~----------------------~S
OPERATIONAL OUT
HOLD OUT
SELECT OUT
REQu~S T
IN
SELECT iN
OPERATIONAL IN
ADDRESS IN
r.OMMAND 0'J'
STATUS IN
SERVICE OUT
SERJICE IN
55
I
ADD~ESS
C4
CTRL CMD
CE STATUS
ILJI
BUS IN 19 CINES,
~
~~
,
I
ADDRESS C4
I
~----------~5'~-----------I--I-------,------------~f
ADDRESS C4
DE STATUS
11
~------------_7fr-~------~
5
SUPPRESS OUT
51
14-----------
t+-------------------------------
CHANNEL-INITIATED SEQUENCES
:5
DEVICE END
STATUS OCCURRED
------+0...---------- ENDING
-----------------------------------------------r--------
~If
DEVICE END
STAruS ACCEPTED
SEQUENCE
SCU-INITIATED SEOIIFNf"
NOTE
TH01S USED TO INDICATE CHECKING
OF SIGNAL LEVEL AND OR BUS CONTENT
BEFORE PROCEEDING
3-9
----I
I
~
INDEX
Channel A Example
READ/WRITE
127' 0
SCU
CHANNEL
A
WRITABLE
CONTROL
STORAGE
(WCS)
READ/WRITE
DATA
MICROPROGRAM
It
I
I
I
DRIVE
1
MICROPROCESSOR
TWO-CHANNEL
SWITCH OPTION.
..
CHANNEL
INTERFACE
---- -- -- -- -
Channel B Example
~~ CH_A_~_N_EL
___
____
CONTROLLER
INTERFACE
CONTROLLER
UJ
II
I-----.JL
Controls each operation as it IS received from
the channel. Maintains status of disconnected
command chaIRS in DCC byte in WCS. Brings up
unsuppresslble status for those drives with a bit
In the DeC byte as thelf Device End is received.
r-----------~I'~-------------------------------------.,
CCW Chain Example-Drive 6
'I
II
..
Ir-
[J
1
I [J
I
~
[J
.J
Control
servo motion
Interrupt microprogram
when seek is complete.
3-10
OPERA'IONAI OU1
If
HOLD OUT
SELECT OUT
REQUEST IN
SELECT IN
STATUS IN
SERVICE 'JUT
SERVICE IN
BUS OUT
BUS IN
DATA OUT
DATA IN
MARK IN 0
COMMAND
RETRY
INDICATION
CHAINING INDICATED
BLOCK MULTIPLEX OPERATION
(DATA IN/DATA OUT TRANSFER)
3-11
When multiple channel programs are. operating concurrently in the block multiplexing mode, a device can
regain control of the channel only when the channel is
not busy. Therefore, only cyclic devices, such as the
367X Drive with RPS, can disconnect during execution of
a command-chained channel program on a block multiplexer channel and resume ,operation later.
OPERATIONAL OUT
AOORESS OUT
HOLD OUT
SELECT OUT
REQUEST IN
SELECT IN
OPERATIONAL IN
ADDRESS IN
COMMAND OUT
STATUS IN
SERVICE OUT
SERVICE IN
BUS OUT
BUS IN
SUPPRESS OUT
DATA OUT
DATA IN
MARK IN 0
3-12
NOTE
Data chaining "capabilities are
dependent on several variable
factors, such as system type, I/O
configuration, and channel
loading.
Because
of
these
dependencies, Read or Write
data chaining within record
areas may cause unpredictable
overruns or chaining checks.
Refer to the FIPs volume if these
conditions are encountered or
suspected.
3.5.7 Disconnect In
The DISCONNECT IN Signal enables the SCU to alert thE.
system of a malfunction that is preventing the SCU frolT'
signalling properly over the I/O interface. In response to
DISCONNECT IN, the channel performs a Selective
"Reset.
3-13
When the command being executed encounters a condition requiring retry. the SCU indicates this requirement
by raising STATUS IN while presenting Unit Check.
Channel End. and Status Modifier (MARK IN 0 being up
for retry status)
3.5.11 Proceed
At any time other than during a channel-mitiated selection sequence. proceed is indicated whenever COMMAND OUT responds to ADDRESS IN. It causes the SCU
to continue the normal servicing sequences on the
interface.
3.6.1 Overview
When requested by the channel, status information
about the subsystem is transferred to the channel by
means of the Test 110 command. This command is
generated by the channel as a result of the Test 110
instruction, or as an internal channel function when the
channel requests status.
DEVICE
STATUS BYTE,
BIT POSITION
2
3
4
5
6
7
32
33
34
35
36
37
38
39
3.6.2.3 BUSY
PARITY
A TIENTION (NOT USED)
STATUS MODIFIER
CONTROL UNIT END
BUSY
CHANNEL END
DEVICE END
UNIT CHECK
UNIT EXCEPTION
A previously initiated operation is being executed. An operation is being executed from the
time initial status is accepted until Device End is
accepted.
Status conditions exist. The condition's accompany the Busy indication. If the Busy indication
pertains to an SCU function, it is accompanied
by Status Modifier.
DESIGNATION
CSW
BIT
3-15
NOTE
The ending interruption condition
can be cleared by Test 110
without generation of Unit Check
if a disc drive becomes not ready
on completion of a command.
3-16
DESIGNATION
Command Reject
Intervention Required
Bus-Out Parity
Equipment Check
Data Check
Overrun
(not used)
(not used)
Conditions that occur during the execution of an instruction command sequence are reported as channel status
and as sense information. Sense information defines
conditions that occurred in the SCU, controller, and disc
drive that are not defined in the status. This sense
information is .obtained by executing a Sense command.
Information concerning the actual state of the SCU,
controller, and disc drive; and unusual conditions
detected in the last operation, are provided by data
transfer during a sense operation. It may describe
reasons for the Unit Check indication of a status byte
and, for example, may also contain an indication that the
susvstem is in the not-ready state.
BIT
3
4
5
6
7
Command Reject-Bit 0
This bit indicates that the command cannot be performed
for any of several reasons. Typical examples are listed
below:
@;
Sequence of commands or the protected conditions has been violated. For example, a Write
command was received which the subsystem
cannot execute because the command violates
the file mask.
Intervention Required-Bit 1
Bus-Out Parity-Bit 2
Overrun-Bit 5
Equipment Check-Bit 3
3672.21-0001-10175
3-17
@]
1. After checking for CBR, the microprogram executes an RD = BI statement and loads a byte
into Buffer A. The Transfer Control Hardware
places this. byte - on the Bus In lines to the
channel and raises DATA IN. Because one
buffer now contains a byte of data, the
Q.EMPTY branch condition is reset in the
microprocessor.
3.S.1 Description
This paragraph provides a simplified block diagram
description of the Read Data Transfer operation.
Paragraph 3.8.2 provides a flowchart of this operation.
The alphabetical keys adjacent to lines of the block
diagram in Figure 3-7 are keyed to the text material
below.
DATA
FROM
DRIV E
INTER
FACE
I (J
JI
1
MICROPROCESSOR
I
~
.1
1. Before entering the Read Data Transfer sequence, the Channel Buffer Ready (CBR) and
the Queue-Empty (Q.EMPTY) branch conditions
in the microprogram are -set by Channel
Transfer bit 0 in the CHC Register being down
or reset (paragraph 6.2.2.5).
I
I
I
=0 latch
cc =
0
LATCH
I
I
MULTIPLEX
CHANNEL
1
1
1
(]0
a.EMPTY
(]~
RD = BI
(Q)
I
TRANSFER
CONTROL
HARDWARE
I
(J@
@
DATA
IN
I SERVICE
IN
I
I
I
1~0
1
CC
REGISTER
!
I
I
!
I
I
CHANNEL TRANSFER BIT AND
CHANNEL WRITE BIT
BUS
IN
~-
BUFFER
B (BII
CBR
@J01
lID
BUFFER
A (BII
CHC
REGISTER
L ______ J
I
I
[[]
[]
DATA TRANSFER
Data is transferred to the channel by the Transfer
Control Hardware alternately raising DATA IN and
SERVICE IN to transfer successive bytes. Each time
a byte is transferred, the CC Register is
decremented to show how many bytes remain to
be transferred to the channel.
[J
@]
SENSE COMMANDS
[J ,
3-19
(CI)
~ (M)
1M)
Il PR O G
LOAD CC:
REG
(CI)
tIM)
(CI)
0 BRANCH CONDITION
(CI)
CC
OR
CC
IS
BEING
RAISE SERVICE IN
AND SET BYTE IN
BFR B ON BUS IN
~(M)
DECR CC
REG AND
SET
Q-EMPTY
1M)
(M)
TO
TO LOAD BI REGISTER
(M)
(CI)
(2 OF 3)
(M)
IlPROG
SET CHAN
XFER AND
CHAN READ
......__- - - - - (C)
(CI)
(C)
(C)
(M)
WAITS
FOR
3-20
FROM
(1 OF 3)
I
'RAISE DATA
IN AND
SET BYTE
IN BFR A
ON BUS IN
....I--+-- (el)
......Ir------ (el)
TO
(3 OF 3)
YES
>4"'_-1-__
(el)
....Ir------ (el)
I'PROG
LOAD BFR
B AND RESET
CBR
DECR CC
REG AND
SET CBR
.....~--- (M)
......1 - - - - -
....1 - - - - - - - (M)
....1 - - - - - ' - - -
(el)
.>04------
(el)
'----r----'
(el)
TO
(1 OF 31
">0.----
(el)
(M)
......Ir------ (el)
TO
1----1.
(3 OF 3)
3-21
FROM
(1 OF 3)
~--+--- (e)
~-+---
(M)
(~)
(M)
YES
YES
TURN OFF
CHNL XFER
~~------------------r-------------------
TURN OFF
CHNL XFER
(M)
(el)
~~--------- (M)
MICROPROGRAM RESETS CHC REGISTER BIT 0 AND TERMINATES TRANSFER. HOWEVER, THE PROGRAM WILL CON
TINUE READING WITH NO TRANSFER TO THE CHANNEL TO
CHECK DATA VALIDITY.
~ .....- - - - - - - - - - - - - - - - - - - ; - - - - - - - - - - - - - - - - -
COMMAND
RETRY
DATA OVERRUN
I.~
__- - - - - -
(el)
(M)
(el)
(M)
(el)
3-22
[[]
I
I
BUS OUT
0 I
0
10
TO A BUS
f
SERVICE IN
TRANSFER
CONTROL
HARDWARE
(]00
I
I
a.EMPTY
[)
RA BO
t t
cc
REGISTER
CHC
REGISTER
I
I
CBR
I
I
CC
0 LATCH
0@
I
I
I
0
@
I
I
L _ _ _ _ _ _ _ _ _ _ _ _ --.J
(Q)
@)~
I
I
I
'---
DATA IN
MULTIPLEX
CHANNEL
BUFFER
BIBO)
rn:J
BUFFER
AIBO)
MICROPROCESSOR
...
[]
3-23
[8]
[IJ
3-24
FROM
(4 OF 4)
t'PROG
LOAD CC
REG AND
RSTCC=O
LATCH
RST CBR
BRCH
CONDITION
(CI)
(M)
(CI)
(M)
(CI)
RAISE
DATA IN
(M)
t'PROG
SET CHNL
XFER AND
CHNL WRITE
BITS
FROM
(3 OF 4)
(el)
(C)
DATA OUT IS THE NORMAL CHANNEL RESPONSE AND INDICATES A BYTE OF DATA IS AVAILABLE ON BUS OUT
DROP
DATA IN
SET
BYTE
IN BFR A
INTO BO
REG
RAISE
SERVICE
IN
(CI)
(CI,
(el,
(el,
(M)
(e)
(M)
NO
DECR
CC REG
SET CBR
AND LOAD
BYTE ON
BUS OUT
INTO BFR A
III
(M)
(M)
(M)
(CI)
(el,
3-25
FROM
(1 OF 4)
FROM
(3 OF 4)
DROP
SERVICE
IN
SET BYTE
IN BFR B
INTO BO
REG
....1 - - - (el)
, ........- - - leI)
~------- (e)
' - - - - - (M)
.....1 - - - - + - - - - - - - - (el)
1------+-------1..-
YES
DECR
CC REG
YES
'--_ _ _ _ lei)
NO
SET CBR
AND LOAD
BYTE ON
BUS OUT
INTO BFR A
RAISE
DATA
IN
NO
=0
....F - - - - (el)
AFTER CHECKING CC
, - - - - - (M)
(M)
TO
(3 OF 4)
TO
TO
(4 OF 4)
(4 OF 4)
3-26
FROM
12 OF 4,
FROM
., OF 4
FROM
14 OF 41
r - - _......._-""
DROP
DATA'
IN
SET BYTE
IN BFR A
INTO BO
REG
RAISE
SERVICE
IN
(CII
(CI)
(CI)
CC
0 INDICATES THAT REQUESTED NUMBER OF BYTES HAS
BEEN ACCEPTED FROM THE CHANNEL
(ell
(CI)
DROP
SERVICE
IN
(CI)
DECR
CC REG
(CI)
(CI)
(M)
(C)
LOAD
BYTE ON BUS
OUT INTO
BFR B
MICROPROGRAM USES RA
BO STATEMENT TO TRANSFER
DATA FROM BO REGISTER TO DO REGISTER SO THAT IT CAN BE
SENT TO DRIVE CONTROLLER.CBR BRANCH CONDITION IS
RESET.
(M)
3-27
FROM
FROM
C (1 OF
G (2 OF
K (3 OF
N (3 OF
Q (4 OF
B (1 OF 4)
F (1 OF 4)
I (2 OF 41
'----+---- (M)
MICROPROGRAM USES RA
BO STATEMENT TO TRANSFER
DATA FROM BO REGISTER TO DO REGISTER SO THAT IT CAN BE
SENT TO DRIVE CONTROLLER CBR BRANCH CONDITION IS
RESET
' - - - - - - - - (e)
DATA OUT IS THE NORMAL CHANNEL RESPONSE AND INDICATES A BYTE OF DATA IS AVAILABLE ON BUS OUT
LOAD BYTE
ON BUS OUT
INTO BFR A
.........- - - - - (el)
DROP
DATA
IN
....~----- (el)
HARDWARE DROPS
/lPROG
SET CHNL
FREEZE
4)
4)
4)
4)
41
INHIBIT
DATA IN
AND
SERVICE IN
.~.....- - - - (el)
/lPROG
UNLOADS
DATA FROM
BUFFERS
.....1 - - - -
(M)
/lPROG
TURN OFF
CHNL XFER
AND CHNL
WRITE
....~--- (M)
MICROPROGRAM HALTS ALL FURTHER TRANSFER BY RESETTING CHANNEL TRANSFER BIT AND CHANNEL WRITE BIT IN CHC
REGISTER
.....t - - - -
(M)
'~"'''---------------(M)
........~-------------+----(M)
~------
(ell
BEFORE
~------- (M)
BE
TAKEN
BY
ERROR
RECOVERY
(el)
' - - - - - - - - (M)
VALIDITY
(el)
DECR
CC REG
DATA
DURING A WRITE
FOLLOWING:
OPERATION,
Q-EMPTY
INDICATES THE
3-28
OPERATIONAL IN UP
COMMAND OUT UP
ADDRESS IN UP
=------1==;:====1
DISCONNECT IN UP
INHIBIT
DISCONNECT
LATCH
SELECT RESET UP
START
00~
OPERATIONAL IN UP
POWER ON RESET
ANY
SCU
OPERATIONAL
IN UP
NOT ANY
OPERATIONAL IN UP
YES
CHECK 1 UP
~Jo
SCU RAISES
REQUEST IN
TO r:HNL
CHNL RAISES
CMD OUT
SCU RAISES
DISCONNECT
IN AND DROPS
ADDR IN
SCU PERFORMS
SELECTIVE RST
AND DROPS
DISCONNECT IN
AND OPERATIONAL
IN
CHNL RAISES
SEL OUT AND
HOLD OUT
SCU RAISES
OPERATIONAL
IN AND DROPS
REQUEST IN
CHNL INITIATES
A SELECTIVE
RST
I
SCU RAISES
ADDR IN
AND PLACES
ADDR ON
BUS IN
[]
SCU RAISES
DISCONNECT IN
CHNL INITIATES
A SELECTIVE
RST
@]
S(,_ PERFORMS
SELECTIVE
RST AND DROPS
DISCONNECT
IN AND
OPERATIONAL IN
SELECT
OUT LATCH SET
SCAN A UP
ADDRESS IN UP
MACHINE RESET
COMMAND OUT UP
Channel initiates a selective reset by raising SUPPRESS OUT and dropping OPERATIONAL OUT.
Channel initiates a selective reset by raising SUPPRESS OUT and dropping OPERATIONAL OUT.
SCU performs selective reset and drops DISCONNECT IN and OPERATIONAL IN.
drops
Figure 3-11. Check 1 Error Controlling Sequence Flowchart and Logic Diagram
3-29
Ending status associated with an interface disconnect has not been accepted by the channel.
NOTE
The last status byte was part of a channelInitiated signal sequence and was stacked by
the channel.
c. Execution
procedure.
of
an
SCU
error
recovery
3.11.5 Addressing
The base address (four high-order bits for 16-spindle
configuration, three for 32-spindle configuration) of the
storage control on one channel is independent of the
base addresses on the other channels. However, the
three low-order address bits for any attached device
must be the same on all channels.
3.11.6 Resets
System Reset clears all reservations and status conditions stored in the SCU for the resetting channel,
terminates all block mUltiplex command chains in
progress on the resetting channel, and resets all device
interrupts not associated with the other channels. The
reset may be initiated by any channel at any time.
Reservations, status, and device interrupts for the other
channels, as well as block multiplex chains in progress
on the other channels, are not affected. If a channel
initiates a System Reset while the selection logic is
connected to another channel, a Machine Reset is
performed when the selection logic goes to neutral. A
Selective Reset has no effect on device reservations or
status.
3-30
SELECT A
l;[
NlllAl HESE T
I'HIOHITY WINDOW A
ICP REGISTER BIT 7)
CASOI
FFINOTSET = D INIT IAl Sf LECTION B
SELECT B
SELECT C
SELECT A
SELECTC
SELECT D
FFI
FF1SET=D-
SCAN A
SCAN B
SCANS A THROUGH 0 CONTROL GENERA
TION OF SHORT SCU BUSY SEQUENCE
AND PROPAGATION OF SELECT OUT.
GENERAL RESET
PRIORITY WINDOW B
(CP REGISTER BIT 6)
FF1NOTSET = D -
SELECT A
SELECT B
FFI
CBSOI
FF2
SCAN C
FF2 SET
TO CI REGISTER
BIT6ANO
SCAN LOGIC
INITIAL SELECTION C
FF1SET=D-
SCAN 0
FF2 SET
SELECT C
SELECT D
SELECT C
FFI
GENERAL RESET
SELECT B
SELECT A
FFI
PRIORITY WINDOW C
(CP REGISTER BIT 5)
CCSOI
CI REGISTER - BIT6
SELECT B
SELECT 0
INITIAL SELECTION 0
r-_
106
SELECT 0
FF1
SELECT A
SELECT B
GENERAL RESET
PRIORITY WINDOW D
(CP REGISTER B(T 4)
CHC REGISTER
BIT6
TO CI REGISTER
BIT 7 AND
SCAN LOGIC
COS01
CI REGISTER
BIT 7
SELECT C
SELECT 0
_-,--_r-_
ANY OPERATIONAL IN UP
LOCK CHANNEL SWITCH
(CHC REGISTER BIT 4 SET)
ANY OPERATIONAL IN UP
ANY SCU SHORT BUSY
SEQUENCE IN PROGRESS
SCU BUSY
(CHC REGISTER BIT 3 SET)
3-31
Seek
Set File Mask
Set Sector
Search
Write
Set Sector
Search
Read
in
detail
these
3-32
Figure 3-13
10
11
3670 State
IS
SET RPS
NO
-=
Definition
No such state
OBTAIN RPS
STATE BYTE
FROM
CHANNEL
Bits 6. 7
Operation
00
COUNT-One
01
NO
304
SET
INVALID
COMMAND
036
SET
STATE 1
SET
CMD REJECT.
INVALID DATA
078
3672.21 -0001-10175
3-33
Sense
Reconnect Sequence
Write
Search
All search command operations are unchanged.
~n7221
-0001-10175
e. SCU detects poll and performs selection sequence with channel using the device address
of the lowest logical numbered drive in the DCC
state.
g. SCU disconnects from the channel and maintains the DCC state of the drive. The stacked
status state is not entered because the "Device
End pending" from the drive interrupt is unchanged.
h. SCU enters the wait loop and raises Request In
when a drive interrupt is present at one or more
of the drives.
j.
Reconnect Status
The operation of these commands is not affected by the
RPS mode of the SCU. They do not present disconnect
status.
3-34
Disconnect Status
Reconnect Sequence
The reconnect sequence for a command retry disconnect
IS similar to that of a normal disconnect. After the Set
RPS command with state code byte indicating state 3 is
processed, the error recovery sequence is continued as
below:
a. DE status is accepted by the 2860
b. SCU enters a pseudo reconnect wait loop. This
is equivalent to the UC contingent connection
wait loop.
c. SCU receives the Set RPS command for command retry reconnect and presents CE, DE
ending status.
d. SCU receives chaining indication from the 2860
and enters the chained reselection loop.
e. SCU receives the retry command and enters the
command retry procedure to perform the retry of
the command.
f. SCU continues the channel program.
g. 2860 continues the channel program.
3672.21-0001-10/75
3-35
3672.21-0001-10175
3-36
SECTION 4. MICROPROGRAM
4.1 MICROINSTRUCTION
4.1.1 General
The microprogram controls the operation of the 3672based subsystem and is permanently stored on a flexible
disc. Immediately after power has been applied to the
subsystem. the microprogram is read from the flexible
file. and stored in writable control storage (WCS).
The following paragraph contains a description and
format of a microinstruction. and a description of
decoding and translation of a field within a microinstructi<?n. Also presented is a layout and definition of a
microinstruction word in the microprogram. and a
microprogram subroutine example. In addition. a chart
depicting the various routines within the microprogram is
included.
the
contents
of
the
4-1
a. FORMAT 0 MICROINSTRUCTIONS
Word Bit Position
Fields
/ 0
2131
FMT
FIELD
/ 6
10
11
12
13
14 1 15 1 16 1 17 1 18
19
20
Specifies register to be
multiplexed onto A Bus
Specifies register to
be loaded from 0 Bus
21 1 22
23
1 24
/ 25 / 26
27
1 28
29
30
31
32 1 33
Provides constant to be
set into register specified
by C field
Specifies
ALU operation
Specifies register
destination of constant
contained in X field
b. FORMAT 1 MICROINSTRUCTIONS
o 1
o I
21
10 1 11
12
13
1 14
1 15
16
17
18
1 19
20
1 21 1 22
23
1 24 1 25 J
26 1 27
28
/ 29 1 30 1 31
FMT
FIELD
..
"
BA
BC
I
..
..
SpeCIfIes condItIons
which if satisfied, will
cause the microprogram
to branch
c. FORMAT 2 MICROINSTRUCTIONS
Word Bit Position
Binary Word Format
o /
1 32 1 33
2/31
FMT
FIELD
/5/6
CL
1 10 / 11
12 /
13 1 14 1 15 1 16 1 17 1 18 1 19
..
SpecIfIes control
functions: transfers,
increment, shift,
reset, etc.
20. 1 21 1 22
23 1 24 1 25 1 26
BA2
27
28
29
30
BC
1 31 1 32 I
33
BA
"
d. FORMAT 3 MICROINSTRUCTIONS
Word Bit Position
1 '1
21
1516
18 J
101 11
12 1 1a
14 1 15 1 16
17
1 18 1 19 1 20 1 21 1 22
23 l24 1
25
1 26 J
27
28 1 29 1 30 1 31
1 32 1 33
FMT
FIELD
..
Same uses as Format 0
BA3
BC
BA
I
Specifies register
to be multiplexed
onto B bus
Specifies ALU
operation
Same'uses as Format 2
4-2
TABLE 4-1
FIELD
CONTENTS
(HEX)
FIELD NAME
00
GO
CL
BC
G03
B (BRO)
C (G03
=R03)
= R03.INC)
01
CI
Gl
+C
CT
Rl
B (BR1)
C (BUF
02
CHF
G2
+1
CHC
R2
B (BR2)
C (CC = R23)
03
BO
G3
BI
CO
B (BR3)
C (DTC = R23)
04
G5
G5
DO
B (BR4)
C (SR
05
G6
G6
CT
B (BR5)
C (BUF
Write data from R03 into buffer at address specified by BAR pnor
to its being loaded from G3. High BAR IS not modified
SW
MD2
PS
B (BR6)
C (BUF = R03)
Write data from R03 IOta buffer at address specified by BAR BAR IS not modified.
06
= R23)
= R02.LD)
B (BR7)
Branch if BR7 is set.
No Operation
C(NONE)
L
CNT
~------~~------r---------~---t----~--------~------~---B--(O--_-O-)------------------------------------------------------1---------------------------------------------------------------1
07
CS
08
CCK
09
SFD
OA
ECR
DB
RWC
RWC
DC
01
SP
Branch if 0 Bus
MCM
SEE ALU
FUNCTION
CODES
-B (0 =0)
FDC
$$$
=zero.
C (R03
B (0
= FF)
8ranch if 0 Bus
-B (0
=FF)
No branch if 0 bus
B (CARRY)
= FF (hex).
=FF (hex)
BUF)
C (R03 = BUF.INC)
C (R03 = BUF.LD)
Transfer BUF 10 R03 and then transfer G3 to BAR. High BAR IS nol modified.
C (RESET.INDX)
C (CH.FREEZE)
00
CT
FOD
-B (CARRY)
C (RESET.K)
DE
CO
CO
-B (COMPARE.EQ)
C (RESET. CKS)
OF
DO
DO
B (COMPARE.HI)
C (READ.CS)
10
RO
G400 ,
RO
B (INT)
Branch
on
selected
interrupt
true.
Controlled
by
IMK
Register.
C (RESET.DBR)
11
Rl
Rloo
Rl
-B (lNT)
Branch
on
selected
interrupt
false.
Controlled
by
IMK
Register.
12
R2
RWoo
R2
13
R3
R300
R3 .
14
INT
INToo
IMK
15
G4
ROoo
G4
B (CNT = 0)
-B (CNT
= 0)
B (LD.SR.
* +1) LOW
16
G7
G700
G7
17
PS
000
PS
C (D. EVEN)
Generate even panty for the 0 bus for the present micrOinstructIOn
C{LO.SR.*+l)
C (BAR
C (BAR = G3)
NOT USED
B (ILACT)
FO Interface
1)
C (CLOCK.DTC)
B (DBR)
In
C (BAR
= G23)
C (G23
= BAR)
~-------4--------~------~~SELBY---+--------~--------~-------------------------------------------------------------~--------------------------------------------------------------~
18
GO
19
G2
CHFoo
PS BITS
ON BR
BUS
lA
lB
TR
-B (DBR + INT)
GO
No
+C
If
DBR
or
the
selected
Interrupt
is
true
CNT
B (Q.EMPTY)
Branch when channel buffers A and B are available for new data
R03
B (NO. BRANCH)
No branch
C (R23
C IR23 = CC)
C (WRITE.CS)
B (LD.SR.
* +1) HI
lC
Gl
G3
G3
B (UNCOND)
lE
CNT
TR
B (D. BUS)
lF
CP
CP
B (ADR
NBROO .....
Gl
C IR03 = G03)
10
0100
= ADD
= ADD
NOT USED
B (CBR)
= SRI
Branch
branch
G2
to
microinstruction
address
address
obtained
from
developed
SR
= SRI
by
Register
NOT USED
C (SPECIAL)
o BUS
567
+1 0. ADD WITH CARRY
- LOGICAL AND
v
*
0
0
LOGICAL OR
EXCLUSIVE OR
K. = COMPARE
L - SHIFT "A" LEFT
= 000 .
001 .
010 '
011 .
100
Not used
NOI used.
ILACT (set ILACT)
ILACT. OFF (reset ILACT).
Not used
4-3
INPUT TO
B MUX
FORMAT 0
INPUT TO
F MUX
BRANCH ADRS
TO ADRS REG
MICROPROCESSOR
CONTROL FIELDS
_,,~oo,
MICROINSTRUCTION
FIELDS
P-~~--~~--~--~~~--~--~~'
INPUT TO
B MUX
FORMAT 1
INPUT TO
F MUX
BRANCH ADRS
TO ADRS REG
MICROPROCESSOR
CONTROL FIELDS
,_,~oo,
MICROINSTRUCTION
FIELDS
FORMAT 2
~~~~-.------~~--~~--~
INPUT TO
B MUX
INPUT TO
F MUX
INPUT TO
B MUX
INPUT TO
F MUX
BRANCH ADRS
TO ADRS REG
MICROPROCESSOR
CONTROL FIELDS
TRANSLATION
MICROINSTRUCTION
FIELDS
FORMAT 3
BRANCH ADRS
TO ADRS REG
MICROPROCESSOR
CONTROL FIELDS
TRANSLATION
MICROINSTRUCTION
FIELDS
4-4
4.2 MICROPROGRAM
Reset Procedure
The machine hardware is Initially reset to the power-on
reset state. The microprogram is then loaded (IMPL)
starting at the IMPL address, or restarted (Selective
Reset and System Reset) at location 000. IMPL starts a
new microprogram with the Writable Co'ntrol Storage
(WCS) and buffer storage in the reset state. General
Reset only resets the devices allocated to the channel
initiating the General Reset command. Selective Reset
only resets the particular operation in progess.
bytes fa: '1 equal, high, or high equal state. The section
then transfers the status of the comparison to the
channel
Write Commands
Command Decode
Command Decode can be entered from File Status
Analysis, or from Chained End Procedure. When entering
from Chained End Procedure, the time through command
decode is taken up in the gaps. Command Decode checks
the validity of the command, checks that the proper
sequencing has occurred prior to execution of the
command, and sets up the command indicators required
to process the command.
Sense Commands
Four Sense Commands accept sense information from
various locations in the Buffer Storage and send the
information to the channel for analysis. A hardware
channel transfer is used to switch DATA IN and SERVICE
IN when transferring the sense bytes.
Control Commands
The Control Command section is not directly involved
with transferrring data from the 3670 file. This section
moves the access position, reads and sets the sector
values, receives the file mask from the channel, and
spaces across bad count fields.
Read Commands
Search Commands
Search Commands section accepts bytes from the Controller and from the channel. The section compares the
Diagnostic Commands
The Diagnostic Commands section controls the in-line
microdiagnostics from the CPU. The section also enables
the 367X Fault Isolation Detection System to evaluate
the test results.
Error Processing
The Error Processing section handles all retryable errors
and error analysis. The retryable errors are: (1) ECC
errors, (2) Seek Incomplete, (3) Defective and Alternate
track errors, (4) Retry pading, (5) Sync check, (6) AM
check, (7) Index Continue, (8) Offset before Write, (9)
Command Overrun, and (10) Data Overrun.
Diagnostic Monitor
The util.ization of all microdiagnostic tests is accomplished through the resident SCU Diagnostic Monitor
section of the Microprogram. The Diagnostic Monitor
interfaces with the functional Microprogram and with the
microdiagnostic required to perform a specific test.
Microdiagnostic
The Microdiagnostic routines are loaded into the CPU
from the Flexible Disc, and then transferred to the WCS.
Execution of a microdiagnostic is initiated by a Diagnostic
Write Command. The microdiagnostics test the SCU,
Controller, and the Disc Drive sequences; and monitors
any errors which may occur. The errors are stored in the
sense bytes for analysis by the Error Recovery Procedure
(EREP) or the Field Engineer (FE).
4-5
BLOCK IDENTIFIER
LOCATION OF
SAME AS FORMAT 0
FORMAT 1
MICROINSTRUCTION
SUBROUTINE BLOCK
SUBROUTINE
NAME
--RETURN
1
ADDER]
~~
L: :
A-:-:-:-D-N--TT-I-O-N
ADD
A~~
ALWAYS ON LINE
4
BRAN CH
ADDRESS
LABE
B L K - - LIN E O P - - - BRA D D
BLK-LI
NE-B-ADDR
8
9
OF
SUBROUT IN
FORMAT 0
SAME AS FORMAT 0
LOCATION OF
FORMAT 0
LAB E L
A
S TAT E MEN T
TBU
STATEMENT
~~TRR6~N~~~~6i~~..N.O,_F_ _ _6
B L K --
ON A PAGE
17 CHARACTERS
MAXIMUM
COMMENTS
R/~:::::::::N'
3
d 0
3
4
LOCATION OF
MICROINSTRUCTION
FORMAT 2
IS ALWAYS ON
LINE 4
1
2
A::E:TATEMENT
;~~~~~~~T~(~~~N._T~IS~____-4~~~ CON T R 0
5
7
o
AD;}R
S TAT E MEN T
CONDIT ION
ADDRESS
ABEL
BRANCH
BRANCH
~~~~~~
OR
~AOOA
8
",-",ANOHAOOR'"
SAME AS FORMAT 0
FOR ENGINEERING
PURPOSES ONLY
OPERATION CODE.
DENOTES FORMAT
0,1, 2,OR 3.
SAME AS FORMAT 0
ADD R
A L U
ALWAYS ON LINE 4
ALWAYS ON LINE 5
5
6
7
8
9
Figure
S TAT E MEN T
3
4
B, R A. N. C H
B R A N C H
L K--L I
0 M MEN
J
/
FORMAT 3
LOCATION OF
MICROINSTRUCTION
STATEME,NT
ADDRESS
LABEL
~:~OOR
-
SAME AS FORMAT 0
4-6
EF
GO with
'~
r-----~..........
Indicates a Subroutine
7f~ro
Lrl
' - r - - - - - 003
Rl=Rl. /EF
;--------i
G5=O.GO
B(LO.SR. "1)
O4AINOEXl
B3--011-3--ooo
CLR ERROR REG.
GO GET INDEX
ORIENTATION.
B2--OO8-1-- 003
RESET INDEX
PASSED IN OP STAT 1.
I N O E x . l - ! - 004
SUBROUTINE O4A
84--014-B
'
--004
..
~i _ _ _ _ _ _
~
-8(0=0)
ERROR
01-015 3 - - 000
BR IF SUBRTN ERROR
(:
Indicates a Subroutine.
"'HA\
r-----+-OO~
lB
G50 G
:G
- s - 1 SUBROUTINE 05F
:
0
B(LO.SR..I)
05FHA
02---017-3
CLR ERROR REG.
GO TO LOAD CNTS
-B(CNT=O)
.
03-019-B
'/0
05-022--0-- 000
SET GO FOR CHNL
XFER IN 040.
"'AOJ TIMER'"
,------009
r-----7<-----DOA
Indicates a Subroutine
ERROR
SUBROUTINE 04F
B(LO.SR. "1)
O4FERROR.ASMB
H2--OO3-3
ASSEMBLE ERRORS.
H3--OO5-B
4-7
t----<
r--t-'
SENSE
COMMANDS
I-- t--<
r-
r--
DIAGNOSTIC
MONITOR
I
I
r-----
r----<
MICRO
DIAGNOSTICS
CONTROL
COMMANDS
1
~
READ
COMMANDS
t--<
L.-..
BASIC
WAIT
LOOP
f-----
FILE
STATUS
ANALYSIS
COMMAND
DECODE
r-----
INITIAL
STATUS
PR ESENTATION
r-t-- r
--~
I--- 1--1
..........
I-- r-
I-SEARCH
COMMANDS
r-- ~
J
~
GENERAL
RESET
SELECTIVE
RESET
WRITE
COMMANDS
I-- ~
RESET
PROCEDURE
UNCHAINED
END
PROCEDURE
ERROR
PROCESSING
ENDING
STATUS
PRESENTATION
CHAINED
END
PROCEDURE
I""-
I-DIAGNOSTIC
COMMANDS
IMPL
J
Figure 4-5. Microprogram Routine Organization
4-8
Oc=)
JACKET
Figure
5-1
5.2 SPECIFICATIONS
3.5 kilobits
30 kilobits
1.4 megabits
1.5 megabits
Rotational Speed
Single Track Access Time
Data Transfer Rate
375 rpm
20 msec
200 kilobits/sec
Disc Characteristics
Number of Tracks
Recording Density
50
2400 bits per inch
(inside track)
Recording Mode
Frequency
tion
8
1
modula-
AC Power
110 10% volts
50/60 Hz, single phase
0.75 amperes
DC Power
+5 0.10 volts @ 0.6 amps, 50 mV ripple
-15 0.30 volts @ 0.12 amps, 50 mV ripple
*-12 0.25 volts @ 0.12 amps, 50 mV ripple
+24 1 volts @ 2.0 amps, 100 mV ripple
The 650 can be damaged by improper servicing, handling, or operating techniques. The following procedures
should be observed to properly operate and maintain the
650.
5.3.4 Safety
AC and dc power are controlled by the SCU. Before
working on the file, verify that all power is removed from
the 650.
KEYING
NOTCH
CARTRIDGE
GUIDE
5-3
.....
/
I
I
I
I
I
READ HEAD
I
SCU
MICRO
PROCESSOR
.....
FLEXIBLE
DISC
INTERFACE
CONTROL,
STATUS,
AND
READ
LOGIC
LOAD HEAD
HEAD
POSITION
ACTUATOR
I
I
I
I
HEAD POSITION ACTUATOR CONTROL
I
650 FLEXIBLE DISC FILE
-~
5-4
SOLENOID
(ENERGIZEDI
LOAD ARM
RETURN
SPRING
CARRIAGE
I
I
'
---=:J~~~_
SEP DATA
READ HEAD
-SEP CLOCK
DETECTOR
-STEP OUT
INDEX/SECTOR
ACCESS HOLE
-STEP IN
TRACK 00
TRACK 00
-LOAD HEAD
-SECTOR
-INDEX
-TRACK "00"
I
I
COI\JTR.OL
LOGIC:
-LOAD HEAD
CARTRIDGE
DOOR SECURED
<;
I
I
READ/WRITE
HEAD OPENING
TRACK 49
OPENING FOR
DRIVING HUB
COMPOSITE INDEX/SECTOR
5-5
TRACK 00
LED
COMPOSITE
INDEX/SECTOR
STEP IN
LOAD HEAD
TRACK 00
Light
READ HEAD
prepare the disc file for operation. The events and timing
for this sequence are shown in Figure 5-8.
The SCU flexible disc interface applies primary and
secondary power to the 650.
After a two-second
delay, -STEP OUT is pulsed until the head is positioned
at Track 00. This operation is performed to ensure that
the head is properly oriented before a read operation
begins. When the head is positioned at Track 00, the
TRACK 00 signal becomes true. It changes to false when
the head leaves that track.
The -LOAD HEAD signal can be applied any time after
the power has been turned on. When the -LOAD HEAD
line is false, the head is unloaded from the disc. The disc
must be loaded on the head before a read operation can
begin.
5.4.4.2 TRACK ACCESS PHASE
The -STEP OUT and -STEP IN functions are used for
positioning the head to the desired track. The only
restriction placed on these Signals is that each pulse
must be spaced by at least 20 msec. The -STEP IN pulse
width is the same as the pulse width for -STEP OUT.
PRIMARY
POWER (AC)
SECONDARY
POWER (DC)
SEP CLOCK
STEP OUT
----1
I-
.-jl
- - -.....
""1.
.
- - -
T~: :sEE:
---------------2-0-.0-M-S-E-C-M-IN-------------~~~rf1~---------------..
TRACK 00
LOAD HEAD
-------------------------~frJ
r --- -------------
5-6
--..l
:'-2.5J1Sj
LO.25I1S (TYPICAL)
READ
DATA
STEP IN/OUT
I_
.....J
1---20.0 MSEC
~~~_ _.....
I
MIN~
+5.25 V MAX
1 - - - 2 0 . 0 MSEC MIN
READ ENABLE
j ~.,.-----
+3.3 V MIN
+0.4 V MAX
'--______---f,s
VALID
READ DATA
--f
~ 1.0 MSEC
U~-------'ll~~
-.l
14--2-50--~1
100 NSEC
+100 NSEC
n'-_____
SECTOR
Jl
INDEX
_________________________
10~.~0~M~S~EC~_n.....
+0.0 V MIN
------L-
I-
-50 NSEC
50 ns
MSEC
5r\--------~nL
160.0 MSEC
-I
5-7
5.4.5.1 CONTROL
HOST
SYSTEM
FLEXIBLE
DISC
FilE
COMMOIII RETURIII
-LOAD HEAD
'-'"\
COMMOIII RETURIII
AX
Input Signals
Table 5-1 lists characteristics of the input Signals.
Output Signals
Table 5-2 lists characteristics of the output signals.
10
11
TABLE 5-1.
12
'-'J'""'i
~INDEX
16
f"'\X
X'-'
COMMON RETURI\j
- TRACK 00
INPUT SIGNAL
DESIGNATION
17
CONNECTOR
AND PIN
ACTIVATION
POLARITY
PULSE
WIDTH
LOGIC
CARD
-STEP IN
J1-1
Negative
COMMON
Jl-2
Negative
10 /lsec to
10 msec
r...
,)"
,.....
6
7
LOGIC GROUND
5 vDC
D.C.
POWER
SUPPLIES
r\.
X
'-"
A
Y
~r-v
50/60 HZ
DEIIIOTESSHIELDEDWIRE
~
MOTOR
-.LOAD HEAD
J1-10
Negative
COMMON
Jl-11
Negative
head load
Return
solenoid
TABLE 5-2_
J2
yy
-.0
Negative
FRAME GROUIIID
Jl-3
10 /lsec to
Enables
Level
50 OR 60 HZ
110 V
-STEP OUT
RETURN
42
r...
A.C. POWER
Positioning
Return
RETURN
10 msec
32
X
'-"
J;
24
+24 VDC
Track
L--
COMMENTS
18
'-'
r-'\.
~'-'
-SECTOR
FUNCTIONS
1
2
X'-'
-STEP OUT
COIIITROL AIIID
DATA
J1
r...
r...X
-STEP 1111
CONNECTOR
AND PIN
ACTIVATION
POLARITY
PULSE
WIDTH
-SECTOR
Jl-12
Negative
1.0 msec
COMMON
Jl-l1
Negative
-INDEX
Jl-16
Negative
COMMON
Jl-17
Negative
-TRACK 00
Jl-18
Negative
COMMON
Jl-17
Negative
OUTPUT SIGNAL
DESIGNATION
COMMENTS
Indicates location
on disc
Return
RETURN
1.0 msec
Indicates location
DEIIIOTESTWISTEDPAIR
Return
RETURN
RETURN
on disc
Level
Return
5-8
5.4.5.2 DATA
5.4.5.3 POWER
TABLE 53
DATA SIGNALS
CONNECTOR
AND PIN
ACTIVATION
PULSE
POLARITY
WIDTH
LOGIC
COMMENTS
J15
Negative
0.25 j.lsec
J1-6
Negative
0.25 j.lsec
DATA
-SEP
-15VDC
Logic ground
+5: 0.10VDC
Power
Logic Power
@0.6A
level
supply
50 mv ripple
@0.12A
Power
for read/write
50 mv ripple
level
amplifiers
ground
Jl32
Jl42
Positive
I!
I
I
I
(-12VDC)'
ground
I
DC power supply
-15 0.30VDC
Negative
CLOCK
-12VDC can be
-.12 0.25VDC
@0.12A
+24VDC
Jl8
I!
I
Positive
+24VDC
Jl9
RETURN
I
I
I
, used in lieu
i of
50 mv ripple
+22 lVDC
Power
@2.0A
level
DC power
ground
ground
ground
Line
50/60Hz
Three
AC
terminal
socket
solenoid
DC power
J2
-15VDC
DC power supply
100 mv ripple
DC Power!
110VAC
COMMENTS
DC power supply
Logic ground
Logic
GROUND
+5VDC
-SEP
Jl24
PULSE
WIDTH
110
+24VDC power
ground
!Must be provided
10"10 VAC
@0.75A
Line
50/60 t 0.5Hz
AC
single phase
! from a branch
circuit protected
at no more than
20 amperes.
FRAME
J2
Frame
Frame
Frame
Center socket
GROUND
Center
ground
ground
ground
of 3wire AC
Socket
socket
5-9
LIGHT
SOURCE
DISC
DETECTOR
INDEX
TRACK 00
POWER
SECTOR
SEP
CLOCK
LD HD
IN
OUT
STEP
5-10
Channel Interface -
Communications link
between the SCU and the
using IBM system.
Microprocessor
Controller Interface-
Communications link
between the SCU, the Controller, and the DDM's.
FE Interface
FROM
USING
SYSTEM
PROVIDES INTERFACE
MICROPROCESSOR.
BETWEEN
THE
650
FLEXIBLE
DISC
AND
THE
MICROPROCESSOR
CHANNEL INTERFACE
--
STORES MICROPROGRAM
-.-
CONTROLLER INTERFACE
TO
DRIVES
j
.
FE INTERFACE
PROVIDES INTERFACE BETWEEN FE PANEL AND OTHER SECTIONS OF THE
SUBSYSTEM.
FE PANEL
6-1
6.2.1 General
The SCU Channel Interface is the asynchronous link
between the IBM Channel and the SCU Microprocessor.
The Channel Interface hardware consists of Bus In lines
and registers, Bus Out lines and registers, address
compare logic, select logic, priority logic, tag lines and
registers, data transfer logic, control registers, and the
multiplexers necessary to handle data to and from
multiple channels. Refer to the block diagram in Figure
6-2.
NOTE
Refer to Section 3 of this manual for
descriptions and definitions of interface lines, commands, and selection
sequence.
6.2.2.5 REGISTERS
The sequencing of the Channel Interface lines in the SCU
to communicate with the channel is controlled by six
special purpose registers.
BUS
OUT
PARITY
ERROR
CU
END
OWED
IN
ITIAl
SELECT
ADDR
OUT
CMD
OUT
CHAIN
ING
DATA
OUT
SERVICE
OUT
CHNl
TRANSFER
CHNL
WRITE
RESET
BUS OUT
PARITY
CHECK
CON
TROL
UNIT
BUSY
LOCK
CHNl
SW
Sup
PRESSSIBLE
DATA
TRANS-
ID
CODE
BIT2
ID
CODE
BIT 1
FOR CHNL
MUX
SCU
ADDR
SCU
AD DR
4
SCU
ADDR
2
SCU
ADDR
1
CU
BUSY
IN
PROG
TAG
ID
CODE
BIT 2
ID
CODE
BIT 1
FOR
SELECTING
CHANNEL
FOR
SELECTING
CHANNEL
6-2
o BUS
---
CHNL A BO 0-7. P
CHNL B BO 0-7. P
CHNL C BO 0-7_ P
CI500
SEL BO 0-7. P
BUS
MULTIPLEXER
CHNL 0 BO 0-7_ P
CM501
LHNLABUSOUTO-3
CHNLOBU~~::::
VALID ADDRESS
SELECT
LOGIC
(X4)
ADDRESS
COMPARE
(X4)
----
BUFFER A
CJ500
BUFFER B
CJ500
(X4)
CX502
,~41
CHANNEL
PRIORITY
SCANNER
REQUEST IN (X4)
...
CHANNEL
IDENTIFICATION
CODE
PARITv
CP REG
RF. RA " BO
BUS 4
~
ERROR
IX41
.....
~
CHF
REGISTERS
(4)
CI501
..
..,..
~
CX503
CX501
-'"
~
cu BUSY
~NNErr
DATA
TRANSFER
LOGIC
tt
CI502
CX501
i1SERVICE
IN/DATA IN
DISCONNECT IN
FT BUS
lAG
MIJ'. TiPLEXER
LOCK
CHANNEL
CH
CI501
SWr
CHANNEL IDENTIFICATION CODE
CHC
REGISTER
I~:~~~:~R
CI501 10 CODE
CI501
CH A BUS 0-7
MUX
CI501
CT MUX
o BUS
2-7
CI500
CT A-D
0-7
CT MUX
"""\-CX500
CT
LTCH
..
--
CT 0-7 __
EX501
EX501
-'"
TR 07 __
CI500
DATA IN
TR
REG
EX501
MULTIPLEXER
I-
CT REG
(X4)
CT
A-D
0.1
l=0\>
SERVICE IN
BI REGISTER
B
~~
CX500
CI500
'~,"Hj=f}
RD-Bl
CHANNEL
0-3: CM5()( ~E
4: EX501
6,7 CI502
~ "":'''''
I-
OP IN
LOCK CHANNEL SWITCH
CJ501 ' 1 1
DECREMENT CC
+
P
CHNL BUFFER
ROV
PRIORITY
ENABLE
CJ500
1
JK
LOB
25-30
CX500
INTEC
GEN RST
(X4)
BO - CC 24-31
MUX
CI
REGISTER
-..
BUS
o BUS 0-7.
CBR
CHNL SEL
OUT
INITIAL SELECT
BO
REGISTER
CJ500
CHC
r-CX500
CC 16-23
......
PRIORITY REQUEST
JUMP 0-3.
CHANNEL ENABLE
..
JUMP 0-3
JUMP 0-3
CC
REG
D::9
BUS IN
REG 0-7. P
,
BUS IN A 0-7_ P
CHNI.. A
DEMULTIPLEXER
BUS IN B 0-7_ P
CHNL 8
BUS IN C 0-7. P
~
:H".
BUS IN 00-7. P
CHNL S
CX502
CHC 0
6-3
RE
AllOW OPERA
RE
TIONAl
QUEST OUEST
DIS
IN
IN
ABLE
IN
OF
OUEUE STACK
THIS
STATUS
ED
STATUS CHNl
ADDR
IN
STATUS
IN
DATA
IN
SER
VICE
IN
CP Register Bit 4-7; Priority Windows. Channels AD.When set by multichannel processor, blocks
microprogram detection of INT bits (5) and CHF 2. If the
channel attempts selection with this bit set, Select Out is
blocked and no further channel action takes place until
either: 1) CU Busy (CHC 3) and/or Lock Channel Switch
(CHC 4) is set, in which case a short busy sequence will
begin; 2) Priority Window (CT 7) is reset, in which case
selection may proceed normally; or if the control unit is
already selected, a short busy sequence will begin.
RE
RE
RE
RE
RE
RE
RE
QUEST
QUEST QUEST QUEST QUEST QUEST QUEST
IN
IN
IN
IN
IN
IN
IN
QUEUED QUEUED QUEUED QUEUED STACK STACK STACK
STATUS STATUS STATUS STATUS
ED
ED
ED
CH 0
CH B
CH A
STATUS STATUS STATUS
CH C
CH B
CH 0
CH C
7
RE
QUEST
IN
STACK
ED
STATUS
CH A
CHAN
NEl
ERROR
POINT
ER
OVER
RUN
ON
CHAN
NEl
WRITE
PRIO
PRIOR
PRIOR
PRIOR
lTV
lTV
lTV
lTV
WIN
DOWS
CH 0
WIN
DOWS
CH C
WIN
DOWS
CH B
WIN
DOWS
CH A
6-4
BUS IN
_ - Q - E - - - - - I TRANS FE R I-----S-D::-;
__~-I..,.~N=-E""IN--RD=BI
H~O:6:~~EI---------~~
CC REG
D BUS
CBR
FT BUS
6-5
1"'"-''--
BUFFER
A
MUX
BUS OUT
DATA IN
--"":S:':"E:":'R':":V"":'IC:":'E-I-N--t
A BUS
---r--
CBR
TC~~~:~~ t -_ _ _ _ _Q;::;E::....-_-tl~
--~~~----tHARDWARE~
CC REG
_ _ _ _ _R_A_=_BO_ _
FT BUS
transferred regularly, the microprogram indicates Suppressible Data transfer to the channel hardware by
setting bit 5 in CHC. The transfer operates identically to
that described above, except that the Channel Interface
hardware is inhibited from setting Data In or Service In to
transfer a new byte while Suppress Out is set at the
channel. When Suppress Out is off, however, the data
transfer hardware continues unaffected.
Channel Read
Indicates that one or both channel buffers are empty.
Channel Write
Indicates that one or both channel buffers are full. The
buffer may be unloaded in the same instruction as the -B
(CBR) statement.
6.2.4.2 QUEUE EMPTY
Indicates that both channel buffers are empty during a
Read operation or the CC Register contents are zero.
6.2.4.3 CHANNEL INTERRUPT (INT 5)
Channel Interrupt is active under one of the following
conditions:
1. Initial Selection AND Not Short Busy Sequence
AND Not Operational In.
2. Operational In AND Halt I/O + Truncation.
6-6
WRITABLE
CONTROL
STORAGE
---
J~
FLEXIBLE
DISC
INTERFACE
"
DATA
PATHS
...
,~
,r
INPUT TO
B MUX
INPUT TO
F MUX
INPUT TO
B MUX
INPUT 10
F MUX
BRANCH ADRS
TO ADRS REG
MICROPROCESSOR
CONTROL FIELDS
TRANSLATION
6.3.2 Microinstructions
6.3.2.1 DESCRIPTIONS AND FORMATS
The microprogram controls the SCU hardware through
the sequencing of microinstructions. These microinstructions are divided down into fields whereby each field
controls a specific function in the hardware. In the SCU
the data for these microinstructions is stored in WCS.
There are four microinstruction word formats. Each
format, and the fields contained therein. raises specific
controls which operate upon the logic circuits.
MICROINSTRUCTION
FIELDS
BRANCH ADRS
TO ADRS REG
MICROPROCESSOR
CONTROL FIELDS
TRANSLATION
MICROINSTRUCTION
FIELDS
MICROPROCESSOR
CONTROL FIELDS
o
INPUT TO
B MUX
BRANCH ADRS
TO "'DRS REG
INPUT 10
F MUX
TRANSLATION
MICROINSTRUCTION
FIELDS
BRANCH ADRS
TO ADRS REG
INPUT TO
F MUX
Translation
RA
FORMAT 3
RD
RK
RX
RT
RF
RBC
RN
BUFFER
STORAGE
TRANSLATION
MICROINSTRUCTION
FIELDS
6-7
r---------,
B FLO
Branching
B FLD
[ )
RN FLO 05
RN FLO 68
FMT 23
RN FLO 911
FMT 3
RX FlO
FMTO
RK FLD
FMT 0 + 1 + 2
RBC FLO
FMT1+2+3
RA FLO
FMT 0
FMT 3
BA FLO
FMT 1 + 2 + 3
BA2 + BA3 FLD
X FLD
ECC
HOWR
Z FLO
Be FLO
A FLD
1+3
FMT 0
)RT/RF
XLTR
SEP RT
AND RF
DECODES
I
I
)L____________~~:.J
I
FMT2
r---------------,
I
I
I
CC FLO
L.. _______RT501
BA3 FLO
C FLO
6-8
RD 0-7,P
BRA
MUX
Rl0-7,P
R20-7.P
R30-7,P
G70-7.P
DO-7,P
INT COND (B)
BRA
0-7.P
SEL GC502
PSA 4-7
DIO-7.P
2. When the microinstruction being executed contains the WCS control statement.
BR
MUX
GM502
ENABLE 01
ENABLE CHF
BR CHF 0-7
BRANCH
ADDR
SET
MUX 1
BRANCH
ADDR
SET
MUX 2
CHF 0-7
RA500
RA500
BC FIELD - -....-------~
ECC Generation
6-9
r----------------------------------------J~~--------------------------------------------------------~
10
1~
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
"
FORMAT 3 MICROINSTRUCTION
FIELD
CONTROLS
BINARY VALUE
OF WORD
STATEMENT FOR
INSTR. BLOCK
OP
CODE
BA3
BC
BA
WORD
FORMAT
A BUS
o BUS
B BUS
ALU
BRANCH ADDR
BITS (11-6)
BRANCH
FIELD
BRANCH ADDR
BITS (5-0)
SELECTS BO
REG TO A BUS
SELECTS
Gl TO
B BUS
HIGH ORDER
SIX BITS OF
RN (11-6)
SELECTS
ALU FUNCT
ADDR
"-
SELECTS BRANCH
CONDITION
/
"-
LOW ORDER
SIX BITS OF
RN (5-0)
~'
HEX
CODE
00
01
02
03
04
05
06
07
08
09
OA
OB
OC
00
OE
OF
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
10
1E
1F
BC CODE
B (BRO)
B (BR1)
B (BR2)
B (BR3)
B (BR4)
B (BR5)
B (BR6)
B (BR7)
B (0 =0)
-B (0 =0)
B (0 =FF)
-B (0 =FF)
B (CARRY)
-B (CARRY)
-B (COMPARE. EO)
B (COMPARE. HI)
B (lNT)
-B (lNT)
B (CNT =0)
-B (CNT =0)
B (LD.SR_*1) LOW
B (DBR)
B (lLACT)
-B (DBR + INT)
B (CBR)
B (0. EMPTY)
B (NO. BRANCH)
B (LD.SR.*+1) HI
B (UNCOND)
B (D_BUS)
B (ADR =SRI
ADDR
REGISTER
0
1
Di
n-{
TO
INCREMENTER
3
4
ADDRESS
5
6
BUS
TO STORAGE
CONTROL (WCS)
8
9
10
11
TO DISPLAY
AND ADDR ERROR
CIRCUITRY
RA502
6-10
INCR
BITS 0-11
SR EXT
3120
. -
IPL
BITS 011
BRCH
ADRS 011
START
ADRS 011
...
ADDRESS 10-71
118-11,--
.......
ADDRESS
REGISTER
DEC
RBSOD
CS
WCS
-RAM-
...
RBSOD
--
RAM
MUX
RM
A~
DATA
REGISTER
ECC Checking
RDSOD
DATA BITS
233
FD
ECC
GENERATION
AND
VERIFICATION
RA502
...
DATA BIT50-41
SYNDROME
GEN
RD50D
FD
A~
"
ERROR
CORRECTION
AND
DETECTION
HARDWARE
FD
INTERFACE
After the data from the WCS is set in the Data Register,
the data and its ECC bits are passed through a syndrome
generating circuit. The generated syndrome is applied to
the correction circuits. If the syndrome is all zero's, no
'error exists. If the syndrome has 3 and only 3 bits
present, a correctable error exists and is therefore
corrected. If any combination of syndrome bits are
present, except 3, an uncorrectable error exists and the
SCU will stop.
Pl- PB
t
DATA
AND ECC
FROM
FD
FC
RESOD
LDB
0-33
"
D BUS BIT 07
MICRO
PROCESSOR
CONTROL
HARDWARE
---
MICROINSTRUCTION
TRANSLATION
RT50D
RT501
6-11
CHIP SELECT
COLUMN 1
10
11
12
13
14
15
16
0-7
ADDRESS INPUT
FROM ADDR REG
--+-DOO
ROW A
AD DR BIT 0-12
WCS OUTPUT
JUMPERED IF
NO WCS EXT
wcs
RB
8-11
DO 0-41
CS1, CS2
D
E
CS3
RAM
MUX
MAXIMUM
4
BOAR~L-____~
RM
3
WCS
EXT
DO 041 U
ADOR BIT 13
1K
A
3K
.A
4K
A
B Bus
-+-o-RIVER
WCS SIGNAL
WRITE ENABLE
ROW A - F
o
Figure 6-11. RAM Board Column Select
6.3.4.1 BUSES
The Microprocessor has five major buses which allow
the transfer of data throughout the SCU. These buses
consist of the A Bus, B Bus, D Bus, T Bus and BR Bus.
The T Bus is 36 bits wide to allow the transfer of 32 data
bits and 4 parity bits. The A, B, D and BR buses are each
Bus
T Bus
This bus transfers data. from the output of the F
multiplexer to a register determined by the RT control
bits. In Format 0 microinstructions, the X field is placed
on the T bus and the RT control bits are specified by the
C field of the microinstruction. In Format 2 microinstructions, the RT control bits are decoded from the CL field of
the microinstruction to effect the necessary register-toregister transfer.
T BUS 32 BITS
GENERAL
PURPOSE ~
REGISTER S
FROM CHAN
FILE.FO&FE
INTERFACES
"
u
GO
(S BITS)
GEN. PUR.
I"
II
l
o BUS
1"
G1
G2
(S BITS)
GEN. PUR.
II "
~I
G4
G5
G6
"
G7
"
RO
(S BITS)
GEN. PUR.
(8 BITS)
GEN. PUR.
(S BITS)
GEN. PUR.
(S BITS)
GEN. PUR.
(8 BITS)
GEN. PUR.
(8 BITS)
GEN. PUR.
(S x 16 BITS)
SCRATCH
I ..
I"
"I
"
_+ I ~~
JI
G3
A~ ~
"
"
PS
(8 BITS)
MPX R03
& BR MPX
.4~
.0
"
~l
FT BUS 32 BITS
'.
Rl
R2
R3
(S x 16 BITS)
SCRATCH
(Sx16BITS)
SCRATCH
(S x 16 BITS)
SCRATCH
"
I
I
I
"
"
"
I A~
~I
~I
FUNCTION
DECODES FROM ..
MICROPROGRAM ...
WORD
"
A BUS
ALU
A
S BITS
"
D~ ~
I I
II
MICROWORD
CONSTANT
(16 BITS:
OP.Q)
(8 BITS:
OP12)
"
I
~~
"
I .. ,",u" ""
0=0
BRANCH CONDo
D=F F
BRANCH CONDo
A<B
BRANCH CONDo
A=B
BRANCH CONDo
CARR Y
BRANCH CONDo
TO ADDRESS REGISTER
MCM
CCK
BUF
BAR
INT
18 BITS)
MACH CHK
MPX REG
MACH CHK
OR CHC
(512 WORDS
32 BITS
BUFFER)
STORAGE
(9 BITS)
ADD FOR
BUF
(8 BITS)
INTERRUPT
REG.
IMK
CNT
SR
(8 BITS)
(8 BITS)
116 BITS)
INTERRUPT MACH CYCLE SUBRTN RET
ADDRESS
REG. MASK
COUNTER
.l
A~
T BUS 32 BITS
BRANCH
CONDITION
GENERATOR
B BUS S BITS
.n
o BUS S BITS
FROM CHAN
FI LE.FD & FE
INTERFACE
A~
.....
TO ADDRESS REGISTER
1"
"
SPECIAL
PURPOSE
REGISTER S
S BITS
T TT T
I I
II
G2.G3-----....J
INCREMENT BAR CONTROL - - - - - - - - - - '
DTC
= ZERO
..
...
........
SUBROUTINE
REGISTER
TO ADDRESS REGISTER
TO CHANNEL. FILE,
FD. & FE INTERFACES
TO CHANNEL &
FILE INTERFACES
.:
~~T;~~~6T CONDITION)
~N~E~ZERO
INCREMENTER
~~~I~~~~UTINE
.
~
_______________________________________________~~
CNT = 0 BRANCH
CONDITION
INTERRUPT BRANCH
CONDITION
CHAN.INTP.
RESPONSE
CHECK 2
6-13
BR Bus
TABLE 6-1
BIT POSITION
ROW 0
2
1
1
1
P P P P P P P P
1 2 3 4
7 s
5 6
30 31 32 33 34 35 36 37 3B 39 40 41
1
1
0
1
1
2
3
REGISTER
GATED TO BR BUS
HEXADECIMAL
CODE IN
PS REGISTER
BITS 4, 5, 6 AND 7
22 23 24 25 26 27 28 29
10 11 12 13 14 15 16 17 IS 19 20 21
6
7
G4
Rl
R2
R3
INT
RO
G7
0
CHF
9
A
B
C
01
E
F
6.3.4.2 REGISTERS
1!0
BIT POSITION
0 1 2
EXAMPLE
DATA WORD
1:
10 11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
P
3
P
4
P
5
P
6
P
7
34
35
36
37
3B
39
40
41
0
1
PI
P
2
1
1
1 1
0
0
1
6-14
Transferring data
Register and R23.
between
the
Buffer Oata
4
SR
SR
SR
BR
PAGE
PAGE
PAGE
PAGE
MUX
MUX
MUX
MUX
SEL
SEL
SEL
SEL
SEL
SEL
SEL
SEL
CHNL
OAT';'
BYTE
XFER
2860
CNT
CNT
CNT
MODE
"0
ZERO
ZERO
CHNL
lOX
INT
CHK
RESP
Subroutine
3672.21 -0001-10/75
Bits 0-3. Page Select. Bits 0-3 are used to address the
Register File. The Register File word operated upon
during a microinstruction's execution is determined by
the value of the PS Register at the end of the previous
microinstruction's execution. The PS Register is loaded
at Register Time.
Bits 4-7. Branch Multiplex Select. Bits 4-7 are used to
'select the register to be multiplexed onto the BR Bus. The
data on the BR Bus is loaded into a buffer at Register
Time of a microinstruction's execution.
CCK Register. The CCK Register is a multiplex of two
independent registers - the CHC Register and the MCK
Register. MCM Register bit 4 controls which of these two
registers is multiplexed onto the A Bus as CCK. When
MCM bit 4 is a set, the CHC Register is multiplexed onto
the A Bus and the MCK Register is degated.
MCK Register. The MCK Register is the collection of 47
latches which are set by specific error conditions
(paragraph 6.6.1). The contents of these latches can be
accessed eight bits at a time through the A Bus. The
eight bits available at any point in time are controlled by
the MCM Register. The error conditions associated with
each latch are shown in Table 6-3. This table presents
error conditions, along with the necessary states of the
MCM Register, to access the conditions through the A
Bus.
6-15
EN
NOT
ECR
ECR
CCKI
MCK
MCK
MCK
CK
USED
MUX
MUX
SFD
MUX
MUX
MUX
BIT
BIT
MUX
BIT
BIT
BIT
BIT
MCM REGISTER
BIT POSITION
MCKO
MCK 1
MCK2
MCK 3
MCK 4
MCK 5
MCK 6
MCK 7
CHCPARITY
ERROR
MULTIPLE
WCS
A BUS
B BUS
T BUS
BRANCH
IMPL
ALU
BR
PS
TRANS
LATION
SUB
ROUTINE
WCS ECC
MULTIPLE
BUFF
BUFF
EGG
TBUFFER
ERROR
6.3.5.1 GENERAL
P1
P2
P3
P4
P5
P6
P7
P8
SEL
SINGLE
SINGLE
FA 12
FA 11
FA 10
FA 9
FA 8
RESET
BUFF
WGS
FA7
FA 6
FA 5
FA4
FA 3
FA 2
FA 1
FAO
GA
GB
GG
GO
FD
READ
FD
SEEK
FD NOT
READY
WRITE
BUS
NOTES
A description of the CC. CI. CHF. CT.
CPo TR. BO and BI Registers will be
found in paragraph 6.2.
A description of the OTC CO. 01. ~O.
and RWC Registers will be found in
paragraph 6.4.
Functions
Add (+). Arithmetic sum with carry-in of zero is performed on operands A and B. The carry latch is loaded
when this function is executed. and is available for
branching on the next machine cycle.
Add With A Carry (+1). Arithmetic sum with carry-in of
one is performed on operands A and B. The carry latch is
loaded when this function is executed and is available for
branching on the next machine cycle.
Add With a Carry Determined by the Carry Latch (+C).
Arithmetic sum with carry-in equal to the value of the
carry latch is performed on operands A and B. The carry
latch is loaded when this function is executed and is
available for branching on the next machine cycle.
Shift A Left (L). A shift left operation is performed on
operand A with the carry-in latch being set with the
carry-out from the ALU from the previous instruction's
T Bus Register
6.3.5.2 DESCRIPTION
A block diagram of the buffer storage is shown in Figure
6-15.
6-16
'-H~~~fl
G5
~I
G6
"
I
I
l____
_
I
G0501:
~
SW BUS
SW 0-7
A-BUS
PRE MPXR
VO
CS
o BUS
RA, VC
'/
DISPLAY MPXR
CS 0-7
VO
AA 0-7
RA
BI~
--
DISPLAY BUS
VD
--
BRANCH CONDITIONS
RA
II'
G0501
~
CHANNEL PRE MPXR
CI
CH A BUS 0-7
FILE 0-7
A1 INT
R03 CARD PRE MPXR
GC
A BUS PRE MPXR 1
GO
A BUS PRE MPXR 2
GO
A BUS
--
A10-7
A20-7
r'\.
GD500
ALU DECODES
RT
LOB BITS
RE
CONTROL BITS
A
B ALU
B-BUS MPXR
...
A *B
CARRY
FF
G0500
l.....
-~
1----1
o BUS
f\
ALU
ERROR
GE
COMPARATOR
ALU ERROR
G0500
\.
B BUS
0-7
GEN
RA BITS
RB BITS
BRANCH
CONDITIO~J
A <B
--
PARITY
CHECKER
--
PARITY
CHECKER
G0501
GE
G0502
G0502
..
6-17
BUFF
PAR
GEN
BUFF
MLX
BUF
BIT
32-38
MB500
,~
T Bur
ERROR
MD500
NOTE
lit
,It
l'
ECC P5-P7
PAR GEN
ECC Pl-P4
PAR GEN
MD501
BP 1-4
Pl-4
, ,It j
P5-7
BP 5-7
,r
"
ECC
ERROR
BuF~ER
STORAGE
COMPARE
MD501
MB50l
,~
BUF ECC
OUT 0-31
"
8UFF
MPXR
GL
BUFFER
ADDRESS
REGISTER
INCREMENT
BAR
G3
BUF MPX
0-31
,r
T-BUS
REGISTER
GA/GB
MB501.
= R03
sequence
6-18
D
E
1
1
1
1
1
1
1
1
1
1
P1 P2 P3 P4 P5 P6 P7
1
1
1
1
1
1
1
1
1
12 13 14 1~ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
1
1
10 11
1
1
TABLE 6-5. EXAMPLE DATA WORD APPLIED TO BUFFER STORAGE ECC MATRIX
'5
DATA WORD
6 17
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2930 31
3672.21-0001-10175
32 33 34 35 36 37 38
P1 P2 P3 P4 P5 P6 P7
1
1
1
1
1
1
1
1
Parity
Parity for the data read from the buffer is generated by
the ECC circuits and gated into the T Bus Register. Odd
parity is used with a parity bit for each byte of the data
word.
E
F
6-19
HEXADECIMAL
ADDRESS
000
I
007
cx:s
I
I
HEXADECIMAL
ADDRESS
HEXA
DECIMAL
AODRESS
07F
10F
080
110
I
I
I
I
I
I
I
I
I
I
I
I
137
Restart Displacement
138
139
Retry Parameters
128
129
Count Buffer
12A
12B
13A
13B
13C
12C
120
ECC Panern
113
010
OAO
114
117
lIB
130
I
OBF
I
I
I
I
I
"
llB
OEO
l1C
OFF
I
I
I
I
I
I
.:
12E
ODF
oeo
040
05F
03F
I
09F
O~O
HEXA
DECIMAL
ADDR~SS
127
:
017
126
OOF
I
HEXA
DECIMAL
ADDRESS
Not Used
100
060
I
I
SIring 0 Drive 7 Data Word 0'
I
I
11 F
I
I
I
I
I
1
17F
Data Buffer
1~0
I
18F
Log Sense Bytes 0-23
190
'~'
Diagnostic Scratch
136
120
Key Buller
131
I
I
Not Used
130
17E
IFF
125
FIGURE 6-16.
3672.21-0001-10175
6-20
HEX
ADDRESS
RANGE
BYTE 0
0
11
~lrong
~t"ng
~evice
~ev,ce
~ev,ce
Reserved
Cha,n
In9
Un,t
Check
SIP
or
SSIP
CU 0
I I J
2. '47.
483.
648
I'
.073.
74' .
824
I V
12
256
Index
Error
32 768
I I
cu
1'6.384 I
536
.
870.
912
1268.
435.
456
134
217.
728
167.108133.554'116.777.
864
432
216
8.192
8.388.
608
4.096
2.048
1.024
1 1 .024
512
256
128.
64
SEEKS
'NOT USEDI
{NOT USEDI
\1
4.096
2.048
512
256
[IJ
I'
1 3
\1
32
16
Online
1 4
15
17
\ 7
\ 2
2.097.
152
1 048
576
524.
288
64
l'
l'
\ 4
\5
II
0
3
17
I'
32
16
1
1 1 I
5
'
32
1 2
-'
I
\
BYTE 3
I I
4
D
5
Anentlon
Busy
_14
12
262
1 144.
131
072
I I
C
I I I
B
11
12
65.
536
.32.768
16.38418.192
1 16
32.768
'6.384
16
4.096
2.048
8.192
1 024
.
ill
512
.1
I
I
I
SM
CUE
Seek
Mask
Busy
I I 1
128
64
Seek
Mask
2
17
11J
Diag
AI!
Write
Auto
Mask
Pad
PCI
Fetch
Mask
CE
16
DE
UE
uc
1
1 1
Double!
Density
32
1
14
12
11
2.048
1.034
512
256
128
64
1
128
I
164
(NOT USED)
32
'6
32
16
12
I'
11
15
17
SEEK ERRORS
[II
I,
I'
12
3
1
11
I' I
0
3
11
I'
I 1
(NOT USED)
15
Cham
{NOT USED,
In.
(NOT USED,
[II
Mask
INOT USED)
SFM
Wrote
BYTES READ
256
INOT USED)
5
Stacked
11
(NOT USED)
15
I I
DEVICE TYPE
12
{NOT USEDI
ill
[II
Mask
".
12
CHANNEL STATUS
HEAD ADDRESS
1512 DO 1256 DD
256 SO
'
11
Write
A
Sector
Ready
FILE MASK
(NOT USED)
11
BYTES READ
m
I I
2
128
plete
FIGURE 6-16A.
3672.21-0001-10175
INOT USED,
118-11B
HIGH CYLINDER
4.194.
304
OEOOFF
116.3841 8.192
11
11
Seek
Com-
I I
32.768
DE OWED
Seek
Incom
plete
tNOT USED,
114-117
64
oeOODF
I'
Offset
Actrve
0A0-06F
BYTES READ
SEEKS
110'13
I I I I I I I
,2B
12
DRiVE STATUS 1
BYTES READ
060-07F
11
LOW CYLINDER
HIGH CYLINDER
04005F
I I I I I I I
ooo-OIF
BYTE 2
BYTE 1
[II
0
3
6-20A
BYTE,
BYTE 0
HEX
ADDRESS
RANGE
' I
Im I I I I I I ,
127
UC.
Log 510
Oone
Log
S",ng
4
Smng
2
5'''"9
1
Dnve
4
Dr,ve
2
Dflve
138
64
.28
1
32
128
64
32
I , I
BYTE 2
I I I I I I I,
Ms~
Ms~
'6
12
I'
16
128
64
I'
1 32
BYTE 3
1'6
1 8
I
,28
1 J
I
64
I ' I
11 1 1 1 I
I I I I I
I'
1
[I]
1, I
I
,
{NOT USEDI
(NOT USED)
Mssg
Fo'ma' 4
Fo,ma' 2
Fo,ma' 1
Fo,mat8 4
Mssg
8
2
CURRENT OFFSET
'39
32
16
J
I
Log
Sense
Log
Log
Count
Count
128
64
32
16
16
I'
2
1
128.1
64
32
/,
When bit is set to a 1. numbered device has Disconnect Command Chaining in progress for this channel
~hen
IT]
FIGURE 6-16A.
3672.21-0001-10175
Device
6-208
I
I
FLEXIBLE
DISC
I
I
I
I
I
I
READ
LOGIC
I
I
..
.....
..
LOAD MEMORY
WRITE ENABLE
SCAN
IPL
ADDRESS
GATE
WRITE ENABLE
FC510
.....
..
SEP DATA
D-BUS (GDI
FDD MUX
AND
REGISTER
FDD BITS
--..
....
FC520
....
SEP CLOCK
..
F
FDC MUX
AND REGISTER
I
I
FD
SHIFT
REGISTER
SECTOR
~ ~
I
I
..
-...
I
I
I
....
WRITE
DATA
BUFFER
....
~
SEP CLK
ADDRESS
REGISTER
...
EOB, TRK 00
.....
..
r
READ
LOGIC
...
~ ~
DECODER
..
FC520
IPL
LOGIC
(GEl'"
FD560
IPL ADDRESS BITS--.
(RA)'"
FC500
RD
STATUS
."
...
FD NOT READY
POWE RON-RESET
FDF ..
FDF
MUX
READ GATE
.....
...
NOTE
The block diagram on this page should
be used in conjunction with the theory
of
operation
on
Flexible Disc
the
Interface. The cali-outs noted in the
lower right corner of each block refer to
logic page numbers in the Logic Diagram
SET POINTER
TRK 0, SECTOR
TOWCS ..
FC590
FC595 I""
~
r-
:..
..
FD530
FD535
..
.......
ECC
GENERATOR
AND
COMPARATOR
FD580
FD585
ECC
BITS
ENABLE 6, 7
...
....
TO WCS ..
.. ENABLE BR + POINTER
FC520
FD540
POINTER
AND
BIT RING
COUNTERS
5 -7
CONTROL
LOGIC
ENABLE 0 - 5
~ ~ ~1~TROLS
....
SHIFT DATA
FLEXIBLE
DISC
MECHAN-ISM
.....
I
T,READ
DATA
TOWCS
---.....
SEEK STATUS
SEEK
LOGIC
FD
STATUS
LOGIC
...
(GE) ...
FC570
6-21
FDD Register
FDP
FDP
FDP
FDP
FDP
FDP
FDP
FDP
FOC. Register
The FDC Register is loaded from the D Bus by raising FD
= FDC. The output of the FDC controls the FDF MUX, the
Seek LogIc, the Read Logic, the Address Register and the
FO Pointer which in turn controls the data strobed
through the Write Data Buffer.
FOF
FOF
FOF
MUX
MUX
MUX
2
POWER ECC
BIT
ON TO
FO
SELEC
TION
FOC
FOC
FOC
MUX
MUX
MUX
2
FDC Reg. bits 0-2; FDF MUX. These three bits enable
reports through the FDF multiplexer. Loadedfrom the D
Bus by raising RD = FDC.
FOC Reg. bit 3; Power On to FD. When set to 0, this bit
enables the FD to be powered on. When set to 1, this bit
enables the FD to be powered off. Loaded from the D Bus
by raising RD = FDC.
FDC Reg. bit 4; ECC Bit Selection. When set to 0,
enables ECC bits generated by the FD interface logic to
be loaded into WCS. This bit is set to
during normal
operation. It is set to 1 only during error diagnostics.
FDCMUX =
FDCMUX = 1 -
Set Pointer
FDCMUX = 2 -
Set Data
FDCMUX = 3 -
FDCMUX
=4
Step In
FDCMUX = 5 -
Step Out
FDCMUX = 6 -
FDCMUX = 7 -
Release
IPL Logic
FD Status Logic
decode after
No operation.
bits
bits
bits
bits
bits
bits
bits
bits
FDC Reg. bits 5-7; Decodes. These bits go to a BCD-todecimal decoder from the D Bus which generates eight
decodes. The eight decodes are defined as follows:
0:
1:
2:
3:
4:
= 5:
= 6:
= 7:
=
=
=
=
=
FD Read Logic
ECC Circuit
The ECC generator accepts data bits during a read
operation and generates anEC code. The code is
compared with the ECC initialiy written into the disc
during a write operation. If the ECC compares, the code
is written into memory either from the ECC generator or
from the Flexible Disc, depending on the state of bit FDC
4. A noncomparison results in a Read Data Check signal
to the FD status logic.
FDF MUX
The FDF MUX makes data available to the A-Bus. This
data can be either Write Control Store data, IPL Address
Bits, or Status Bits denoting the status of the FD
interface. The data is multiplexed through a byte at a
time by FDC bits 0, 1, and 2. A chart depicting the FDF
MUX output bytes is shown in Table 6-6. A description of
the FD status bits (FDC 0, 1, 2 = 0) is provided in the
following text. 3 OO
FDF MUX = 0, FDF Bit 0 (Overrun). Word ready was not
reset before new data was loaded into the Write Data
Buffer.
6-22
FOC 0, 1,2
=0
OVERRUN
SEEK
COMPL
FOC 0, I, 2
=1
A7
A6
FOC O. I, 2
=2
FDF MUX
following:
FO
SEEK
READY
FO
READ
ERROR
FO
NOT
READY
BUSY
WORD
READY
A5
A4
A3
A2
Al
AO
1\12
All
10
A9
A8
36
37
28
029
EOB
40
0 41
only)
FOCO,I.2;3
0 32
0 33
0 34
FOC 0, 1,2
=4
0 24
FOC 0, I, 2
=5
017
FOC 0, I, 2
=6
FOC 0, I, 2
=7
DO
O
2
16
25
0 42
26
18
10
FDF MUX
0, FDF Bit , (Seek Complete), SEEK
COMPLETE is normally up unless a Seek is initiated by
raising STEP IN or STEP OUT. SEEK COMPLETE will
come back up, allowing another Seek to be initiated,
within a minimum of 20 milliseconds and a maximum of
40 milliseconds after a Seek is initiated.
35
19
0 21
011
20
12
13
30
22
14
39
31
23
15
192 BITS
(ALL O'S)
2 SYNC
BYTES
DATA
RECORD
10 BYTES
o0
HEXADECIMAL
TRACK
NO.
00
38
27
Track Format
(Setr 2
HEXA
DECIMAL
SECTOR
NO.
00
20
040,041,111111
NOTE
40
60
80
AD
FDF MUX
0, FDF Bit 7 (EOB), The following
conditions will reset EOB (End of Block):
CO
31
A machine reset
Initiating a Microprogram read
Release
49
EO
6-23
r--~
STEPS TO STEP
OUT IINI STATE 2
fFC5701
NOTE
GUARANTEES PROP
E R TIME BETWEEN
CONSECUTIVE STEP
IN (OUTI PULSES
(2 OF 3)
LEADING EDGE OF
SECTOR PULSE
IMPL
SWITCH
POWER ON RESET
L
f'
.
I
LEADING EDGE OF
SECTOR PULSE
REG TIME
YES
STEP TO READ
STATE 2
IPL SEEK ERR
(AFTER 16 PASSES
THRU HERE IMPL
ERR WILL BE
ACTIVATED)
LEADING EDGE OF
SECTOR PULSE
TRAILING EDGE OF
SECTOR PULSE
*IPLINHIBIT
*IPL ADDR GATE
*IPL WR ENABLE
*ACTIVE TO PPROC
(+WORD WRITTEN
INTO WCSI
REG TIME
STEP TO IPL
ADDR GATE STATE 2
*IPL INHIBIT
*IPL RST WORD RDY
~~~~~~GpG~~EE
REG TIME
STEP TO IPL ADDR
GATE STATE 3
STEP TO READ
STATE 7
ENABLE BIT
RING CTR
ENABLE BYTE
POINTER
ENABLE 0 ACTIVE,
TRK :!i:LOADED
INTO DATA REG
(FD530,535)
ENABLE 1 SETS
WORD READY
LATCH (FC5801
REG TIME
STEP TO READ
STATE 3
ENABLE BIT
RING CTR
LEADING EDGE OF
SECTOR PULSE
STEP TO READ
STATE 1 (FC500)
ENABLE BIT
RING CTR
CLEAR BYTE
POINTER
CLEAR ADDR REG
RESETS TO STEP
OUT liN) STATE 0
CONDITIONS SEEK
COMPLETE SIGNAL
(FC570
STEP TO READ
STATE 5
ENABLE BIT
RING CTR
ENABLE BYTE
POINTER
ENABLE 1 ACTIVE,
SCTR
LOADED
INTO DATA REG
(FD530,5351
STEP TO READ
STATE 6
OF .... '-'
(2 OF 3)
(1 OF 3)
RD = FDC (START
SETS READ
GATE LATCH)
FC520 ,FC560,F 0550
(ALSO SET UP
FDC 0-3 TO
USE FDF BIT 3
FOR MONITORING
WORD READY)
~READ
ENABLE 1 ACTIVE,
FD DATA BYTE S
LOAD INTO
DATA REG
RESET TO IPL
ADDR GATE
STATE 0
87
RD = FDC (SET
DATA ACTIVATES
ENABLE 6 LOADING.
FDD 0-7 INTO
ADDR REG 7 -0)
FC520,FC595,FC590
ENABLE 2 ACTIVE,
FD DATA BYTE 1
LOAD INTO DATA
REG (FD530,535)
NO
B7
ENABLE 3 ACTIVE,
- FD DATA BYTE 2
NOTE
J.lPROGRAM
B7
ENABLE 4 ACTIVE,
FD DATA BYTE 3,
INCR IPL ADDR
REG
READ
RST TO READ
STATE 0 (FC500)
RST IPL LATCH
(FC5S0)
-ENABLE ADDR REG
BEGIN J.lPROG
EXECUTION
(1 OF 3)
SE~UENCE. ALL
~PROGRAMS WHICH
REOUIRE DATA.
FROM F 0 BEGIN
HERE (I.E. DIAG
NOSTIC LOAD, COM
P LETION OF IMPL).
B7
ENABLE 5 ACTIVE,
FD DATA BYTE 4
STEP TO READ
STATE 3
ENABLE BIT
RING CTR
B7
RD = FDD (SET
FDD 4-7 FOR
WCS ADDR
BIT 11 THRU 8)
RD = FDC (SET
POINTER LOADS
FDD 5,S,7 INTO
BYTE POINTER,
ENBS) FC520,FC595
RD = FDC (SET
DATA ACTIVATES
ENABLE 7 LOADING
FDD 4-7 INTO
ADDR REG 11-8)
B7
ENABLE 0 ACTIVE,
FD DATA BYTE 5
STEP TO READ
STATE 1
ENABLE BIT
fliNG CTR
CLEAR BYTE
POINTER FC500
STEP TO READ
STATE 7
ENABLE BIT
RING CTR
ENABLE BYTE
POINTER
ENABLE 0 LOADS
DATA BYTE INTO
DATA REG
(FD530,535)
(3 OF 3)
B7
6-25
(2 OF 3)
STEP TO READ
STATE 5
ENABLE BIT
RING CTR
ENABLE BYTE
POINTER
ENABLE 1 LOAD
DATA BYTE INTO
DATA REG
(FD530.535)
25 MHZ
XTAL
~....-
- - - - -__~
OSC
'/,
CLK
TIME
TOGGLE
ENABLE 1 SETS
WORD READY
LATCH TO jJPROC
THRU FDF BIT 3
A TIME
B TIME
C TIME
o TIME
E TIME
F TIME
RD =FDC (RESET
WORD READY
RESETS WORD READY
LATCH)
FC580
LOGIC ONRE501
COMPLETE IPL
ACTION OF READING ONE RECORD
OF DATA FROM
TRACK 0, SECTOR O.
1ST PASS DATA
BYTE IS TRACK
NUMBER
1ST PASS D.ATA
BYTE IS SECTOR
NUMBER
6-26
T240iO
I
I
T40
I
I
~~------------------~~~----------
A TIME (RE50l)
__________~r___l
B TIME (RE50l)
____________~r__l
C TIME (RE50l)
r---I~
________ ________
~
__
__~--
r---L-
r-
~r---l
__________________
~r___l~
___________________
D TIME (RE501)
MEMORY LATCH TIME (RE501)
MACH RESET (RE501)
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J~
~~
L...-_ _ _ _ _ _ _ _---Jr
______________________J~~~~SE~T____________________~r_
SET INCREMENTER (RE501)
____________________________---J~~~
__S~T~E_P_____________________
STEP INCREMENTER (RE501)
~I.~~~
o REGISTER
CLOCK (RE501)
______________
-fl--------~
~~
________________ ________
~
BR CLOCK (RE50l)
____
~r___I~
____________r____t
____________
~r---l~
________________________
______________
~r____1~
___________
CO CLOCK (01500)
DO CLOCK
RESET CHK 1 (GE5OO)
____~r____l
________~r__J
.r---I~
____________
r___l.~
_____
CHECK 2 (GE5OO)
MULTIPLE OR SINGLE
WCS ERROR (GE5OO)
RBC ERROR CLOCK
EARLY ERRORS
LATCHED (GE50l)
LATE ERRORS
LATCHED (GE50ll
__~-----------------J~----------------------------L
~r-------------------------~---------------______________~_2~r--------------------------
6-27
T240/0
NOTES
T40
T80
Tl20
T160
T240/0
T200
I
I
J
J
MEMORY
LATCH TIME
211
194
REGISTER
TIME
10
21
211
194
I
76
106
178
10
206
D REGISTER
CLOCK
T REGISTER
CLOCK
97
112
137
152
155
190
007
213
INCREMENTER
STEP
---144
110
INCREMENTER
SET
194
BRANCH CLOCK
ADDRESS
REGISTER SET
ADDRESS
REGISTER
RESET
206
234
I
194
006
42
73
I<
" 57
r,
1
'
88
122
110
120
I I
138
206
21
234
006
T40
CLOCK
Tao
T120
T160
T200
T40
T240/0
Tao
T120
ij
;,>
a. SCU Addressing
I
I
I
I
I
J
o
BUS GOOD
/
1
I
I
<,
2'1
..I
I
I
".
........ \.
l .. i/.i
.;1
. .. . .. .. . >
>.
k ...
......:
.I . . .
I
I
'-
;;:::..
:?
I
Figure 6-23. Detailed Microprocessor SCU Addressing and ALU Path Timing
6-29
BUS
BUS
The Controller interface (CTl-l) consists of specialpurpose registers. counters and support hardware
organized to perform the sequencing and data transfer
functions between the SCU and the Controller. A block
diagram of these elements is shown in Figure 6-24_ The
CTl-1 is under direct control of the SCU Control Program.
Data transfer operations within the SCU are initiated
when the CPU transfers a command to the SCUrequiring
such a transfer. Data transfers between the Controller
and the SCU are initiated by read and write commands:
.....
BUS OUT
..
.
CE COMMUNICATION
~
S
T
0
R
A
G
E
------
a. Read Commands
------
b. Write Commands
Write commands are those commands which
cause data to be transferred from the SCU to
the Controller.
TAG OUT
TAG GATE
SEl HOLD
BUS
0
N
T
R
BUS IN
0
N
T
R
0
l
---
---
-"
---SYNC IN
o
N
T
R
----
LINE
RECEIVERS
NORMAL END
UNSEl ALERT 1
SELECT ACTIVE
---
TAG VALID
"
---
SYNC IN
SEL ALERT 1
CHECK END
SEL ALERT 2
RECYCLE
DTC = 0
6-30
Select Hold
CE Communication
Tag Valid
The SELECT HOLD line rises during any select tag and
remains up to maintain selection of a Controller and/or
Drive. The line stays up until the end signal of the last
operation to be performed on the Controller and/or Drive
is received and acknowledged (see Figure 6-26 for timing
relationship).
Select Active
Sync Out
The SYNC OUT line is used to validate and deskew the
Bus Out bits during data transfers from SCU to Controller. It is also used during data transfers from the
Controller to SCU to check the data count (see BUS
OUT/SYNC OUT waveforms of Figure 6-27 for timing
relationship).
Response
This line indicates acknowledgement of a Normal End or
Check End condition for extended (Read/Write)
operations.
Recycle
Tag Gate
Selected Alert 1
This line indicates an unusual condition (Equipment
Check) in the selected Controller or Drive. This line is
Reset by a Check Reset or Controller Reset operation
performed by the SCU.
Selected Alert 2
The SELECTED ALERT 2 line indicates the detection of
Index in the selected Drive. This line will not be active
unless a Drive is presently in operation (i.e., an Operate
Up tag (decode 8B) has been issued after selection).
Unselected Alert 1
One line used for diagnostic purposes only.
Bus In
Data from the Controller or Drive during a Read operation, as well as ECC conditions or error information, are
transmitted to the SCU by means of the Bus In lines. This
bus consists of nine lines: eight bits plus parity.
The SCU has the responsibility of deskewing Bus In
information except during read data transfers.
BUS OUT
BUS OUT
TAG OUT
II
TAG GATE
I
I
SELECT HOLDI
I
~,
II
100
NSEC
l- X
I
SYNC OUT
,I
--t
I
100
NSEC
\ .. MIN ..
l.I
DRIVE TAGS
-700 NSEC MIN
CONTROLLER TAGS
-100 NSEC MIN
'II
. MIN
,..
MIN
~:..
S~YN~C~I~N_ _ _ _ _ _~I
100
NSEC
60 NSEC
..
I..
MIN .. 1
125 NSEC""'_ _ __
155 35 NSEC
MIN
..:..
..I
LI_ _ _ _ _ _ _ _ _ _ _ __
CO Register
The CO Register generates the tag out bits for the
Controller along with SELECT HOLD and CTL TAG GATE
for control of the file. The register can be loaded from
either the D Bus or the T Bus.
Check End
CHECK END indicates that an abnormal ending condition
exists. The abnormal condition is presented on Bus In
along with proper parity during the duration of CHECK
END. For Read or Write operations, CHECK END stays on
and BUS IN maintains proper parity until the Storage
Control acknowledges the receipt of the abnormal end
status information with the RESPONSE line. CHECK END
is used for extended operations only.
co
co
co
co 2
SE
SELECT QUENCE TAG
BUS 0
OUT
OUT
co
TAG
BUS 3
co
TAG
BUS 4
co
TAG
BUS 5
co
TAG
BUS 6
co
TAG
BUS 7
The tag out bits (0, 3-7) have odd parity generated to be
sent with the tag bits to the Controller.
6-31
DO Register
The DO Register is llsed when transferring data to the
file In the write mode. or used to define the command to
the Controller in conjunction with the tag out bits defined
by the CO Register. The register can be loaded from
either the 0 Bus or the T Bus.
DO .REGISTER BIT ASSIGNMENTS
DO 0
DO 1
DO 2
DO 3
DO 4
DO 5
DO 6
D07
BUS
OUT
BUS
OUT
1
BUS
OUT
2
BUS
OUT
3
BUS
OUT
4
BUS
OUT
5
BUS
OUT
6
BUS
OUT
7
DIO
Dll
DI2
DI3
DI4
DI5
DI6
DI7
BUS
IN
0
BUS
IN
1
BUS
IN
BUS
IN
3
BUS
IN
4
BUS
IN
BUS
IN
BUS
IN
7
RWC Register Bit 2 Gate Bus In. This bit is used to gate
data from the Read Buffer Register into the 01 Register at
Register Time during a Read Mode or command sequence. The data transfer takes place with or without
TAG VALID, NORMAL END, or CHECK END.
MCM
1 23
000
SELECT SELECT
ALERT 1 ACTIVE
CHECK
001
DI
BUFFER
CHECK
010
01 1
TAG
VALID
(NOT
USED)
SYNC IN
UNEXP.
END
SELECT
ACTIVE
CHECK
(NOT
USED)
CE
ALERT
DTC 0
DTC 1
DTC 2
DTC 3
DTC 4
DTC 5
DTC 6
DTC 7
DTC 8
DTC 9
DTC 10
DTC 11
DTC 12
DTC 13
DTC 14
DTC 15
NORMAL CHECK
END
END
GATE
DO TO
WRITE
BUFFER
CTL
RECYCLE
GATE
BUS
IN
ALLOW
RESPONSE
CLOCK
DTC
UP
CTLI
READ
MODE
CTL-I
WRITE
MODE
CHANNEL
INTERFACE
CHECKS
6.5 FE INTERFACE
~:~~~~EF~~~CK - - - - t l..~
INPUT CARDS
6.5.1 General
The FE (Field Engineer) interface contains the logic
required to manually address. load. start and stop the
SCU during maintenance procedures. The logic required
to control and display diagnostic routines and errors.
while in the In-line or Off-line mode. is also contained in
the FE Interface
FROM
MICR O
PROCESS OR
TIMING
ERROR
LIGHT
DRIVERS
..._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..~~
VCf>02
DISPLAY
SELECTION
LOGIC
VC502
ROLLER BAR
INPUT CMDS
FROM FE
DIAGNOSTIC
CONTROL INDICATOR
SIGNALS TO FE
SELO.1.2.3
SIGNALS TO
I-SWITCH
DRIVERS
SW O-SW 7
es o-es
VC501
DATA. PARITY
DISPLAY
STROBES
SEL 0 1 2 3
PRESENT/LAST
ADDRESS
REGISTER
VD500'
LOAD START
ADDR.
SEL 0 1 2 3
START
ADDRESS
REGISTER
START ADDR
VD501'
LOAD A.
SEL 0 1 23
STOP A
ADDRESS
REGISTER
--
LOAD B
SEL 0 1 23
STOP B
ADDRESS
REGISTER
VD500-
MACHINE:
CONTROLS
FROM FE
TOGGLE
SWITCH
LOGIC
ILATCHESi
VD502
VC504
VD503'
ADDRESS
COMPARISON
CIRCUITS
STOP B ADDR
,
ADDR BITS F ROM
MICROPROCE SSOR
LJISPLA'
REGISTER
STOP A ADDR
VD500'
VD
TO INPUT
CARDS
CS O-CS 7
SWO-SW 7
ROLLER BAR
SWITCH
INTERFACE
DIAGNOSTIC
INDICATOR
DRIVER AND
MD 2 REGISTER
VC
MACHINE CHECK
ERROR SIGNALS
TO FE
IID500-
LOAD ADDRESS
INPUTS FROM FE
TOGGLE
SWITCH
LOGIC
(GATING)
cs O. CS 2
TO INPUT CARDS
VC502
VC504
6-33
and the channel issues a Selective Reset (raises SUPPRESS OUT and drops OPERATIONAL OUT). If
OPERATIONAL IN is down when the error is detected,
the SCU raises REQUEST IN. Then in response to
COMMAND OUT In the SCU-initiated sequence. the SCU
raises DISCONNECT IN and the channel follows with a
Selective Reset.
these bits are false. the SCU Microprocessor is functioning properly. When anyone of these error bits is set,
the status of all 16 bits (0-15) is frozen as well as the
failing address (27-39) associated with the error(s). If the
active error bit is MULTIPLE WCS ERROR (1), the failing
WCS error-correcting parity pattern is. also frozen (1623). If the active error bit is A Bus, B Bus or T Bus parity
error (2-4), then MCK bits 40 through 43 point to the PCB
(GA GB, GC or GO) which contains the source register
associated with that particular parity error. MCK bits 25,
26 and 44 through 47 are Check-2 errors.
BIT
DEFINITION
CHC PARITY ERROR
CHC Register contains wrong parity error
MULTIPLE WCS ERROR
A
Illuiliple (noncorrectablel
WCS
ERROR
CLASS
DISCRETE
DISPLAY
CKl
None
CKt
RAM
Indicator
accessing
CKl
CKl
CKl
T Bus
Indicator
BRANCH ERROR
a Miscompare of address parity and incrementer
parity if increment cycle.
b
Miscompare of address parity and SR parity if
B (ADR = SRI cycle.
c. Detection of simultaneous Branch Set and
Increment Set signals.
CK-l
BRNCH
Indicator
IMPL ERROR
During hardware IMPl. one of the following
conditions was detected:
a. Single Track Seek was not completed within
one second.
b A sync byte was not found in the FD read
data within one second.
Read overrun.
Sixteen occurrences of:
1 No TRACK = 0 decode (after TRACK 0 line
from FD valid). or
2. Parity error detected on FD Read Data
CKl
ALU ERROR
a. Miscompare of duplicate ALU outputs including
D = FF and carry conditions.
b. Miscompare of latched 0 Bus with the
ALU output.
CKl
BIT
A Bus
Indicator
10
B Bus
Indicator
ERROR
CLASS
DISCRETE
DISPLAY
BR MPXR ERROR
Miscompare of parity generated for a register
at the output of the BR Multiplexer
with the parity bit previously stored for that
register.
CKl
BRNCH
Indicator
PS ERROR
Miscompare of duplicate PS registers.
CKl
PAGE
Indicator
CKl
TRANS
Indicator
DEFINITION
for
DISCRETE
DISPLAY
DEFINITION
26
CK2
(in SCAN
only)
CKl
40
GA PCB
The PCB containing the source register for an
A Bus. B Bus, or T Bus panty error IS the
GA PCB.
CKl
GA
Indicator
2739
the
ERROR
CLASS
BIT
Roller
position
11
SUBROUTINE ERROR
Miscompare of SR parity and address parity
parity for C(LD.SR.+I) or B(LD.SF.+I).
CKl
BRNCH
Indicator
41
GB PCB
The PCB containing the source register for an
A Bus parity error is the GD PCB.
CKl
GB
Indicator
12
CKl
ECC
Indicator
42
GC PCB
. The PCB containing the source register for an
A Bus or T Bus parity error is the GC PCB.
CKl
GC
Indicator
13
CKl
BUFF
Indicator
43
GD PCB
The PCB containing the source register for an
A Bus parity error is the GO PCB.
CKl
GO
Indicator
CKl
BUFF
Indicator
44
FD READ ERROR
CK2 or
CK-l (if
IMPL)
14
buffer
accessing
access
parity.
15
CKl
16.23
FAILING Pl-PS
The a-bit error correcting parity pattern associated
with a multiple or single WCS error (MCK 1
OR MCK26).
CK-lor
CK-2
24
SELECTIVE RESET
Indicates that channel has issued a Selective
Reset (Microprogram checks this bit in the reset
procedure to distinguish between General and
Selective Reset).
25
IMPL
Indicator
ALU
Indicator
a.
b.
c.
BUFF
Indicator
45
CK2
(for diagnostic
purposes only)
FD SEEK ERROR
a. A Seek was not completed within one
second. or
b. A TRACK
0 Read decode was not found
within two sectors after the TRACK 0 line
from the FD went active.
46
FD NOT READY
A time delay signal which should be 57
seconds in duration after FD power is initiated
47
CK2 or
CK-l (if
IMPL)
CK2
FDD
or
NOTE:
1111 MCK Ill!" co111ll! displayed through SET DISPLAY of MCK register (microprogram display).
6-35
GLOSSARY OF TERMS
ADDR. ADRS
ALU
AM
Address
Arithmetic Logic Unit
Address Mark
B
BAR
BI
BO
Branch
Buffer Address Register
Bus In
Bus Out
I/O Instruction Base Address
Register Location
B1
C
CAR
CAW
CBR
CC
Count
Cylinder Address Register
Channel Address Word
Channel Buffer Ready
Chain Command. Channel Byte Count.
Condition Code
C.C
CD
CCW
CE
CHC
CHF
CHNL
CI
CK
CKD
CLK
CMD
CP
3672.21-0001-10/75
CPU
CT
CTL
CTL-I
CUDI
0
DC
DCC
DDM
DE
DEV
01
DL
DO
DTC
0
1
Data
Data Counter
Disconnected Command Chaining
Disc Drive Module
Device End
Device
Device Interrupt
Data Length
Data Out
Data Transfer Counter
I/O Instruction Displacement
ECC
EOB
EREP
ERP
FO
FOC
FDD
FE
FIDS
FLO
FSR
Flexible Disc
Flexible Disc Control
Flexible Disc Drive
Field Engineer
Fault Isolation Diagnostic System
Field
Field Service Representative
SCTR
SCU
SEQ
SERDES
SLI
SR
SW
Sector
Storage Control Unit
Sequence
Serializer /Deserializer
Suppress Length Indicator
Subroutine
Switch
R
RN
RAM
RST
R/W
RWC
R03
Record
Record n
Random Access Memory
Reset
Read/Write
Read/Write Control
Registers 0 through 3
No Operation
TIC
TR
TRK
Transfer In Channel
Transmit Request
Track
OLTEP
OP
UC
UE
Unit Check
Unit Exception
P
PCI
PLO
PS
Problem State
Program Control Interrupt
Phase Locked Oscillator
Page Select
VFO
W
WCS
Wait State
Writable Control Storage
QE
Queue Empty
J.L
Gn
HA
HAR
H.H
Gap n
Home Address
Home Address Register
Head Address (two bytes)
10
ILC
INCR
I(M)PL
Identifier
Instruction Length Code
Increment
Initial (Micro) Program Load
K
KL
M
MCK
MPXR
MUX
NO-OP
G-1
COMMENTS FORM
3672.21-00/0001
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