Cortex Resource Guide 2010

FALL 2010/SPRIN G 2011 ARM
R E S O U
R C
G U
w w w .d ig ik e y .c o m /c o rte x
CORTEX
I D
DigiKey_Cortex2010_Cover_Layout 1 10/14/10 10:15 AM Page 2
Digi-K ey
In tro d u c tio n
Digi-K ey and the ARM Cortex

An I n tro duc tio n to th e D igi-K ey C o rtex Reso urc e G uide, by D av e D o h erty ,
V ic e P residen t, Semic o n duc to r P ro duc ts, D igi-K ey C o rp o ratio n
AR M
in-stock and available for purchase at

our definitive one-stop-shop for tools0
www.devtoolsxpress.com.
processors are
some of the
most ubiquitous processors in the tech
industry, with more than 1v billion
ARM-based devices bundled in products over the past years. We know that
many of you are responsible for the
groundbreaking products that have
been designed using these devices.
The media attention on the past

ARMx, ARMz and X Scale dominance
has been eclipsed in the past three
years by the rise of the Cortex Core.
Like the saying goes--t h i s i s n o t y o u r
f a t h e r ' s O l d s m o b i l e --and neither are
the Cortex generation of chips that drive the automotive,
mobile and industrial world you helped create.
All predictions point to the Cortex design-ins as surpassing
devices built on earlier ARM cores. The sixth Cortex Core,
the M4, released earlier this year, will be used in digital
signal control, and has been licensed by five of the
industry s leading semiconductor companies. The M4 can
be used alone as a DSC or combined as a dual-core with
other Cortex-based devices like the Cortex-M0 MPU for
more robust and full-featured applications.
We believe this Digi-K ey Cortex Resource Guide is the
industry s most definitive volume on the ARM Cortex.
Most of the industry s leading semiconductor suppliers
that license and manufacture devices based on the ARM
Cortex Core are in this volume and are currently on
Digi-K ey s line card.
Hundreds of the development tools that support these
devices are also contained in this reference guide, and are
www.digikey.com/cortex Fall 2010/Spring 2011
With this unequaled level of support,

it will come as no surprise to you that
Digi-K ey is one of the world s leading
ARM Cortex-based device distributors.
It will also come as no surprise that
once again we are reaching out to you,
the engineer, to offer design support
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In addition, Digi-K ey is the only
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We hope that these resources, together with our reputation
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W i t h Re g a r d s ,
Dav e Doherty
V ice President, Semiconductor Products
Digi-K ey Corporation
Cortex Resource Guide
DigiKey_Cortex2010_1-5_CortexRes ou rc eGu id e2010-2011 10/14/10 10:31 AM Page 2
C ON TEN TS
CONTENTS
6
8
The ARM Cortex F amily

An introduction to the ARM Cortex Families that
form the core of the devices in this Resource Guide.
B y G le n n Im O b e r s te g , E m b e d d e d D e v e lo p e r
23
H arv esting the F uture of Mobile
27
U nderstanding the I ns and Outs

of Standard I nterfaces
Dev eloping ARM Cortex -M Class

Processor-based Sy stems
This paper evaluates microcontroller prototyping
systems (MPS) available from K eil, and its suitability
for Cortex-M class processor-based hardware and
software development environments. B y P u r u
Mi s h r a , Ma r k S a u n d e r s , a n d Ma r k O n i o n s , ARM
16
Y ou are debugging an application in flash memory,

when the reaction time of the system becomes so
slow that debugging becomes impossible. The
system has used all the hardware breakpoints and
the debugger has switched to low-level stepping.
What now?
B y D i r k Ak e m a n n , S E G G E R Mi c r o c o n t r o l l e r
Dual Processing with the ARM

Cortex -M4 DSC and Cortex -M0 MCU
An interview with Geoff Lees, V ice President and
General Manager of Microcontrollers, N X P, on the
N X P Cortex roadmap, including the introduction of
the Cortex-M4 and the Cortex-M0 Sub-system.
B y G le n n Im O b e r s te g , E m b e d d e d D e v e lo p e r
11
20
32
Reducing H ousehold Energy U se

through ARM Powered Smart Meters
Using the power-efficient Cortex-M processors, ARM
and their partners are developing a new range of
smart, all-digital metering devices. B y L o r e n Y e e , ARM
36
2 Cortex Resource Guide
Improvements in batteries have lagged behind

the increasing requirements of other components
inside the mobile phone, but other technologies
have emerged to deliver on the promise of alwayson mobility. B y S t e p h a n e C o r d o v a , S T - E r i c s s o n
In this article, various standard interfaces are highlighted along with suggestions on how they may
differ among embedded chip vendors.
B y C l a y T u r n e r , J a m e s D o u b l e s i n , L a w r e n c e Ro n k
a n d S te v e K ip is z , T e x a s In s tr u m e n ts
Shifting the Balance of Power

To address the embedded market s demanding
appetite for more performance with less power
for low-power design, Freescale Semiconductor
introduces the K inetis Cortex-M4 microcontrollers.
B y P a u lo K n ir s c h a n d D o n n ie G a r c ia , F r e e s c a le
S e m ic o n d u c to r s
Break ing F lash Barriers: Debugging

Embedded MCU Applications
A is for Android and Acceleration9

The Cortex-A8 is running the Motorola Milestone.
Designed in partnership with Google, the Milestone
delivers high-speed Web and voice-activated search
and GPS. B y J a n H o w e l l s , ARM
Cortex -M0 Silicon Suppliers

Company
N X P LPC1100
N X P LPC1102
N X P LPC11C00
Dev ice F amily

Microcontroller Family
C ON TEN TS
Cortex -M0 Dev elopment K its

Page
40
42
44
Product Name wDescription

NXP L PC1100w11C00w1102 Dev elopment K its
LPCX presso Low-Cost Development Platform
Embedded Artists LPCX presso Base Board
Page
z0
z0
Cortex -M3 Silicon Suppliers
Cortex -M3 Dev elopment K its
Company
Atmel
Cypress
Energy Micro
Energy Micro
Fujitsu
N X P
N X P
N X P
STMicroelectronics
STMicroelectronics
STMicroelectronics
Texas Instruments
Toshiba
Atmel AT91SAM3U w3S Dev elopment K its

SAM3S-EK Evaluation K it
SAM3U-EK Evaluation K it
z1
z1
Cy press PSoC 5 Dev elopment K its

PSoC v Development K it
PSoC v FirstTouch Starter K it
z2
z2
Energy Micro EF M32GwT Geck o Dev elopment K its

EFM32 Gecko Starter K it
EFM32-G2xx Gecko Development K it
EFM32-G8xx Gecko Development K it
z3
z3
z3
NXP L PC1300 Dev elopment K its

LPC1343 X presso Low-Cost Development Platform
LPC1300-Stick
Embedded Artists LPCX presso Base Board
LPC1300 Evaluation Board
zv
zv
zv
zv
NXP L PC17 00 Dev elopment K its

LPC1x00 Evaluation Board
LPC1xw8 mBed Development Board
LPC1xw8 Development K it
zw
zw
zw
Dev ice F amily

Page
ATz 1SAM3U/3S Microcontroller Family 48
PSoCv
v0
EFM32 Tiny Gecko
v1
EFM32 Gecko and Giant Gecko
v2
FM3 Family
v3
LPC1300 Microcontroller Family
v4
LPC1x00 Microcontroller Family
vw
v8
STM32F Microcontroller Family
w0
STM32L Microcontroller Family
w2
STM32W Microcontroller Family
w4
Stellaris
wv
TX 03 Series of Microcontrollers
ww
Cortex -M4 Silicon Suppliers: Coming in 2011

Company
Freescale
Freescale
Freescale
Freescale
N X P
Dev ice F amily

K inetis K 20 Microcontrollers
K inetis K w0 Microcontrollers
Page
x0
x2
x4
xw
x8
Cortex -A8 Silicon Suppliers

Company
Texas Instruments
Texas Instruments
Texas Instruments
Dev ice F amily

Sitara AM3vx Microprocessors
OMAP3v30/2v Processors
Sitara AM3xx Microprocessors
Page
84
8v
8w
Cortex -R4 Silicon Suppliers

Company
Dev ice F amily
Texas Instruments TMSvx0 Safety Microcontrollers
Page
88
STMicroelectronics STM32 Dev elopment K its

STM32-comStick
STM32-PerformanceStick
STM32 Starter K it
STM32E Starter K it
STM32F103E Starter K it
STM32 Evaluation Board
STM32F10xC Starter K it
MCBSTM32C Evaluation Board
STM32 Evaluation Board . uLink-ME JTAG Adapter
STM32 Evaluation Board . uLink2 JTAG Adapter
STM3210B Starter K it
STM32 Primer
STM3210C Starter K it
STM3210E Evaluation board
STM3210B-EV AL Evaluation Board
STM3210C Evaluation Board
zx
zx
zx
zx
z8
z8
z8
z8
zz
zz
zz
zz
100
100
100
100
DigiKey_Cortex2010_1-5_CortexRes ou rc eGu id e2010-2011 10/14/10 10:32 AM Page 4
C ON TEN TS
Cortex -M3 Dev elopment K its (continued)

Tex as I nstruments Stellaris Dev elopment K its
LM3S811 Evaluation K its
LM3S2z wv CAN Evaluation K its
LM3S1z w8 Evaluation K its
LM3S3x48 Evaluation Boards
LM3Swz wv Ethernet Evaluation K its
LM3Sz Bz 0 Evaluation K its
LM3S8z w2 Ethernet . CAN Eval K its
LM3Sz Bz 2 Evaluation K its
Toshiba TX03 Dev elopment K its
MCBTMPM330 TX 03 Evaluation Board
I ntegrated Dev elopment Env ironments

Page
101
101
101
101
102
102
102
102
103
Cortex -A8 Dev elopment K its

F reescale iuMX Dev elopment K its
i.MX v1 SBC
i.MX v1v StackableUSB Computer (Linux-ready)
i.MX v1v StackableUSB Computer (WinCE-ready)
104
104
104
Tex as I nstruments AM35 x x w37 x x Dev elopment K its

Sitara AM3v1x EV M
TI AM3v1x eX perimenter K it
TI AM3xx Evaluation Module
10v
10v
10v
Tex as I nstruments OMAP35 x x Dev elopment K its

OMAP3vx Torpedo Development K it
Beagle Board
Beagle Board-xM
TI Z oom OMAP3v Development K it
10w
10w
10w
10w

Embedded Workbench
K eil RealV iew MDK Basic
K eil RealV iew MDK
Code Composer Studio v4.0 Microcontroller Edition
Code Composer Studio v4.0 Platinum Edition
Page
108
108
108
10z
10z
JTAG Probes
K eil ULIN K pro Debug and Trace Unit
K eil ULIN K 2 USB-JTAG Adapter
SEGGER J-Link
SEGGER J-Link Pro
SEGGER J-Trace
Signum JTAGjet
Signum JTAGjet-OMAP3
Signum JTAGjet-Trace with Trace Buffer (1MB, 2MB, 4MB)
110
110
110
110
111
111
111
111
Cortex -R4 Dev elopment K its

Tex as I nstruments TMS5 7 0 Dev elopment K its
TMSvx0 USB Development K it
TMSvx0 Development K it
10x
10x
The Digi-K ey Fall 2010/Spring 2011 ARM Cortex Resource Guide is published by
Digi-K ey Corportation.
Copyrights0The masthead, logo, design, articles, content and format of is Copyright
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may be reproduced in part or in whole without express permission, in writing, from
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Trademarks0DIGI-K EY and the Digi-K ey logo are trademarks of Digi-K ey Corporation.
ARM is a registered trademark of ARM Limited. All other brands or product names
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IN C. Cortex-M0, Cortex-M3, Cortex-M4, Cortex-A8, and Cortex-R4 are registered
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Cover and section pages image iStockphoto.com/Inok
FALL 2010/SPRIN G 2011 ARM CORTEX
RESOU RC E
GU I D E
ARTI C L ES
I n t r o d u c t i o n t o ARM
C o rte x
Digi-K ey
The ARM Cortex F amily

An in tro duc tio n to th e ARM C o rtex Famil ies th at f o rm th e c o re o f
th e dev ic es in th is editio n o f th e Reso urc e G uide.
AR M
is the industry1s
leading provider of
32-bit embedded RISC microprocessors.
ARM processors are licensed by the
majority of the world1s leading
semiconductor manufacturers, who
together have shipped in excess of
18 billion processors since the company
was formed in 1z z 0.
ARM offers a wide range of processor IP based on a

common architecture delivering high performance together
with low power consumption and system cost. This
energy-efficient performance is enhanced by ARM Physical
IP, development tools and the broad ARM ecosystem of
third party systems, design support, software and training
providers which provide a complete solution for products
based on the ARM architecture.
it is an open architecture that provides

unparalleled levels of compatibility and
design reusability, combined with
superior performance, compact code
density and low cost per DMIPS.
The Cortex family of processors
provides Digi-K ey s ARM core-based
device and their customers with a range of solutions
optimized for specific markets and applications across a
spectrum of performance and functionality. This underlines
ARM1s strategy of aligning technology around specific
market applications and performance requirements.
The ARM Cortex family comprises three series, which all
adhere to the ARMvx architecture and implement the
Thumb -2 instruction set to deliver the highest
performance in cost sensitive embedded markets0
The ARM architecture is the most widely used 32-bit

embedded RISC solution in the world. All ARM processors
share this architecture, ensuring that developers gain the
maximum return on software development as they move to
higher performance processors.
ARM Cortex -A Series, applications processors supporting

complex OS and multiple user applications.
The latest reports show that ARM s market share of the

embedded RISC microprocessor market is more than xv
percent, with ARM Partners shipping almost 4 billion ARM
processor-based devices per year. It has excelled because
ARM Cortex -M Series, deeply embedded processors

optimized for very cost sensitive microcontrollers and
FPGA.
ARM Cortex -R Series, embedded processors for deeply

embedded real-time systems.
An overview of each of the members in the series covered

by this resource guide is detailed on the following page.
w Cortex Resource Guide
DigiKey_Cortex2010_6 -7 _L ayou t 1 10/14/10 10:35 AM Page 2
Digi-K ey
C o r t e x - M 0 Pr o c e s s o r
The ARM Cortex-M0 processor is the smallest, lowest
power and most energy efficient ARM processor available,
in an area of under 12K gates. The exceptional low power,
small gate count and code footprint of the processor
enables MCU developers to achieve 32-bit performance at
an 8-bit price point, bypassing the step to 1w-bit devices.
Cortex -M3 Processor
The Cortex-M3 processor provides a high performance,
low-cost platform for a broad range of applications and can
be configured to meet the exact requirements with a N ested
V ectored Interrupts Controller (N V IC), configurable debug
and trace options and optional MPU. In addition, the Wake
Up Interrupt Controller (WIC) enables the system to be
placed into an ultra low-power retention mode.
Cortex -M4
The ARM Cortex-M4 processor is the latest embedded
processor by ARM specifically developed to address digital
signal control markets that demand an efficient, easy-to-use
blend of control and signal processing capabilities.
I n t r o d u c t i o n t o ARM
C o rte x
C o r t e x - A8 Pr o c e s s o r
With the ability to scale in speed from w00MHz to greater
than 1GHz, the Cortex-A8 processor can meet the
requirements for power optimized mobile devices needing
operation in less than 300mW and performance optimized
consumer applications requiring 2000 Dhrystone MIPS.
Cortex -R4 Processor
The Cortex-R4 processor supports substantial
configurability during synthesis to optimize the processor
for different applications and is capable of running at clock
speeds of up to v00MHz on typical wvnm processes. The
Cortex-R4F processor provides an additional, synthesisoptional Floating-Point Unit (FPU) optimized for single
precision processing.
Cortex ARMv7
ARMv6
ARMv5
ARMv4
I N TERV I EW
Ar t i c l e
An I n terv iew w ith G eo f f L ees, V ic e P residen t an d G en eral Man ager, Mic ro c o n tro l l ers, N X P
Dual Processing with the ARM Cortex -M4

Digital Signal Controller and Cortex -M0 MCU
by Glenn I mObersteg, E m b e d d e d D e v e l o p e r
N X P
has released a
raft of new ARM Cortex-based
products since ESC West in
April of this year. Recently,
Glenn ImObersteg, President
of Embedded Developer,
caught up with Geoff Lees,
V ice President and General
Manager, Microcontrollers,
N X P, in Sunnyvale, California
to discuss their 2011 roadmap
Geoff Lees, V P and General
and the Cortex-M4.
Manager, Microcontrollers, N X P
G le n n : T h e r e s b e e n a lo t o f a c tiv ity a t N X P s u r r o u n d in g n e w
ARM P r o d u c t s s i n c e y o u a n n o u n c e d t h e C o r t e x - M4 a t E S C .
Geoff0Our Cortex product range has gained momentum in the
last six months, and we re coming up to an extensive series of
product launches for the fall embedded events. We1ve got a
number of new Cortex-M0 and -M3 products in the low-power
area coming out, offering improvements in both dynamic as well
as stand-by power. Customers today are more and more looking
to reduce the dynamic power component of high performance
systems in order to achieve stringent energy efficiency targets.
We also announced becoming a lead licensing partner for
Cortex-M4 with ARM at Embedded World, leading to Embedded
Systems Conference in Silicon V alley where we showed first
functional silicon of the Cortex-M4, and we ve been working on
a lot of innovative new ideas in that series of products.
ARMz 2w family has been using since 200w, but we1ve spent more
in the area of active leakage reduction. We1ve also improved our
flash interface technology on that process and are seeing major
performance increases up to 1v0MHz and higher.
G le n n : S o th e L P C 1 8 0 0 is th e fir s t p r o d u c t in y o u r n e w 9 0 n m
F la s h p r o c e s s .
Geoff0Y es, and it s the industry1s highest performance
Cortex-M3. We1ve implemented our new 2vw-bit wide flash
memory interface with a dual bank safe re-programming
architecture for the first time, continuing the performance
advantage of N X P s high-performance zero-wait flash. So,
you re now able to execute from one flash bank while
reprogramming the other. In the first product range, we1ll
have up to one megabyte of Flash memory consisting of two
flash banks of up to v12 kbytes each. In future products we1re
planning to be able to offer two megabytes and later four
megabytes of memory.
G le n n : Iv e h e a r d th e n e w L P C 1 1 0 2 is th e W o r ld s s m a lle s t
3 2 - b it m ic r o c o n tr o lle r. W h a ts h a p p e n in g th e r e ?
Geoff0The LPC1100 family is already allowing us to offer some
incredible innovations0the LPC1102, for example, is the first
32-bit MCU in a 2 x 2 mm wafer level chip scale package. It
combines an amazing v channels of A to D, two serial channels
and multiple timers in a tiny package. But even more incredible
is the fact that it offers 32 kbytes of flash and 8 kbytes of SRAM
in such a small package.
G le n n : L e ts d is c u s s y o u r n e w 9 0 n m ( n a n o m e te r ) p r o d u c t lin e ,
f i r s t . T h i s i s b a s e d o n t h e C o r t e x - M3 , c o r r e c t ?
G le n n : T r a d itio n a lly , th e o n ly tin y m ic r o c o n tr o lle r s a v a ila b le h a v e

b e e n 8 - b it p a r ts w ith 1 K o f p r o g r a m c o d e a n d u p to 2 5 6 - b its o f
r a m in th e s a m e p a c k a g e s iz e .
Geoff0That s right -- The new LPC1800 Cortex-M3 series is

designed using our new z 0nm Flash process. This is an
extension of our z 0nm low-power process that our LPC3000
Geoff0That s right and the difference is dramatic0the LPC1102

offers thirty-two times more code and data memory size by comparison in conjunction with 32-bit performance.
DigiKey_Cortex2010_8-10_CRG 10-10-2011 10/14/10 10:36 AM Page 2
I N TERV I EW
We now have plans for a much wider range of chip scale

derivatives with the addition of more analog mixed signal
functionality, covering a wide spread of digital power control and
conversion applications. We re also working on offering more
innovative peripherals, as well as much more on-chip memory,
but maintaining all the benefits of our M0 family0low-cost,
ultra-low power, reduced code size and easy-to-use--all of those
are proving invaluable to our customers in adopting the M0, and
the ease at which our customers can now migrate to 32-bit is
quite amazing. This has been the most successful and rapid
adoption of any of our microcontroller series.
G l e n n : Ar e y o u p l a n n i n g o n e x p a n d i n g y o u r l o w - c o s t t o o l s
s o lu tio n s to k e e p p a c e w ith th e in tr o d u c tio n o f th e s e n e w
d e v ic e s ?
Geoff0We recently extended our LPCX presso development tool to
include coverage for all the LPC1x00 range, so that it now that
supports all of our Cortex-M0 and -M3 families. Within the last
12 months 10,000 new users have started development with our
Eclipse-based LPCX presso tools, and we can easily see from this
the widespread popularity of open-source development increasing in the future.
Our LPC1xw8-based mbed rapid prototyping tool is primarily
targeted at new users, fast prototypes, market demonstrations,
and areas where developers are looking at spending less time on
code generation and validation, and much more exploration of
new applications of embedded technologies. We are very much
focused on increasing the on-line database of applications and
content, as well as improving the usability of mBed.
G le n
to la
th a t
tie s .
n : L a
u n c h
m e rg
W h a
s t S p r in g
a h y b r id
e b o th D
t p ro g re s
a t
fa m
S P
s h
E S C , th e
ily o f D S
fu n c tio n a
a v e y o u m
p r e s s r e p o r te d th a t N X P is g o in g
C 's ( d ig ita l s ig n a l c o n tr o lle r s ) ,
l i t i e s a s w e l l a s MC U f u n c t i o n a l i a d e ?
Geoff0The Cortex-M4 series is being launched as the LPC4000.

Importantly, this not just another Cortex-M4, in fact it s the first
time we1ve introduced the concept of dual-core processing to the
microcontroller area. Bringing high performance digital signal
controller applications within range of Cortex-based microcontrollers, it includes DSP instruction expansion as well as single
precision floating point, combined with a Cortex-M0 based peripheral subsystem. All of these features are very suited to power
control and conversion applications such as motor control,
ac-dc converters, robotics, automation and industrial applictions.
In addition, other signal-processing applications such as multichannel Audio coding/de-coding and voice recognition/synthesis
will benefit from enhanced DSP performance, really right across
the application range in the MCU market.
Ar t i c l e
G le n n : Its n o t th e fir s t D S C in th e m a r k e tp la c e , is it? B o th T I a n d

F r e e s c a le h a v e in tr o d u c e d D S C s in th e p a s t.
Geoff0N o, it s not the first DSC, but it is the first time that the
digital signal control element has been based on ARM Cortex
architecture and as a result developers will be able to take full
advantage of the wide range of ARM software and development
tool ecosystem including optimized DSP libraries for the M4
processor. In contrast to symmetric dual core implementations,
such as dual Cortex-Az examples hitting the news recently, this is
really an asymmetric approach to integrating a Cortex-M0 based
peripheral processor subsystem. The idea is to be able to take
care of a lot of hardware intensive I/O tasks as well as regular
housekeeping, and users can then take much better advantage of
the Cortex-M41s true DSP performance.
G l e n n : S o t h e L P C 4 0 0 0 D S C d u a l c o r e C o r t e x - M4 p l u s - M0
c o m b i n e s t h e D S P a n d MC U f u n c t i o n a l i t y o f t h e M4 w i t h t h e
M0 s p e r i p h e r a l h a n d l i n g . I s a n y o n e e l s e o f f e r i n g t h i s a p p r o a c h ?
Geoff0Cortex-M0 is such a small processing core, around 12k
gates, but it offers a lot of advantages for enhancing a userconfigurable peripheral sub-system. We re going beyond just
setting up programmable peripherals on their own to a point
where we have a local 32-bit processor dedicated to software and
hardware based I/O tasks.The M4 can just as easily be used for
conventional MCU duties, in a very similar way to our LPC1800
M3 family, for example. But one of the characteristics of digital
signal control applications compared to regular microcontroller
operation is intensive math and control computation as well as
streaming signal processing for waveform analysis, synthesis,
coding and compression.
In those applications you want to be able to dedicate processor
performance to the application for a higher percentage of available bandwidth than in typical MCU applications. At this point no
other ARM partners who have announced M4 licenses have
stated that they re offering dual core systems, so we haven1t seen
any other products that include peripheral sub-system processors. We believe that this is a powerful new approach for realtime control processing, which allows many customers to
approach the flexibility of a custom ASIC solution without major
cost or engineering design effort.
G l e n n : Ar e t h e r e a n y o t h e r i n n o v a t i o n s i n t h e n e w L P C 4 0 0 0 s
p e r ip h e r a l s u b - s y s te m ?
Geoff0To take advantage of the addition of the M0 processor,
we1ve added a new range of configurable peripherals. Peripherals
that go far beyond the regular range of functionality today.
For example, state configurable timers that have an awareness
of the sequence and state of operations and that can benefit
from more extensive processor interaction. So a 32-bit processor
can be combined to form a closed-loop current-control system in
DigiKey_Cortex2010_8-10_CRG 10-10-2011 10/14/10 10:36 AM Page 3
I N TERV I EW
hardware, and software control loops for PID-based speed and

field control algorithms. Advanced motor control is an area that
we specifically designed the sub-system to address efficiently.
We1ve also developed a special I/O cell for the sub-system, so
that the M0 (or M4) has access to and control of dedicated I/O.
Functionality, such as sequential serial and parallel operations,
can be combined with the M0 core to develop virtual peripherals
far more effectively. This can be used to generate a wide range of
serial communications with special or unique protocols without
requiring ASIC hardware. One example that is now possible from
the overall architecture is an audio codec software and hardware
application with transmission via a dedicated x.1 channel I2S
port. The whole peripheral processing sub-system has really been
optimized around the capabilities of the M0 sub-processor.
G le n n : D o e s th e d u a l p r o c e s s o r a r c h ite c tu r e c a u s e p r o b le m s fo r
s y s te m d e v e lo p m e n t? W h a t to o ls d o e s a n e n g in e e r n e e d to
d e v e lo p to ta k e a d v a n ta g e o f th e L P C 4 0 0 0 c a p a b ilitie s ?
Geoff0As I said earlier, the advantage of a dual core M4 and M0
processor architecture is that they can be programmed at the
same time using the same integrated development environment.
This uses the same project overview, the same compiler chain
and the same debugging tools.
Y ou can look at both of the cores separately, as the initial
architectures are intended for a relatively low degree of software
interaction, or as the architecture develop further, and tool
vendors respond, there will increasingly be options for simultaneous interactive debugging.There is also the opportunity for a lot
of software re-use, from a wide range of MCU functionality and
application code that has come from our own discrete Cortex-M0
LPC1100 family and can now be utilized again in the high-performance dual-core series. If you take our current LPCX presso
development tool available for under m30, you can immediately
connect it into current and future LPC1800 and LPC4000
products via the standard SWD connector. This is the big benefit
derived from having a single scalable ARM architecture and a
range of compatible Cortex cores.
Ar t i c l e
G le n n : W h a t o th e r s u p p o r t m a te r ia l h a v e y o u c r e a te d to g e t
c u s to m e r s u p to s p e e d w ith th e L P C 4 0 0 0 ?
Geoff0We have prepared a number of white papers during recent
months, such as working with the Q uad SPI dataflash interface,
the state configurable timers and the serial parallel GPIO,
and those will be available at the product launch. From the very
successful LPC1100 Cortex-M0 family, we1ve already developed
a number of dedicated applications in areas such as keyboard
scan, serial communication handling for example and those
applications and the code can be taken directly and run on the
M0 sub-processor in the LPC4000.
G le n n : W h e r e w o u ld u s e r s g e t th e m o s t b e n e fit fr o m th e
L P C 4 0 0 0 D S C s o lu tio n , a n d w h e n w ill th e y b e a b le to s ta r t?
Geoff0The LPC4000 will make it a lot easier to integrate DSP
functions and DSP assisted control to increase the performance,
efficiency and range of regular microcontroller-based power
control applications. Typically today an engineer would have to
add a DSP-based solution in addition to a general purpose MCU.
The reason why DSP alone does not cover this type of application
is that generally DSP1s don1t come integrated with high
bandwidth communication peripherals such as Ethernet 10/100,
high-speed USB . PHY , Controller Area N etwork interface.
Another area where Cortex processor solutions are much
stronger than DSP devices is in interfacing to a wide range of
advanced color graphics touch-screen LCD controllers.
This is all going to be in the sub-m10 price range depending on
the memory configuration. For example, the first LPC4000
products will have up to 2w4 kbytes of SRAM, extending the
current Cortex microcontroller range significantly. N X P will be
presenting and demonstrating the LPC4000 series at Electronica
2010 and at ARM TechCon 2010, and product and tools will be
available from Digi-K ey shortly afterwards.
ARM
Ar t i c l e
Dev eloping ARM Cortex -M Class

Processor-based Sy stems
by Puru Mishra, Spencer Saunders, and Mark Onions, ARM
Reprinted by permission of IQ Magazine
ardware and software development using Cortex-M class

processors requires considering a range of IP and tools
options very carefully. Prototyping of a Cortex-M based system
typically requires a) putting together required hardware component
IP of the design in an emulation environment, b) validating the
system, c) running relevant benchmark applications using application
development, debug and trace tools, and d) fine-tuning or even
extending the design until the product requirements are met. Each
stage requires taking well-informed decisions both from IP and
tools perspective. For instance, the diversity of processors from ARM
within the Cortex-M class processor family, and availability of a range
of peripherals including ARM Primecell peripherals, mandates that
functional IP blocks with correct performance point be chosen in
order to design an optimal MCU solution for a given application.
Choosing a wrong microcontroller solution can be a costly mistake.
Hence, a hardware prototyping environment that makes evaluation
of the most optimal MCU solution possible in a simple and costeffective manner is important.
an on-board FPGA or structured ASIC chip to port third party or

in-house peripheral IP. Once the evaluation has been done by running
benchmarking programs, the most optimal system can be chosen.
This approach, however, is not suitable for many reasons. The
hardware development boards are not available for new Cortex-M
processors. It takes at least six months to a year for a standard MCU
development board to be available in the market. Also, managing
separate boards requires a lot of duplicate effort, thus impacting the
cost as well as the development time of the project.
An emulation environment is often used for software development

until the actual silicon is available. This enables software
development to start in parallel with the hardware development,
thus helping accelerate the time-to-market. The challenge here is
to use a Cortex-M class processor-based emulation environment that
is tested, pre-validated and easy to use. A reliable and easy-to-use
environment with wide range of standard peripheral interfaces is
desirable in this case.
The most suitable option, however, would be a hardware development system that provides access to relevant ARM IP Cortex-M
processors and ARM PrimeCells with simple terms and conditions,
specifically for evaluation purposes.
Another approach would be to take all the hardware IP including

ARM Cortex-M processors, Primecell peripherals IP and third party
IP, port them on an FPGA or structured ASIC to create a single
system where an exhaustive evaluation can be carried out. However,
access to the RTL of the IP could prove to be a huge upfront
investment. Also, licensing the IP would typically require going
through many standard legal processes that are often very
time consuming. Therefore, this option is not suitable.
Finally, if hardware IP and tools for the development of a prototyping

system are pulled from separate sources, the development may not
only take longer, but also result in extra investment, significantly
increasing the development cost. Therefore, a single vendor that can
provide a complete range of IP and tools is desirable.
Configuration and V alidation of a H ardware Dev elopment Sy stem

A system using lots of third party IP requires a lot of effort in
validation. Even when all the IP is available, integrating and validating
the system will significantly add to the development cycle and delay
the product development. Therefore, IP supplied in a Cortex-M
hardware development system with pre-validated and tested example
systems will help accelerate the development time. The pre-validated
systems can also allow applications and libraries to be developed and
tested in an easy and quick manner.
H ardware Sy stem Ev aluation

Before finalizing the components for a Cortex-M class processorbased MCU system, the evaluation of Cortex-M processors, ARM
Primecell peripherals and third party peripherals in a hardware
development environment is a requirement. There are multiple
options available in the market today in order to carry out this
evaluation.
Today, a Cortex-M based system implemented on an FPGA can run at

speeds of around v0MHz. This is similar or very close to the speed of
a typical embedded microcontroller in silicon. Therefore, an FPGA
based prototyping and evaluation system is ideal. Without sacrificing
on the performance, it provides the flexibility of easily configuring the
hardware components on the board. This enables fast development
of an optimal Cortex-M class processor-based MCU solution.
A traditional approach is to use separate hardware platform boards,

each based on different Cortex-M class processor, together with
11
DigiKey_Cortex2010_11-15_L ayou t 1 10/14/10 10:39 AM Page 2
ARM
Others F actors
When developing a Cortex-M based system, a developer is required
to use a number of development tools for various tasks. For instance,
an FPGA-based development system would require the use tools to
a) design and configure the hardware system, b) download the
hardware system on FPGA, c) download application code into the
system, d) debug application code, e) trace execution of application
code, and f) optimize application code. With the large number of
tools required, it is desirable to choose a vendor that can provide the
complete flow of development tools as well as providing a hardware
development system.
Further, while evaluating a development system it is also important
to look at the list of interfaces available on the system. It is important
that a system with a complete set of interfaces be chosen. It is
equally important that there is an option in the system that allows
users to design their own interfaces and extend the system, either
using on-board resources (FPGA) or using companion boards that
can be attached to the main board.
K eeping the factors discussed above in mind, this paper evaluates
the Cortex-M based Microcontroller Prototyping System (MPS)
available from ARM. The ARM K eil MPS provides a simple system
to aid evaluation and prototyping of an embedded design based
on ARM Cortex-M class processors. It allows early evaluation of
Cortex-M class processors enabling selection of the correct
processor for an application. The simple and flexible hardware
development environment, combined with an integrated software
environment to compile and debug software, makes this a suitable
solution from concept through to final silicon.
Ar t i c l e
Microcontroller Prototy ping Sy stem (MPS)

The MPS is based around two Altera Stratix III EP3SLv0 FPGAs. The
first holds the processor and memory subsystem (CPU), including
w4MB N OR Flash and 8MB SRAM; the second FPGA is for hardware
development (DUT). The processor FPGA is encrypted to allow a
simple click-through license agreement (EULA) to be used for all
supported processors. This
means one can begin
evaluating the selected
processor quickly and
without the need for access
to the processor RTL.
The CPU FPGA can also
accept a non-encrypted
image, so once the processor
RTL has been licensed,
licensees can make
modifications and update
the CPU FPGA with their
own image.
To aid prototyping and allow the development work to start quickly,
the MPS has an array of peripheral interfaces. Some are supported
via the example system while others have just the physical interfaces,
to be used together with in-house IP which would be programmed
into the DUT FPGA. The list on the next page (Table 1) details the
peripherals and level of support.
ARM
Ar t i c l e
Peripheral
H wW Support
SwW Support
Note
Childboard
Product Number
F eatures
Debug/Trace
ULIN K 2, RV I/RV T
MDK , RV DS
CPU FPGA
Connector LED board
HC-COLEv2
MDK , Boot Monitor
CPU FPGA
Five 2wpin 0.1 pitch IDC headers. Each signal

connected to LED and these can be turned on/off
with jumpers
2 Channel Gbit Ethernet
HC-ETH2v2
Two N ational DP838wv phy s with magnetics.

MII, GMII and RGMII interface supporting
10/100/1000BASE-T
N OR Flash (32bit w4MB) CPU FPGA

SRAM (32bit 8MB)
1 wait state CPU FPGA MDK , Boot Monitor
CPU FPGA
UARTs
PL011 RTL
Selftest, Boot Monitor
DUT FPGA example
ACz x
PL041 netlist
Selftest
DUT FPGA example
SD/MMCard
PL181 netlist
Boot Monitor
DUT FPGA example
SDRAM
HC-SDRv2
2vwMB organized as 32M xw4-bit at 120MHz
Character LCD
RTL
DUT FPGA example
DDR2
HC-DDR
1GB of DDR2 RAM, product in development
LEDs/switches
RTL
DUT FPGA example
N AN D
HC-N AN D4v2
USB 2.0 HOST/OTG
USB Chip
N one
N X P ISP1xw1
Four 1GB devices with each with a separate 8-bit

interface on the childboard connector
Ethernet 10/100
Phy only
N one
Requires MAC IP
CAN
Phy only
N one
Requires IP
Requires IP
LIN
Phy only
N one
FlexRay
Phy only
N one
Requires IP
V ideo (up to X V GA)
Phy only
N one
Requires IP
T abl e 1
In addition to the list of peripherals shown in Table 1, the DUT FPGA

has a Childboard interface to allow the expansion of the I/O features
of the system. This is a simple interface of FPGA I/O pins together
with power pins enabling users to use off the shelf boards or develop their own for custom requirements. A selection of Childboards
are available from Gleichmann (Table 2) that enables addition of I/O
Synchronous SRAM and HC-FRMEMv2

N OR Flash
Two synchronous flow through N tRAM 1Mx32

(4MB) 8.vns access time and two N OR Flash
memories 1wMx32 (w4MB) x0ns access time
T abl e 2
functions to the MPS, ranging from simple I/O breakout boards

with LEDs and headers to complex gigabit Ethernet Phys or
DDR2 memories.
To accelerate evaluation and development, an example system is
shipped with the MPS for the DUT FPGA. This FPGA image supports
most of the features on the board and is supplied with the example
software and hardware design files necessary to rebuild both the
software and hardware image of the FPGA.
13
ARM
The next section of the paper will cover the design flow to rebuild,
download and execute both the DUT FPGA image and software for
execution on the MPS.
H ardware Design
The example system is supplied as a mixture of RTL and netlists (for
high value IP) allowing users to rebuild the FPGA image. The netlists
for some IP blocks ensures that only a simple click-through license is
required. The top level architecture above the IP blocks is RTL-based
to enable easy modification.
Users need to edit and modify the RTL to add or remove features as
required. They can use the free Altera Q uartus II Web Edition tools
to synthesize, and then place and route the design for the FPGA.
The example scripts used can easily be modified and contain the
synthesis and timing constraints required to rebuild the FPGA image,
and they can be used in the GUI or on the command line for
automated builds.
Downloading and Configuring the MPS
Users have now created the FPGA image as a .SOF file for the MPS.
This can be downloaded into the MPS system via the HPE-Desk
software supplied with the MPS. This is a Windows-based application
that downloads images to the FPGA via the USB port on the front
of the MPS.
The HPE-Desk offers two options for downloading the image into the
Ar t i c l e
DUT FPGA. The first is download sof file to System FPGA which is a
fast method of downloading directly into the FPGA.
However, this method is volatile meaning that when the system is
rebooted, the FPGA is configured with the current system Flash
image and any changes made to the FPGA image will be lost. This
method is useful to save time during prototyping where users would
like to quickly test small changes to the FPGA image.
The second option takes longer but is non-volatile as the image is
downloaded to the system Flash. The download to System Flash
Memory option is ideal for making more permanent changes to the
system image and should be used later in the development phase or
to make milestone changes to the system.
The second feature of the HPE-Desk is the ability to route different
clock signal outputs from the FPGA back into the FPGA s clock
inputs. This is basically a cross switch allowing users to drive clock
sources (shown as rows) to clock inputs (shown as columns) in the
FPGA. The default configuration is suitable for the example system,
but if users wish to change the PLL in the DUT FPGA to create
different clock frequencies for the processor and AHB lite interface
then they can use this to switch between clocks without having to
rebuild the FPGA images, saving time.
Software Design
Once the hardware image is downloaded and working on the MPS,
users can begin developing and running a software application. This
is a straight forward exercise as the MPS and its example system are
fully supported by the K eil software development tools.
The MPS is supplied with an evaluation version of MDK -ARM
(Microcontroller Development K it) which is code size limited to
32K B, and the evaluation version can be upgraded to a full version
of MDK -ARM by contacting K eil or our local distributor. The MPS
also includes a ULIN K 2 adapter which allows the MDK -ARM to
download application code to the target and debug it in JTAG or
SWD via the PC s USB port.
ARM
Ar t i c l e
Project Setup and Configuration

MDK -ARM contains a Device Database which allows users to easily
setup and configure their project. Within the Device Database select
ARM and the required processor [ Cortex-M3/M0] as the target
device and the required tool options and customized dialogs are
automatically configured. As users continue their application
development, only those options that are relevant to the selected
device will be displayed, thus preventing selection of incompatible
directives.
General Debug and Analy sis
The V ision4 IDE/Debugger offers a wealth of debug and analysis
tools to help users analyze and optimize their application code. In
the Debugger, the Watch Window displays the values of automatic
variables in the current function, the Memory Window displays
various memory areas, and the Serial Window provides a terminal
output for the on-chip UART. The Flexible Window Management
System introduced in V ision4 enables developers to use multiple
monitors and provides complete control over window placement
anywhere on the visual surface.
V ision4 includes a Logic Analyzer which records the values of
variables and peripheral I/O signals over time and displays them.
These signal values can be displayed in three different formats0bits,
showing outputs as a logic level 0 or 1; State, showing stage
changes of a value; and Analog, showing a graphical representation.
Cortex -M Class Processor Debug ) Trace

MDK -ARM and ULIN K 2 have extended features for debugging
applications running on Cortex-M3 and Cortex-M0 processor-based
systems using the standard JTAG, or the advanced Serial-Wire debug
modes. Additionally, Data Trace Windows provide information from
a running Cortex-M3 processor-based system for program data,
exceptions, variables and printf-style outputs. For example, one may
use the Trace Records window to view all the trace records captured
during the debug session, including overflows and timestamps; while
the Exception Trace windows show which exceptions have taken
place, including the number of times they have occurred and how
long the system spent handling these exceptions. Users may also
view printf-style debug or other program-specific information using
the ITM V iewer window or keep a track of the events in their
application using the Event Counter window.
Conclusion
This paper has evaluated the suitability of MPS for Cortex-M class
processor-based hardware and software development environment.
MPS provides a unique development environment that allows evaluation and then selection of the correct Cortex-M processor for a given
application. It allows easy and fast prototyping of Cortex-M processor-based systems. A programmable and pre-validated platform, it is
tailored to the needs of designers working on Cortex-M based designs. Applications and libraries can be developed and tested before
the silicon is available thus accelerating the time-to-market. Looking
at the requirements of the industry today, MPS provides an ideal
choice for both hardware and software system development based
on Cortex-M class processors.
Design Support Serv ices

Digi-K ey s Design Support Services (DSS) team of appllications engineers and
technicians provides general information and complimentary project-specific
assistance. DSS provides service to engineers ranging from one-time contacts
regarding product recommendations to ongoing prototype-to-production
design support.
DSS strives to guide the customer through the design process while achieving
the best solutions and, ultimately, streamlining the design cycle. The DSS team
provides support and advice on system design, aids with product selection and
development tools, and provides assistance with other applicable design issues.
Additionally, members of the DSS team produce application notes, webinars, and
instructional videos. The DSS team is available from 8030 am--v000 pm CST via
telephone, email, and web-conferencing software.
w w w .d ig ik e y .c o m /d s s
1v
F re e s c a le
Ar t i c l e
Shifting the Balance of Power

by Paulo K nirsch and Donnie Garcia, MC U S y s t e m s E n g i n e e r i n g , F r e e s c a l e S e m i c o n d u c t o r a n d
Danny Basler, MC U P r o d u c t Ma r k e t i n g , F r e e s c a l e S e m i c o n d u c t o r
F reescale s low-power technology pushes ahead with K inetis

ARM Cortex -M4 MCU s
h e e m b e d d e d m a r k e ts d e m a n d in g a p p e tite fo r m o r e
p e r fo r m a n c e w ith le s s p o w e r c o n s u m p tio n n o w e x te n d s
a c r o s s a w id e s p e c tr u m o f p o r ta b le a n d w a ll- p o w e r e d a p p lic a tio n s .
T o a d d r e s s th is d e m a n d , F r e e s c a le c o n tin u e s to p u s h th e b o u n d a r ie s o f lo w - p o w e r d e s ig n . T h e la te s t b e n e fic ia r y is its n e w K in e tis
l i n e o f ARM C o r t e x - M4 m i c r o c o n t r o l l e r s . S a m p l i n g i n t h e f o u r t h
q u a r te r o f 2 0 1 0 , K in e tis r e p r e s e n ts th e fir s t b r o a d - m a r k e t m ix e d
s i g n a l MC U p o r t f o l i o b a s e d o n t h e n e w ARM C o r t e x - M4 c o r e , a n d
o n e o f t h e m o s t s c a l a b l e ARM C o r t e x - M4 MC U p o r t f o l i o s i n t h e
i n d u s t r y . Mu l t i p l e h a r d w a r e - a n d
s o f t w a r e - c o m p a t i b l e MC U f a m i l i e s
w ill o ffe r e x c e p tio n a l p e r fo r m a n c e ,
m e m o r y a n d fe a tu r e s c a la b ility
r a n g i n g f r o m 5 0 MH z , 3 2 K B f l a s h
d e v ic e s in u ltr a - s m a ll fo o tp r in t
Q F N p a c k a g e s , u p t o 1 5 0 MH z
d e v i c e s w i t h 1 MB o f f l a s h m e m o r y
a n d r ic h in d u s tr ia l- fo c u s e d p e r ip h e r a l s e ts . L o w - p o w e r h a s p la y e d a
c e n t r a l r o l e i n t h e K i n e t i s MC U
d e s ig n . T h is is r e fle c te d in th e u s e
o f F r e e s c a le s n e w 9 0 n m S p lit G a te
T h in F ilm S to r a g e ( S G - T F S )
p r o c e s s te c h n o lo g y a n d in a b r o a d
ra n g e o f g e n e ra l p u rp o s e a n d
a p p lic a tio n s p e c ific p e r ip h e r a ls th a t
c o m e p a c k e d w ith p o w e r s a v in g fu n c tio n s .
I n n o v a t i v e L o w - Po w e r Pr o c e s s
Te c h n o l o g y
Process technology is the basic building block of any
semiconductor product and a key factor in determining an MCU s
power consumption. K inetis MCUs are the first to take advantage
of Freescale s SG-TFS flash technology which, in addition to
offering extremely fast access times and high immunity to charge
loss, has been specifically designed to address the needs of
power-sensitive applications. In designing the SG-TFS bit cell,
1w Cortex Resource Guide
Freescale has utilized fast, low voltage transistors in the read path
resulting in a lower operating voltage range of 1.x1V to 3.wV . In
applications that utilize two 1.vV batteries, cell life deteriorates
rapidly once the 0.z V level is reached. This means that the 1.x1V
lower voltage limit translates into extended battery life versus
traditional MCUs that are typically limited to 2V or above. This
extended voltage range applies not only to the on-chip memories
flash, SRAM and Freescale s new FlexMemory (configurable, high
endurance EEPROM) but also to the analog peripherals, thereby
allowing continual signal measuring and conditioning even at the
lower end of the power curve.
The voltage characteristics of TFS
also contribute to reduced run
currents by allowing signals which
are switched at high speed to
operate at lower voltages (typically
1.2V ). Because run current is
proportional to C) V ^ 2) f, the
reduction in V is very beneficial
to the flash component of the
active current.
Re q u i s i t e Po w e r M o d e s
In the majority of battery-operated
applications the CPU spends most
of its time in reduced power or
sleep modes. It is therefore critical
that the MCU offers an attractive
selection of power modes,
wake-up sources, and start-up
times so designers can optimize peripheral activity and recovery
times to application requirements and in turn extract the most out
of the available energy source. Freescale has addressed this by
equipping K inetis MCUs with no less than 10 low-power run, wait
and stop modes accompanied by multiple wake-up sources (see
figures 1 and 2). Each run mode comes with a corresponding wait
and stop mode. Freescale also has introduced several low-leakage
DigiKey_Cortex2010_16 -19_CRG-2010-2011 10/14/10 10:41 AM Page 2
F re e s c a le
Ar t i c l e
Figure 2 : D esc rip tio n o f p o w er mo des
Figure 1 : C o mp ariso n o f p o w er mo des
modes and a new low-leakage wake-up controller to satisfy the

most aggressive power budgets.
When operating in run mode, the CPU executes code at full speed
and can achieve power consumption as low as 200 A/MHz. For
periods when maximum bus frequency is not required, the very
low-power run (V LPR) mode can be utilized. This limits the CPU
frequency to 2 MHz and places the internal voltage regulator in
standby mode while maintaining full peripheral and low voltage
detect (LV D) functionality. The power saving achieved in this
mode can be significant with V LPR LDD ranging from w00 A to
1 mA depending on the performance, memory and peripheral
configuration of the MCU.
Wait mode and very low-power wait (V LPW) mode are similar
to their equivalent run modes, except that the CPU is halted and
flash and FlexMemory programming is unavailable. With peripheral
interrupts enabled, the MCU is able to exit wait modes, perform the
scheduled task and then quickly revert to a low-power state. This
minimizes average power in applications that frequently toggle
between active and reduced power states. Depending on the bus
frequency, savings of between 30n and w0n of the run mode LDD
are achievable.
A variety of stop modes provide state retention and partial or full
power down of certain logic and/or memory. The low-leakage stop
(LLS) mode, the lowest power mode with a 4 S recovery time,
reduces the voltage to internal logic, minimizes leakage from
unused internal circuits and has a typical LDD range of 1.2 A
to x A. The very low-leakage stop (V LLS) modes go a step
further by powering down the internal logic, and optionally
the RAM memory, thereby eliminating leakage from unused

circuits. The differences between each V LLS mode relate to the
level of RAM retention. In V LLS3 mode all RAM is retained, in
V LLS2 partial RAM is retained and in V LLS1 no RAM is retained
but a 32 byte register file is available for storage of critical
application data.
A key low-power component of the K inetis MCU is the low-leakage
wake-up unit (LLWU) which acts as the wake-up monitor in all
of the low-leakage stop modes. The LLWU supports up to sixteen
external input pins (programmable as falling edge, rising edge
or any transition) and up to eight internal peripherals that can
be configured by the user as wake-up events. In the lowest power
mode several wake-up sources are available0low-power timer,
real-time clock, analog comparator, touch-sensing interface (TSI)
and several pin interrupts. Wakeup inputs are activated, if enabled,
once the MCU enters the LLS mode or any of the V LLS modes.
With clocks consuming as much as 40 percent of active power,
K inetis MCUs employ programmable clock gating for all modules.
This shuts down unused peripheral clocks in the run and wait
modes while maintaining the same levels of performance and
functionality. This is particularly important given the large number
of communications modules and timers that are offered on K inetis
devices. Power gating is also employed to shut off inactive
memories and logic, further reducing leakage currents.
K inetis MCUs include a low-power timer which adds further
flexibility by enabling continual system operation in reduced power
states. This can be used either as a generic timer or with the
on-chip comparators to count comparator output pulses. Finally,
a low-voltage detection (LV D) unit supports two low-voltage
detection trip points with four warning levels per trip point. It can
be configured to generate a reset or interrupt in the event of supply
voltage variations, thereby safeguarding memory contents and
MCU system states.
1x
F re e s c a le
Ar t i c l e
Several applications require the implementation
of keypad, rotary and slider user interfaces.
To support this, Freescale offers its Touch
Sense Software (TSS) Library which is fully
compatibility with its CodeWarrior Integrated
Development Environment (IDE). Among the
features included in the TSS library are smart
auto-calibration mechanisms to prevent
environmental issues, noise rejection
algorithms, an optimized buffer structure
enabling any arrangement of electrodes and a
PC GUI application for electrode characterization
that comes complete with demos and application examples.
L o w - Po w e r Se g m e n t L C D
Segment LCD displays are commonly used in
a range of power-sensitive applications for providing instructions,
monitoring system status, showing operational/functional progress
or giving results. In most systems, the LCD is powered at all times,
even in reduced power modes, to display status, battery condition
or just time-of-day information. It is therefore essential that the
power drawn by the LCD does not adversely affect battery life.
The K inetis K 30 and K 40 MCU families include a flexible segment
LCD controller that supports a wide range of 3V and vV LCD panels
with up to 320 segments, designed primarily for low-power
systems. These MCU families span from w4 K B to v12 K B of flash.
Figure 3: X trin sic to uc h sen c e in terf ac e l o w -p o w er mo de o p eratio n
L o w - Po w e r To u c h Se n s i n g
All K inetis MCUs include Freescale s new X trinsic touch sense
technology. X trinsic provides a modern alternative to traditional
mechanical push-button switches through the creation of touchactivated button, slider and rotary user interfaces. As well as
aesthetic appeal, touch sense interfaces offer design flexibility,
low maintenance and the ability to support a variety of sensitivity
levels and overlay surfaces. These advantages are driving their
adoption beyond the latest consumer gadgets into applications
such as home appliances, medical devices and industrial control
panels. The touch-sense input (TSI) module offers the added
benefit of being functional in all low-power modes with only
minimal current adder when enabled. This opens up touch
sensing to a wide range of battery-operated applications that
were previously inaccessible.
Within the TSI module is an internal periodic scan unit that has
separate scan intervals for low-power and run modes. This allows
the user to set long scan intervals for minimizing power consumption. Conversely, in run mode the scan interval can be reduced for
faster touch response.
As illustrated in figure 3, the TSI module has programmable high
and low capacitance thresholds within which the CPU remains in
sleep mode until a TSI event is detected. When a touch occurs,
the instantaneous electrode capacitance is detected to be out of the
threshold-defined range, which in turn issues a TSI interrupt and
quickly wakes up the CPU. Once the touch sense input has been
processed, the MCU is then free to return to its reduced power
state. The TSI module supports up to 1w electrodes/buttons using
a single pin per electrode without the need for external components, enabling reduced system cost. With a capacitance measurement resolution down to 0.02 fF, it can also be used with thick
glass, plastic and flexi-glass overlays. Furthermore, electrode
sampling integration and fault detection hardware increase system
robustness, an important consideration in noisy industrial
environments.
The LCD controller operates in all CPU modes of operation

including very low-leakage stop modes. Unless the chip is in
reset, the screen will display information without attention from
the rest of the MCU. A key feature is its ability to support blink
mode operation which allows desired segments to be turned on
and off at 1/8s, 1/4s, 1/2s, 1s, 2s, 4s and 8s intervals to either
draw attention to that part of the display or simply to conserve
power during the v0 percent off cycle. Because blinking is
performed in a small part of the LCD module, it too runs without
having to wake up the CPU, buses or the rest of the MCU. Blinking
to a blank screen turns all segments off, while blinking to an
alternate screen allows different display data to be shown during
the configurable blink period. With this function, the MCU can
achieve lower average power consumption by supporting LCD
blinking without exiting the low-power mode, as shown in figure 4.
Minimizing the number of external components also contributes to
increased system battery life. The LCD controller generates the
frontplane and backplane display signals with a charge pump that
requires only four external capacitors.
The data for the LCD is also held at the location closest to the
LCD at the pad cell. Rather than LCD data residing in registers deep
within the chip, this eliminates the drive necessary to overcome
loading between a centralized register and the I/O pins and allows
a reduction in the LCD driver voltage domain.
F re e s c a le
Ar t i c l e
guard against erroneous display readouts, and multi-purpose LCD

pins which support backplane, frontplane or GPIO functions.
En a b l i n g L o w - Po w e r So l u t i o n s
With the K inetis portfolio, Freescale is committed to delivering the
latest in low-power MCU innovation. This applies not only to the
MCU itself but also to the development tools and design resources
that enable it. K inetis MCUs will be supported by an extensive suite
of application notes, reference designs and training materials.
These will be supplemented by a powerful array of third party tools
including IAR Systems Embedded Workbench IDE, which incorporates innovative power debug and analysis tools. These features
provide the software developer with the ability to map key events in
the program1s execution in terms of their power consumption and
in turn modify their source code to fit their power profile.
Figure 4 : Segmen t L C D bl in k mo de timin g
Combined, these low-power features enable consumer, industrial

and wireless LCD applications that provide ultra-long life using a
variety of batteries, including AA, AAA, lithium coin and 3.wV .
Additional benefits of the LCD controller include the ability to
configure any LCD pin as either a frontplane or a backplane via
software allowing LCD design changes without the need for costly
hardware re-design, segment fault-detection capabilities which
Applications today demand more than just low-power. There is

frequent need for a broad set of performance, memory and
peripheral options as low-power becomes a critical need on
ever-larger numbers of end products. With the industry1s latest
low-power process technology, multiple low-power operating
modes that can be optimized for individual applications, a rich
suite of low-power enabled human machine interface peripherals
and a comprehensive enablement offering, K inetis MCUs are
ideally positioned to respond. For further information on K inetis
MCUs visit www.freescale.com/kinetis.
All the tools in this resource guide can be found at
Y our One-Stop-Shop for all y our Dev elopment

Tool needsu F ind, compare by price, features
and performance, and buy today 9
w w w .d e v to o ls x p re s s .c o m
1z
SEGGER M i c r o c o n t r o l l e r
Ar t i c l e
Break ing F lash Barriers:

Debugging Embedded Microcontroller Applications
by Dirk Ak emann, S E G G E R Mi c r o c o n t r o l l e r
Y ou are debugging an application in flash memory , when the reaction

time of the sy stem becomes so slow that debugging becomes impossibleu
The sy stem has used all the hardware break points and the debugger has
switched to low-lev el steppingu Dirk Ak emann look s at how to ov ercome
this and other barriers to debugging flash microcontrollersu
oday the number of programmers in the world is measured

in the millions and yet they are still spending a good part of
their life finding errors in their programs.
Within the embedded environment, while good programming

practices and the use of appropriate tools can reduce dramatically
the number of bugs that appear in compiled code, there will
inevitably be issues that appear only when the code is executed
in the target system. To track these down it is common to use a
debugger, a software tool that provides insight into the code
execution and the state of the software environment.
One of the most valuable tools within the debug environment is

the use of breakpoints. The idea is both simple and powerful0
when a program encounters a breakpoint it stops execution and
hands control to the debugging software. The debugger can then
display the status of the application environment (variables,
memory, stacks, registers, etc.) to help the developer discover
how the application has reached this state.
Once the cause of the bug is identified, changes can be made to
the code and the debug process restarted.
The host processor communicates with the target
microcontroller, and the standard
method is through the JTAG interface,
originally created for hardware
checking (boundary scan) and now used
also for software debugging and for
loading software into the target
microcontroller. With ARM based architectures, the device implementer may also offer
SWD (Serial Wire Debug) which uses only two
pins compared to JTAG1s five and Freescale products
usually offer BDM (Background Debug Mode.) Between the host
PC and the JTAG, or other interface, the physical connection is
usually an emulator.
This typically has a USB connection with
the PC and a ribbon cable to the target
board, and translates from one
environment to the other. (Emulator
is a name inherited from a previous
technology - no emulation takes
place.)
DigiKey_Cortex2010_20-22_CRG-2010-2011 10/14/10 10:44 AM Page 2
Memory and Debugging

Different memory architectures present different debugging
challenges, particularly when writing to memory requires extra
effort or is even impossible.
Debugging in RAM is fairly easy, since the debugger uses a simple
breakpoint instruction, which is as short as the shortest instruction
of the CPU. RAM allows for multiple reads and writes without any
noticeable effect.
Ar t i c l e
H ow Many Break points Do I Need?

For more detailed debugging many more breakpoints are needed.
Even just stepping over an instruction without single stepping
requires at least two breakpoints. This is because, as the system
hits a breakpoint and stops, the breakpoint is removed and a new
breakpoint is set at the next step in the program. The application is
restarted and runs until it hits the next breakpoint, when it halts
again. If the next step in the program is a branch, then each possible
branch requires a breakpoint. So a simple if() needs two breakpoints
while a typical switch() needs at least three; one at each case
with another at the default0instruction. Y et another breakpoint is
needed if the debugger needs to display the terminal output. If a
debugger tries to set more breakpoints than the microcontroller
can provide, the debugger will normally default to low-level-single
step execution, with a dramatic reduction in performance.
Adding breakpoints in the flash memory would seem a logical
move to overcome these problems, but flash presents its own
challenges.
Writing to flash needs code in RAM, and writing to flash when
the application is running can be difficult, particularly when the
application uses techniques to improve speed of code execution
or power consumption, like changing the CPU speed at run time.
Writing a breakpoint to flash, as with any flash write, may change
the contents of registers and RAM, destroying the evidence
needed for debugging. There are also problems of flash memory
speed and endurance (the physical life) when compared with
RAM. Unlike writing to RAM, where a write operation can address
a single memory location, when a flash write takes place a huge
block of memory (which may be up to w4k) has first to be
cleared and then written to.
T h e debugger h an ds o v er th e man agemen t o f break p o in ts to th e J -L in k

debug p ro be. Fo r a h igh -l ev el step th e debugger o n l y n eeds to issue
aSetB P ( ) -G o ( ) -C l earB P ( ) -seq uen c e to th e J -L in k .
However, since RAM is normally limited in microcontroller

systems, debugging in RAM is not always possible.
For ROM the microcontroller designers provided the hardware
breakpoints now commonly used for debugging in flash.
Hardware breakpoints simply compare the instruction pointer
with the breakpoint position and check whether the instruction is
actually called. If this is the case, the program is halted and the
debugger is started.
The hardware breakpoints are normally limited in number and in
capability. In ARMx or ARMz implementations there are only 2
watchpoints (ARM terminology for a hardware breakpoint). The
new ARM Cortex-M3 has w hardware breakpoints available.
T h is ex amp l e demo n strates h o w man y break p o in ts th e debugger n eeds f o r

a simp l e sw itc h ( ) -in struc tio n w h il e step p in g th ro ugh th e so urc e c o de.
21
N ormally setting even a single breakpoint would require this

write cycle. And flash has a finite life0typically after 100,000
writes to a flash memory cell the time it will retain data begins to
fall. For a microcontroller memory it is possible that specific cells
could reach this number of write cycles unless appropriate
measures are taken to avoid it.
Break point in F lash
These are not insuperable obstacles. SEGGER Microcontroller
supplies the J-Link JTAG emulator for a wide range of microcontrollers and has developed the optional FlashBP feature, which
allows developers using J-Link to use flash breakpoints as easily as
RAM breakpoints. It is designed to assist the developer to make the
best use of resources available and reduce the number of times flash
is programmed. (Reducing flash programming steps both speeds up
debugging and extends flash life.) During the debugging process, all
the resources of the microcontroller are available to the application
program; no memory is lost for debugging.
At the heart of the feature is a RAM code specifically designed
for setting flash breakpoints0when using this code on devices
with fast flash, setting and executing flash breakpoints is as fast
as setting breakpoints in RAM. There are occasions when hardware
breakpoints, even with their limitations, can be useful, for
example when stepping through code one source-level instruction
at a time. When they are appropriate, J-Link will use hardware
breakpoints or a mix of hardware and software breakpoints,
reducing the number flash write cycles.
There are a number of other performance enhancements used by
J-Link. Flash sectors are programmed only when necessary, usually
the moment execution of the target program starts.
Ar t i c l e
Where possible, J-Link locates several breakpoints in the same flash

sector0programming a single sector then sets multiple breakpoints.
And debugging does not consume memory, leaving all the
resources of the processor available to the application.
When single-stepping and the current instruction is already
breakpointed, the built-in instruction set simulator reduces the
number of flash programming operations. Without instruction set
simulation, the debugger needs to clear the breakpoint, step over
the current instruction and set the breakpoint back again. The
instruction set simulator allows instructions to be simulated or
emulated in RAM. Simulation creates the results of the breakpointed instruction.
If a register is set, or a memory area is moved, J-Link simply
executes this as if the instruction actually has been executed and
increases the program counter accordingly. Some instructions
cannot be simulated because their effect is unclear or system/
implementation dependent, such as a co-processor instruction. If
the instruction allows to be executed at a different place in memory,
J-Link will emulate the instruction. The emulation is executed by
copying the instruction with its arguments to RAM and executing the
instruction there.
Before flash programming takes place, the contents of memory and
registers are saved. This protects their contents against changes
when programming takes place.
Debugging in the target system will continue to be a significant
part of ensuing that a product functions as it should. It will never
be an easy task, requiring insight and professional skills from the
developer. The different elements of the J-Link toolkit and
FlashBP have been designed to allow the developer to select
those parts that will make the debugging task as simple and as
fast as possible.
ST- Er i c s s o n
Ar t i c l e
H arv esting the F uture of Mobile

by Stephane Cordov a, Ma r k e t i n g Ma n a g e r , An a l o g & Mi x e d S i g n a l B u s i n e s s U n i t , S T - E r i c s s o n
I t s been a great summer day , and y our mobile phone has play ed many
hours of music during this long day at the beachu I t s time to go home, and
y our battery is still fullu Sounds impossible with today s batteries and
dev ices? W ell soon this ex perience could be part of y our ev ery day reality u
mprovements in batteries have lagged behind the increasing

power requirements of other components inside the mobile
phone but other technologies have emerged to deliver on the
promise of always-on mobility. Power harvesting, the technique of
collecting alternative energy sources and managing them, has
rapidly evolved and is poised to be a key technology of future mobile
devices.
With over w billion subscriptions and more than 1 billion smartphones forecasted by most analysts in 2014, the incredibly fast
innovation of the past 10 years has put amazing new capabilities
in the hands of consumers. Devices are expected to offer faster
processors, bigger screens, and high quality cameras while being
always connected. The latest augmented reality applications, 3D
game or social network sites demand always more performance.
23
DigiKey_Cortex2010_23-26 _CRG-2010-2011 10/14/10 10:47 AM Page 2
ST- Er i c s s o n
But all the more, they need to achieve it with no need for a charge
every half day.
The semiconductor industry has made amazing progress in making
devices more efficient, and capable of delivering ever higher
performance at low power consumption. However, despite this
progress, the gap between the energy need and the energy available
is continuously widening.
Ar t i c l e
N ow lets s address the parts of the process which have seen little or
no improvements in the past five years are collection and to a larger
extent distribution.
Energy H arv esting
Energy harvesting (also known as power harvesting or energy
scavenging) is the process by which energy derived from external
sources is collected and stored. There can be a variety of energy
sources such as solar power, thermal energy, wind
energy, salinity gradients, and kinetic energy).
Frequently, this term is applied when speaking about
small, wireless autonomous devices, like those used
in wearable electronics and wireless sensor networks
(source0Wikipedia). Harvesting is interesting for the
wireless industry for two reasons0Firstly, it could
solve battery life problems and deliver more energy to
applications. Secondly, it contributes to reduce use of
carbon energy by using alternative green sources. In
this article we will focus on the first benefit.
Figure 1 : As dev ic es ev o l v e, th e gap betw een p o w er budget an d battery c ap ac ity in c reases
Although being a relatively new technology, energy

harvesting is already used in other industries. The
sensor industry is the forerunner0today standalone
sensors are using alternative energies such as solar
or wind for unlimited use. The proliferation of solar
lamps for the garden is a good example of how
widespread this technology has become. Innovative
use-cases are starting to appear as well with devices
using kinetic energy while you run to recharge your
music player.
To address the energy gap relying only on battery evolution is not

enough. Following the trend of development of sustainable energies
in other industry sectors, the wireless industry is also looking at
alternative sources and power harvesting to solve the battery life
issue of future devices.
Power management is an essential and integral part of any mobile
device. There are three angles from which the power cycle in a mobile
device can be addressed0collection, distribution and consumption.
Consumption is an area where we ve seen some great improvements
in recent years, especially with the ARM architecture. As smartphones evolved so did highly clocked processors which today
offer attractive performance, smoother applications, high-quality
multimedia and support complex use cases. However, as we ve seen
in the PC world, there is a design point where pushing frequency
beyond the sweet spot does not bring the right returns. This is
where scaling performance through multi-processing becomes a
must. With designs such as the recent multicore processors offered
by ARM (e.g. Cortex-Az ), mobile platforms can deliver a perfect
balance between scalable performance and low-power consumption,
making an ideal solution for thermal and cost constrained devices.
Using a dual-Cortex-Az, a platform like ST-Ericsson s U8v00 can
achieve 120 hours of audio playback and 12 hours of HD video,
numbers which are today not even expected from standalone music
or video players.
Figure 2 : Mul tip l e en ergy so urc es av ail abl e f o r use in f uture mo bil e
dev ic es
Integrating the collection of alternative energy sources to a

mobile device brings a number of challenges. External look o
feel, form-factor, cost, portability, are only a few of the inherent
constraints brought by the device. If we add in the different maturity
levels of the technologies and the need for co-existence then it s
easy to understand that this is not a simple problem.
ST- Er i c s s o n
Energy
Description
Mark et status
Contactless supply Wireless chargers can become an alternative to the standard

charger. One wireless charger can be used for all mobile
products in a family.
Commercialized
Kinetic energy
Development
Energy from movement or vibration. The increased use of

MEMs in mobile is reinforcing this harvesting concept.
Ar t i c l e
Solar has already made some appearances in mobile; in the Samsung Blue
Earth, a solar panel is added on the
back of the phone to be used as a
charger for the battery. The phone may
be used in developing countries with
poor access to electricity.
Development, potential The next step is to allow the solar

commercialization
energy to power the different parts of
2012/2013
the phone and not only be used to
charge the battery. When improving
Micro-battery
A good candidate for mobile application. Small size and flexible Research
the energy path and distribution, one
use make it very easy to use.
can use specific energy sources to
power selected areas of an application.
Thermal harvesting Thermal harvesting is really interesting as it is a source of
Research
energy available everywhere, inside the phone, at ICs level or
At the Mobile World Congress this
system level and outside the phone.
year, ST-Ericsson demonstrated a useRadio waves
Would be a new area for investigation. We all are surrounded
Research
case called endless mp3 playback.
by RF microwaves and being able to harvest this energy would
Using only solar energy, the system
generate a significant source of energy for a mobile application.
would directly power an audio component to deliver mp3 playback without a
Solar energy
Commonly used in other industries and introduced in
Commercialized
need for the device s battery (figure 3).
production in wireless. A big potential lies in transparent flexible
solar cells.
It is important to understand that
T abl e 1
energy harvesting is unpredictable in contrast to a battery or USB
charger. One cannot predict the amount of energy in the environment
Multiple technologies and energies are being investigated for power
from which it is harvested. Therefore, the distribution part of the
harvesting in mobile (see figure 1 and table 1), but one of the most
system must be smart and built in order to0
advanced is solar. Despite low efficiency of current photovoltaic
- Gather the harvesting energy when it is present with the best
cells, the use of solar energy in houses and multiple other fields has
possible efficiency
clearly proven the interest and popularity of this technology. In the
- Mix the harvesting energy with the other usual energy
coming years we will see photovoltaic cells with higher efficiency
- Partially (when possible) replace entirely the standard energy
and more attractive cost enabling a wide deployment in mobile
(battery) to fully power a use case as explained above with the
equipments.
music playback.
Fuel cells
Fuel-cell technology is an interesting source of energy which

has been demonstrated but is not yet ready for broad use in
mobile and industrialization.
Figure 3: E n dl ess mp 3 p l ay bac k usin g so l ar as th e o n l y en ergy so urc e
2v
ST- Er i c s s o n
Ar t i c l e
Once a better distribution mechanism achieved, one can only

imagine the possibilities opened by energy harvesting. All basic
use-cases could be powered by different types of alternative
technologies and your wireless device could recharge while you are
walking or standing anywhere in the sun.
All the sources are available in or around mobile phones and can be
used to supply or charge. Every source brings its set of advantages
and disadvantages and probably none will yet replace the battery.
However, being able to collect and manage them all in a smart way
will make the difference. The optimal energy harvesting system
should be simple, automatic and smart with the capability to supply
energy to the right components when and where required. The
harvesting can therefore not be considered as a standalone
solution, but must be integrated in the whole process of saving,
managing and distributing the power to the application.
Semiconductors have also made tremendous progress on the ICs
power consumption, but also on the software managing the power
in the platform in a wise manner.
Conclusion
While the current solutions are not yet optimal, there is a bright
future for the vision of the always connected device. Thanks to
advances in power management and processors we ve reached
amazing performance with low power consumption in today s
devices. Energy harvesting, is one of the next steps in making
phones complete power efficient systems. As the technologies
evolve, challenges will have to be solved; how will each energy
source be integrated into the device or what cost will it add to the
bill of materials.
With the growth of mobile broadband and the vision of v0 billion
connections in 2020, the environmental impact of the wireless
industry will be closely watched and power efficiency will be a
measurable factor of it.
During 2010, we should see the first energy harvesting components
coming to market; ST-Ericsson is actively involved in developing
energy harvesting technologies and believes it is a critical area for
a future green wireless industry.
Design Support Serv ices

Digi-K ey s Design Support Services (DSS) team of appllications
engineers and technicians provides general information and
complimentary project-specific assistance. DSS provides
service to engineers ranging from one-time contacts regarding
product recommendations to ongoing prototype-to-production
design support.
DSS strives to guide the customer through the design process
while achieving the best solutions and, ultimately, streamlining
the design cycle. The DSS team provides support and advice
on system design, aids with product selection and development
tools, and provides assistance with other applicable design
issues. Additionally, members of the DSS team produce
application notes, webinars, and instructional videos. The DSS
team is available from 8030 am--v000 pm CST via telephone,
email, and web-conferencing software.
w w w .d ig ik e y .c o m /d s s
Te x a s I n s t r u m e n t s
Ar t i c l e
U nderstanding the I ns and Outs of

Standard I nterfaces
by Clay Turner, James Doublesin, L awrence Ronk a n d Stev e K ipisz , T e x a s I n s t r u m e n t s
Matching an applicationrs performance, power, memory and interface req uirements

to a specific embedded processor can be a daunting task for designers since similar
sy stems can v ary significantly u Although ARM processors are av ailable in a doz en
v ariations, sy stem designers seldom find a operfect fitou
I n this article, v arious standard interfaces are highlighted along with suggestions
on how they may differ among embedded chip v endorsu U nderstanding the basic
interfaces can help designers prioritiz e which ones should be on-chipu H owev er,
while standard interfaces serv e a v aluable purpose, there is also an additional
need for on-chip interfaces to be customiz ed to prov ide additional on-chip
resourcesu The article describes two of these peripheral block su
he universal serial bus (USB) interface was initially

developed to connect personal computers to peripherals.
Over time it has become popular for industrial and infrastructure
applications. Human interface devices (HIDs), such as keyboards,
mice and oscilloscopes, typically employ the USB interface meaning it must be supported by the system1s embedded processor. The
most effective way to accomplish this is with an on-chip peripheral.
In addition to HIDs, two other device classes can be utilized in

industrial and infrastructure applications. USB communication
device class (CDC) was designed for modems and faxes but also
supports simple networking by providing an interface for transmitting Ethernet packets. Similarly, USB mass storage device (MSD)
targets hard disk drives and other storage media.
The USB 2.0 specification requires the host to initiate all inbound
and outbound transfers. The specification also defines three basic
devices0host controllers, hubs and peripherals.
USB 2.01s physical interconnect is a tiered-star topology with a hub
at the center of each star. Each wire segment is a point-to-point
connection between the host and a hub or function, or a hub
connected to another hub or function.
The addressing scheme used for devices in a USB 2.0 system

allows for up to 12x devices to be connected to a single host.
These 12x devices can be any combination of hubs or peripherals.
A compound or composite device will account for two or more
of these 12x devices.
Although USB 2.0 is likely the first choice in industrial and many
infrastructure applications, USB On-the-Go (OTG) is deployed
when peripheral devices need to communicate with each other
without any involvement from the host. To accommodate peerto-peer communication, USB OTG introduced a new class of
devices containing limited host capabilities for two peripherals
to share data.
The OTG supplement defines a new handshake called the host
negotiation protocol (HN P). Using HN P, a device connected as a
default peripheral can request that it become the host. This allows
the existing USB 2.0 host-device paradigm to provide peer-to-peer
communication. A session request protocol (SRP) is also defined.
USB1s popularity and status as a solid standard makes it possible
for embedded processor vendors to offer software libraries that
target specific USB functionality and therefore significantly trim
2x
development time. Instead of writing their own code to implement

the interface, system designers simply make a function call.
The libraries should be certified as having passed USB device
and embedded host compliance testing conducted by the USB
Implementers Forum. Some vendors, such as Texas Instruments
(TI), offer extensive USB libraries for their embedded processors.
In 200x, the USB 3.0 Promoter Group was formed to create a
faster USB variant that will be backward compatible with previous
USB standards but deliver 10 times the data of USB 2.0. USB 3.0
uses a new signaling scheme. Backward compatibility is maintained by keeping the USB 2.0 two-wire interface. Although this
faster version is in the early stages of deployment, USB 2.0 will
likely remain the most popular USB variant for several years with
three speed options high-speed (480 Mbps), low-speed (1.vMbps)
and full-speed (12 Mbps).
EMAC
Although an interface conforming to the IEEE 802.3 Ethernet
standard is often incorrectly referred to as an Ethernet media
access controller (EMAC), a complete EMAC subsystem interface
actually consists of three modules all of which may or may not be
integrated on chip0
1. The physical layer interface (PHY )
2. The Ethernet MAC, which implements the EMAC layer of the
protocol
3. A custom interface typically referred to as the MAC control
module
The EMAC module controls the flow of packet data from the
system to the PHY . The MDIO module handles configuration of
the PHY and status monitoring. Both modules access the system
core through the MAC control module, which also optimizes data
flow. In completely integrated solutions such as embedded
processors from TI, the custom interface is considered integral
to the EMAC/MDIO peripheral. A complete EMAC subsystem is
illustrated in Figure 1.
The EMAC control module controls device interrupts and incorporates an 8 kbyte internal random access memory (RAM) to hold
Ar t i c l e
EMAC buffer descriptors. The MDIO module implements the

802.3 serial management interface to interrogate and control up
to 32 Ethernet PHY s connected to the device by using a shared
two-wire bus.
Host software use the MDIO module to configure the auto
negotiation parameters of each PHY attached to the EMAC, retrieve
the negotiation results, and configure required parameters in the
EMAC module for correct operation. The module is designed to
allow almost transparent operation of the MDIO interface, with very
little maintenance from the core processor.
EMAC modules provide an efficient interface between the
processor and the network. EMAC modules usually offer 10Base-T
(10 Mbits/sec) and 100BaseTX (100 Mbits/sec), half-duplex and
full-duplex mode, and hardware flow control and quality-of-service
(Q oS) support. In addition, some processors now support gigabit
EMAC capability supporting data rates of 1000 Mbits/sec.
Since Ethernet is so widely used, embedded processors typically
integrate one or more EMAC interfaces on chip. There is some
variation in the way different vendors implement the complete
EMAC subsystem described above. The quality and extent of
software support and libraries for implementing Ethernet
interfaces is another decision point in choosing an embedded
processor vendor.
At times, applications such as routers or switches will require more
than one EMAC. By using multiple EMACs, these applications are
able to communicate to numerous devices at once creating a
synchronized process of communication.
SATA
The serial ATA (SATA) bus connects host bus adapters to mass
storage devices such as hard disk drives and optical drives. It has
nearly replaced its predecessor, parallel ATA (PATA) which required
40/80 wire parallel cable that could not exceed 18 inches. PATA s
maximum data transfer rate was 133 Mbytes/s while SATA1s serial
data format uses two differential pairs to support interfaces to data
storage devices at line speeds of 1.v Gbits/s (SATA Revision 1), 3.0
Gbits/s (SATA Revision 2) and w.0 Gbits/s (SATA Revision 3). SATA
1 and SATA 2 capability are available today with SATA 3 support
coming in the near future.
Also, SATA controllers require a thinner cable as long as three feet.
A thinner cable offers flexibility permits both easier routing and
better air ventilation inside the mass storage enclosure.
Figure 1 : E MAC subsy stem
The serial link attains its high performance in part by implementing

an advanced system memory structure to accommodate highspeed serial data. The advanced host controller interface (AHCI)
memory structure contains a generic area for control, status and
a command list data table. Each entry in the command list table
contains information for programming a SATA device, as well as
a pointer to a descriptor table for transferring data between system
memory and the device.
Most SATA controllers support hot swapping and the use of a port
multiplier to increase the number of devices that can be attached to
the single HBA port. The SATA standard includes a long list of
features, but few SATA controllers support all of them. Popular
features include0
support for the AHCI controller spec 1.1
integrated SERDES PHY
integrated Rx and Tx data buffers
support for SATA power management features
internal DMA engine per port
hardware-assisted native command queuing (N CQ ) for up to
32 entries
32-bit addressing
support for a port multiplier
activity LED support
mechanical presence switch
Since SATA is able to store data stretching into the terabyte range,
it is highly utilized in applications including netbooks, laptops,
desktops, multimedia devices and portable data terminals. SATA
can be used in industrial applications where sensors or system
monitors may need to store large amounts of data to be analyzed at
a later time.
DDR2wMobile DDR
DDR2 is the successor to the double data rate (DDR) SDRAM
specification and the two standards are not compatible. By transferring data on the rising and falling edges of the bus clock signal
and by operating at a higher bus speed, DDR2 achieves a total of
four data transfers per internal clock cycle.
A simplified DDR2 controller interface includes the following
design blocks0
memory control
read interface
write interface
and an IO block
These blocks and their relationship to the DDR2 memory chip and
core logic are shown in Figure 2.
The memory control block issues accesses from memory to the
application-specific core logic or vice versa. The read physical
block handles external signal timing that captures data during read
cycles; and the write physical block manages the issuance of clock
and data with the appropriate external signal timing.
Ar t i c l e
A byte-wide, bidirectional data strobe (DQ S) is transmitted

externally along with data (DQ ) for capture. DQ S is transmitted
by memory during reads and by the controller during writes.
On-chip delay-lock loops (DLLs) are used to clock out DQ S and
corresponding DQ s. This assures that they can track each other
during changes in voltage and temperature.
DDR2 SRAMs have differential clock inputs to reduce the effects of
duty cycle variations on clock inputs. DDR2 SRAMs also support
data mask signals to mask data bits during write cycles.
Mobile DDR (MDDR) is also called Low Power Double Data Rate
memory (LPDDR) because it operates at 1.8 volts as opposed to
the more traditional 2.v or 3.3 volts and is commonly used in
portable electronics. Mobile DDR memory also supports low-power
states that are not available on traditional DDR2 memory. As with
all DDR memory, the double data rate is achieved by transferring
data on both clock edges of the device.
uPP
With the number of on-chip peripherals limited either by cost or
other constraints, system designers often tend to find novel ways
of moving data on and off chip. One tactic is to tap the resources
of an unused video port, essentially tricking it to send and receive
non-video data at high speeds. One of the downsides of this
approach is that the data has to be formatted into video frames,
which requires some processor MIPS during operation and
valuable programming time during the design cycle.
Other methods present similar difficulties and most of the standard
on-chip data interfaces are serial ports that are not capable of
handling high-speed transfers.
As a result, many system designers see great value in a flexible,
high-speed peripheral primarily for data transfer that does not
conform to a particular interface standard but can be configured
in a number of ways. This is particularly true if the system
processor has to interface with high speed DACs, ADCs, DSPs
and even FPGAs capable of high speed data transfers of the order
of 2v0 MB/s.
The basic architecture of such a peripheral is easy to describe. It
would have multiple channels with separate, parallel data buses
that could be configured to accommodate more than one word
length. It would also have an internal DMA block so that its
operations could proceed without draining the core1s MIPS budget.
Single or double data rates and multiple
data packing formats are also desirable.
The universal parallel port (uPP) is available
on a variety of TI embedded processors
including the Sitara ARMz AM1808 and
AM180w microprocessors (MPUs) and
OMAP-L138 processor, which includes a
TMS320Cwx4x core and an ARMz core.
Figure 2 : Simp l if ied D D R2 c o n tro l l er imp l emen tatio n
2z
Unlike serial peripherals such as SPI and UARTs, uPP offers

designers the advantages of a parallel data bus with a data width
of 8- to 1w-bit per channel.
When running at its maximum clock speed of xv MHz, uPP transfers data much faster than the serial port peripherals. For example,
a single 1w-bit uPP channel operating at xv MHz is as much as 24
times faster than a SPI peripheral operating at v0 MHz. A simplified
block diagram is shown in Figure 3.
Ar t i c l e
PRU
The programmable real-time unit (PRU) is a small, 32-bit
processing engine that provides additional resources for real-time
processing on chip. Used exclusively in TI1s embedded processors
in the AM1x MPUs and OMAP-L138 solutions, PRU offers system
designers an extra measure of flexibility, typically reducing
component costs.
The PRU1s four bus architecture allows instructions to be fetched
and executed concurrently with data transfers. In addition, an input
register is provided in order to allow external status information to
be reflected in the internal processor status register.
An important goal in the PRU1s design was to create as much
flexibility as possible to perform a wide range of functions. The
flexibility of the PRU allows developers to incorporate additional
interfaces into their end product whether it s a touch screen,
integrated displays or storage capabilities to further extend their
capabilities or the capabilities of their own proprietary interfaces.
This goal was in large part accomplished by giving the PRU full
system visibility including all system memory, I/Os and interrupts.
Figure 3: uP P simp l if ied bl o c k diagram
The most important features of the uPP include0

Two independent channels with separate data buses
- Channels can operate in same or opposing directions
simultaneously
I/O speeds up to xv MHz with 8-1w bit data width per channel
Internal DMA leaves CPU EDMA free
Simple protocol with few control pins (configurable02-4 per
channel)
Single and double data rates (use one or both edges of clock
signal)
- Double data rate imposes a maximum clock speed of 3x.v MHz
Multiple data packing formats for z -1v bit data widths
Data interleave mode (single channel only)
Although its access to system resources is comprehensive, the

PRU1s internal resources are relatively modest. It has 4 K bytes of
instruction memory and v12 bytes of data memory. The PRU also
has its own GPIOs with latencies measured in nanoseconds.
The PRU can be programmed with simple assembly code to
implement custom logic. The instruction set is divided into four
major categories0
move data in or out of the processor1s internal registers
perform arithmetic operations
perform logical operations
control program flow
In industrial applications, the PRU is often configured into an IO
block to stand in for IO that is not available in the processor. It
could be used, for example, in a portable data terminal that requires
uPP bears some resemblance to another TI peripheral dedicated to

configurable data handling, the Host Port Interface (HPI). The HPI
is a parallel interface allowing an external host to access memory
inside the processor directly. Unlike HPI, however, uPP does not
grant direct memory access to an external device and it requires
I/O transfers to be queued by device software. Perhaps the biggest
difference is that uPP is considerably faster than HPI and has a
much simpler protocol.
uPP is largely used for applications requiring off chip real-time
processing like FPGAs or DSPs and is highly beneficial to markets
needing data instantly such as the medical field. By utilizing the
uPP, decision making processors are able to draw conclusions with
up to date information.
Figure 4 : U sin g th e P RU to ex ten d th e c ap abil ities o f th e ex istin g dev ic e

p erip h eral s
Ar t i c l e
a combination of UART blocks to connect to a GSM, GPS and Bluetooth, keypad, print, LED bank and RS232 port. However, while the
best choice within the processor family integrates only three
UARTs, the PRU can provide additional UART interfaces to handle
the needs of evolving end-equipments to handle all the type of
functionalities.
Besides being an IO replacement, PRU can be programmed to
execute a variety of control, monitoring or other functions that
are not available on chip. This flexibility is particularly helpful in
applications containing control requirements that do not match
those available on any standard processor configurations.
ARM Subsy stem and Peripheral I ntegration
When evaluating peripheral interfaces in an ARM-based processor,
it is important to understand how the
peripherals and the ARM Subsystem
Master
integrate.
- Bus arbiters for accessing system and peripheral control

registers
- Bus arbiters for accessing external memories
Debug, trace, and emulation modules
- JTAG
- ICECrusher
- Embedded Trace Macrocell (ETM)
System Control Peripherals
- ARM Interrupt Control Module
- PLL (Phased-Lock Loop) and Clock Control Module
- Power Management Module
- System Control Module
Refer to Figure v for a block diagram of a typical ARMz -based ARM
Subsystem.
IF
Arbiter
Arbiter
I-AHB
D-AHB
System
Control
I-TCM
D-TCM
Slave
Arbiter
16K
ROM
16K
RAM1
IF
16K
RAM0
CFG Bus
ARM926EJ-S
DMA Bus
The ARM processor is suitable for

complex, multi-tasking, and generalpurpose control tasks. It has a large
program memory space and it has
good context switching capability. It s
suitable for running Real-Time Operating
Systems (RTOS) and sophisticated
High Level Operating Systems. The ARM
is responsible for system configuration
and control, which includes peripheral
configuration and control, clock control,
memory initialization, interrupt handling,
power management, etc. The ARM
Subsystem includes the ARM processor
and other components necessary for
the ARM processor to act as master of
the overall processor system.
ARM
Interrupt
Controller
(AINTC)
Master IF
PLLC2
PPLC1
Power
Sleep
Controller
(PSC)
Peripherals
A typical ARM Subsystem consists

Figure 5 : ARM Subsy stem bl o c k diagram
of combinations of the following
components0
ARM Core
Conclusion
(for example0ARMz 2wEJ-S or ARM Cortex-A8)
Although standard interfaces play a critical role in designing
- MMU
systems that are interoperable, low-cost and require less time
- Write Buffer
to design, their utility is still limited for a design team that needs to
- Instruction CACHE
differentiate its product. Designers should also look to their
- Data CACHE
chip vendors for a wide variety of standard interfaces in multiple
- Java accelerator
combinations. High quality software libraries that help implement
- N eon single instruction, multiple data (SIMD) Engine
the interfaces efficiently are other differentiating factors for chip
- V ector floating point coprocessor (V FP)
vendors. Offering an additional level of flexibility is also helpful
and can be accomplished by configurable interfaces such as TI1s
ARM Internal Memories
PRU and uPP. With options like these in their tool kit, system
- RAM
designers can be creative while simultaneously keeping component
- ROM (ARM boot loader)
Bus Arbiters
costs low.
- Bus arbiters for accessing internal memories
31
ARM
Ar t i c l e
Reducing H ousehold Energy U se

through ARM Powered Smart Meters
by L oren Y ee, P h y s i c a l I P D i v i s i o n , ARM
mart meters are new, all-digital metering devices that precisely track energy usage and transmits
the data directly to the utility company. Since these new meters help manage usage more efficiently
and reduce costs, governments and utility companies around the world are moving quickly to install
them in households everywhere.
Over time, as these smart meters become part of a larger network that
includes home appliances, wireless communications, and the Internet,
the benefits will be even greater. Utility companies will be able to
maximize their infrastructure with targeted power production, and
consumers will have detailed information that helps them manage
their everyday household use to become more
efficient and contribute to combating the
damaging effects of global warming.
ARM and their partners are developing a
range of low-power, low-cost solutions
for smart meters. These highly
integrated SoCs use the power-efficient
ARM Cortex-M processor family with
optimized physical IP, and are
produced in the industry proven TSMC
0.18- m, ultra low-leakage process.
They can be used in standalone
smart meters or in appliances
that combine power
monitoring with other
tasks. The meter
concept can further
extend to a variety of
applications, including
industrial, consumer and
medical systems.
ARM
Smart Meters
Increased concern over global warming, volatility in oil pricing, and
the recent downturn in the economy have made energy conservation
a pressing issue for everyone. Consumers are finding that simple
changes, like washing clothes in cold water, lowering the thermostat,
or waiting for off-peak hours for better rates, can have an impact.
They1re selecting appliances and electronics that use less power, and
are changing their habits to reduce usage.
Governments are also starting to get involved, using their resources
and legislative powers to encourage homes and businesses to conserve more and reduce their emissions of greenhouse gases. In the
US, for example, the Energy Policy Act of 200v introduced subsidies
for alternative and renewable energy sources, like wind, solar, wave,
and geothermal, and extended daylight savings time by several
weeks. It required utility companies with annual sales of more than
v00 million kWh to consider time-based rates and smart metering
options, and created a demand-response program that rewards
commercial buildings that curtail usage at peak times. It also
introduced tax breaks for people who make energy-saving improvements to their homes.
Another program in the US, called Energy Star, is a joint program of
the US Environmental Protection Agency and the US Department of
Energy, designed to help homes and businesses save money and
protect the environment through energy-efficient products and
practices. In place since 1z z 2, the program is starting to show real
results. According to the program website (energystar.gov), in
200x, through the help of Energy Star product labeling and savings
guidelines, Americans saved m1w billion on their utility bills while
avoiding greenhouse gas emissions equivalent to 2x million cars.
Utility companies, for their part, are looking for better ways to
monitor and manage energy usage for greater efficiency and lower
overall cost. Smart meters, also known as Automatic Meter Readers
or AMRs, are giving utility companies more control over their
networks and making them more responsive to outages. They1re
also making it possible to gather real-time information about energy
usage, so consumers can, ultimately, have access to detailed
information that will help them make better-informed decisions
about energy consumption.
Ar t i c l e
higher levels of mechanical stress, and they can withstand the

reactive and non-linear loads that cause problems in traditional,
electromechanical meters. They also let utility companies manage
their networks better and respond to outages faster.
Repair crews don1t have to patrol entire circuits to locate a problem,
with smart meters they can identify where there1s an outage with
pinpoint accuracy. Utility personnel make fewer house calls, too,
because service can be turned on or off remotely.
When equipped with a microcontroller, a smart meter can be
configured to monitor other factors, such as power strength and
quality. The system can also be programmed to implement timebased metering, with different rates for peak and off-peak usage.
When connected to a network, via wired or wireless connectivity,
smart meters can report measurements directly to the utility
company, so there1s no need for roving personnel to read meters.
That lowers cost and simplifies the preparation of monthly bills.
Readings can also be taken more than once a month, and usage can
be reported with a breakdown, showing peak and off-peak usage,
instead of a simple lump sum.
N etworked meters can also direct usage data, in real-time, to
databases that consumers can access via the Internet. Figure 1,
gives a sample setup to support this kind of reporting. The network,
known as an Advanced Metering Infrastructure or AMI, has a
wireless smart meter sending data to a local wireless transceiver
installed on a power pole. The data makes its way to the utility
company, where it1s stored in a data warehouse and posted on the
Internet. Consumers can access their data online, for a simple,
paperless way to track usage.
Several companies, including Google, are already prototyping
interfaces for online power meters. The prototypes receive data from
smart meters and energy-management devices, and present the data
in an easy-to-read, web-based graph.
In the ideal scenario, the online meters provide detailed information
about consumption. They identify the source of usage, showing
exactly which appliances are using the energy.
The Mov e to Smart Meters

The transition to smart meters has only just begun, but experts
agree that utility companies around the world are set to move
very quickly with new installations. According to Datamonitor,
only wn of households in Europe and N orth America have
smart-metering devices installed today. By 2012, however, they
predict that 8z n of US and 41n of European households will
be equipped with smart meters. In California, the state-wide
utility company PGo E expects to have z .3 million smartmetering devices installed by 2011, with v.1 million for
electricity and 4.2 million for gas. And, on a global level, ARM,
the leader in microprocessor IP, predicts that 130 million units
will be installed annually by 2013.
The new smart meters offer several benefits. They1re more
reliable because electronic meters can be designed to tolerate
Figure 1 : Smart Meter N etw o rk
33
ARM
Ar t i c l e
With labels for specific appliances - clothes dryer, furnace, refrigerator, TV , web server, hot tub, outdoor lights - the readings let
consumers see exactly how much energy they1re using, and why.
networking functions. Manufacturers are looking for high integration,

too, since many of their machines combine several inexpensive
8-bit MCUs.
They can know, at a glance, if it1s the pot boiling on the stove or the
extra load of laundry that1s causing a spike in usage. They can make
the connection between energy consumption and personal habits,
changing how or when they perform routine tasks to conserve more.
A typical washing machine, for example, might use separate MCUs

for motor control, wash cycles, and the user interface. Replacing
these several MCUs with a single 32-bit SoC that performs all the
necessary functions, including the added power monitoring and
connectivity functions, can deliver real savings.
The greatest savings are achieved, of course, when every household

appliance is connected to the network. Figure 2 shows a sample
configuration, with next-generation appliances, equipped with
powermonitoring and connectivity functions, linked to the metering
network.
Taking the next step, appliances can be configured to provide their
own energy-saving recommendations. A washing machine equipped
with smart-metering technology can, for example, be programmed to
recommend different times for
starting a wash, so the consumer
can take advantage of lower rates.
The machine can be set to turn on
automatically at the specified time,
and can report to the user how
much money they1ve saved by
rescheduling the operation.
It can simplify design, increase efficiency, and lower overall cost.

Moving to a single processor architecture also reduces software
overhead, since there1s just one software engine to be used, and
makes it easier to reuse software in future designs.
Industry organizations and governments will also play a role in
development. The goal of worldwide deployment underscores the
need for standards and common industry interfaces. The whole
metering network needs to
work seamlessly, and everything needs to be plug-andplay.
The ARM Solution:

L ow-Cost, L ow-Power
ARM is enabling technologies for smart meters and
smart appliances, and has
The complete AMI infrastructure,
targeted its development
with smart meters, smart applito address both markets.
ances, and smart user interfaces,
By combining three things may not be here today, but it1s
the ARM Cortex CPU
on the horizon. As new meters
architecture, physical IP
become commonplace, and
from ARM and third
consumers start having online
parties, and the TSMC
access to usage data, the
.18uLL Embedded Flash
companies that make the
Figure 2 : H o me N etw o rk C o n f iguratio n
process - ARM has
household appliances, electronengineered cost-effective
ics, and lighting fixtures will be
solutions for standalone meters and appliances that integrate smartmotivated to add functions that supply data to the metering network.
metering functions.
Design Considerations
Figure 3 on the next page shows the SoC solutions for two smart
Since standalone smart meters are needed on a global scale and in
meters, one for use with electricity and one for gas or water. Both
very high volumes, they have to be as cost-effective as possible. The
SoCs use an ARM Cortex-M family processor, the latest ARM
metering SoCs need to be inexpensive to produce - under mv is a
microprocessor architecture. Recognized for its outstanding
reasonable goal - and they also need to be reliable and inexpensive
computational capabilities and exceptional system response, the
to replace.
Cortex-M processor family delivers high performance with low
manufacturing costs and enhanced energy efficiency. A minimal
At present, real-time processing performance is less critical, since
Cortex-M3 processor implementation requires only 40K gates,
data currently only needs to be read several times a day; however
delivers 1.2v DMIPS/ MHz on the Dhrystone 2.1 Benchmark, and
power consumption and connectivity interfaces are vital. Meters that
uses clock gating and integrated sleep modes to reduce power at
aren1t connected to an electrical line need to run for five to ten
no loss of performance.
years without a battery change, and all meters, whether they1re battery operated or not, need to be able to transmit data over a variety
The Cortex-M3 processor also offers a long list of features for
of technologies, from Z igBee and Bluetooth to Wi-Fi, RF, cellular and
system design and software development. To make finalizing
satellite. Small size is important, too, to keep costs low and make it
designs easier, configurable debug can be accessed via a Serial
easier to convert existing metering setups to new formats. Most of
Wire or JTAG interface, and the enhanced system debug has optional
these requirements - low cost, low power, and wide connectivity ETM for real-time instruction trace capabilities. Writing software is
are the same for appliances that incorporate power-monitoring and
ARM
Ar t i c l e
easier, too, with 100n C coding that includes interrupt handlers and
boot code. There1s no assembler code required, and the application
envelope covers everything from low cost microcontrollers to analog
and mixed-signal applications.
The power gates and isolation cells enable a sleep mode. To ensure
fast wake-ups, the libraries are equipped with data-retention
flip-flops and always-on cells. Biasing cells provide connections for
well-back biasing and reduce leakage even further.
The recently introduced ARM Cortex-M0 processor extends the

Cortex processor family with the smallest, lowest-power ARM
processor ever developed. It brings substantial savings in system
cost with exceptionally low-power, gate count, and code footprint,
while remaining compatible with the feature-rich Cortex-M3
processor. It consumes as little as 8v microwatts/MHz in an area
of under 12k gates when using the ARM standard cell library on a
0.18- m, ultra low-leakage process.
Added power savings can come from the low-power memory

instances. The core and periphery use separate V DD/V SS supplies,
and the memories support retention mode. Also, using the PMK
power-gating cells makes external power gating possible.
For smart meters that require less processing capability and simpler
microcontroller functions, the Cortex-M0 processor saves cost and
reduces power. The Cortex-M0 processor is also a good choice for
smart appliances, since it offers a cost-effective way for manufacturers to increase integration while expanding functionality.
Combining a Cortex-M processor with ARM1s physical IP serves
to reduce the die area and lower the silicon cost. The highly dense
architecture of the ARM memory compilers, processor-optimized
1024x32 and v12x32 single-port register file instances, and the
Ultra High Density Standard Cell Library also contribute to create
the smallest footprint possible. Industry-leading core density results
in smaller memories, while fewer pinouts and reduced power
consumption make it possible to house the SoCs in less-expensive
packages.
The ARM Free Library Program gives designers another way to
reduce costs. It provides design teams with a wide selection of
0.18- m products, all downloadable, free of charge, from the ARM
website. Every product in the Free Library is high-quality IP, designed
using the ARM
Process-Perfect Design
Methodology, and
licensed for use by the
specified ARM foundry.
Using ARM physical IP
for smart-meter SoCs
saves cost, and power.
The ARM Power
Management K it
(PMK ) libraries,
available for the
TSMC 0.18- m uLL
Embedded Flash
processes, minimize
power consumption in
several ways. They support dynamic operation
of functional blocks at
multiple voltages, to
achieve optimal power
tradeoffs.
Process technology, when combined with processor architecture and

physical IP, plays an essential part in reducing power consumption.
By using the TSMC 0.18- m uLL Embedded Flash process, the SoCs
reduce typical leakage in the order of 8x compared to ones produced
in a generic 0.18- m process. ARM low-power memory instances,
tuned for Cortex-M family processors, deliver up to 18x lower leakage than their generic 0.18- m counterparts. Using the ARM Ultra
High Density Standard Cell Library cuts leakage by up to 10x. During
standby operations, core leakage can be lowered even further by
using the Cortex wake-up interrupt controller and the PMK library.
Other Metering Applications

The basic idea behind the ARM SoCs - having a low-cost, low-power
way to monitor and transmit usage data - has potential in other
metering applications, beyond energy usage. Water utilities can use
smart meters to regulate consumption in areas where water is a
scarce resource, and large buildings can use smart meters in their
heating, ventilation, and air conditioning (HV AC) systems to make
them run more efficiently.
Smart meters can also be used in standalone systems, such as
motor controllers, blood-pressure monitors, blood glucose meters,
thermostats, and solar units, to improve accuracy and increase
efficiency on a smaller scale.
Figure 3: ARM-based Smart Meters
3v
ARM
Ar t i c l e
A is for Android and Acceleration9

by Jan H owells, ARM
Europe is getting a piece of the Android action with Motorola s

Milestone running Android 2u0u The Milestone boasts sharp,
super-slim features for users who want the ultimate
smartphone ex perience and lightening fast connection
speed v ia ARM s Cortex -A8 processoru The
Milestone has been designed to deliv er
high-speed W eb, v oice-activ ated
search and comes with access to
thousands of customiz able
applications and widgets from
Android Mark etu
otorola has pinned its colors to the Android mast in

Europe with the ARM powered Milestone, developed in
partnership with Google, dubbing it the smartphone without
compromise .
The Milestone, which is badged the Droid in the US as part of
Motorola s partnership with V erizon, Wireless, comes with some
neat features, but central are internet access and GPS. Thanks to the
ARM Cortex-A8 processor, clocked at vv0 Mhz, these are incredibly
fast. The full html browser can swiftly handle content heavy Web
pages. Users can run several applications at once and there is no
drop off in speed or delay when the browser is launched, for
example. In another dimension, slot the Milestone into its auto
mount and it turns into a full-blown GPS navigation system.
Milestone is powered by a Cortex-A8 processor with dedicated
hardware acceleration for a quick and fluid graphics experience.
This is part of a new processor family that can actually deliver up
to three times the performance of a typical ARM11-based processor,
explained a spokesperson for Motorola.
Motorola opted for the ARM Cortex-A8 to enable the user to
experience a faster, richer, more responsive mobile device, added
the spokesperson for Motorola.
ARM
The Milestone, built with the multitasking user top of the agenda,
maintains it has the thinnest Q WERTY slider keyboard on the market
at 13.x mm, for messaging and push email that syncs with both
Microsoft Exange and personal accounts through GoogleMail. All
emails are channelled into one box with emails pushed directly to
the user.
The GPS receiver comes with Google Maps and also Motorola s own
MOTON AV software, a fully featured package that includes both auto
and on-foot directions which comes with free European maps and a
trial period for a Premium mapping service.
Milestone incorporates a 3.x high-resolution display, with 8v4
pixels width and 400,000 pixels total, which covers most of the
smartphone s real estate providing a very clear widescreen
experience. Users can run multiple applications at the same time and
benefit from multi-touch pinch and zoom browsing. The touch screen
also means users can hit hyperlinks accurately.
Multi-touch input is the primary method of navigation around the

handset s functionality. In addition to the Q WERTY keyboard and five
way navigation key, the Milestone also includes an accelerometer and
proximity sensors.
Motorola refers to the Milestone s cutting edge image features as the
pocket paparazzi . Users keen on taking snaps on the move to send
to colleagues or upload to blogs will be interested in the Milestone s
v megapixel camera with a dual-LED flash, autofocus, geo-tagging
and image stabilization as standard. For users who prefer video
Ar t i c l e
footage or capture, the camera includes the ability to record DV D

quality video at 24 frames per second.
Users can drag, drop and sync content, then post, share or playback
with the optional Motorola Multimedia Station, which doubles as a
charger. Using the Station users can display photos and movies or
play music. It syncs media to a PC using a USB cable. In addition,
it shows the weather, time and works as an alarm clock.
The Milestone comes with a bumper 8 GB of storage, which supports
up to 32 GB micro SD expandable. It also includes stereo Bluetooth,
CrystalTalk for enhanced talk quality, IM support for Google Talk,
email support via IMAP and Pop together with GoogleMail together
with Motorola Media Link and Motorola Phone Portal to manage and
share media content across desktop, phone and the Web.
Application hungry users have access to thousands of applications
and widgets from Android Market. A suite of Google applications,
including Google Maps with Latitude, Google Mail and Y ouTube, are
also integrated into the Milestone.
Milestone may not be the prettiest model on the block, but it does
what it says on the tin. It is an impressively powerful multi-tasking
device and users will undoubtedly be impressed my its internet and
GPS functionality. In addition, it touts all the main open source
advantages that are going to see Android handsets hold their own
on the shelves this year.
3x
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N X P Semiconductors
L PC1100 Microcontroller F amily

With over 4v DMIPS of performance compared to the sub-DMIP
performance typical of 8-bit MCUs and 3 to v DMIPS for 1w-bit
MCUs, the LPC1100 not only execute basic control tasks but
sophisticated algorithms as well, making even the most complex
tasks within reach. Using less time to do more tasks translates
directly into lower energy consumption.
This level of performance is delivered at v0 MHz, with extensive
power optimization, at less than 10 mA.
The L PC1100 and Code Density :
Challenging the belief that 8/1w-bit microcontrollers use less
code, industry-standard Coremark benchmarks show that the
LPC1100 requires 40-v0n less code for the most common
microcontroller tasks.
N X P5 0 - M H z , 3 2 - b it C o r t e x - M 0 m ic r o c o n t r o lle r s
Built around the new Cortex-M0 architecture, the smallest, lowest power, and most energy-efficient ARM core ever developed,
these MCUs are ideally equipped for use in many traditional
8/1w-bit applications.The LPC1100 is the lowest-priced 32-bit
MCU solution in the market.It offers greater value than existing
8/1w-bit microcontroller by delivering unprecedented performance, simplicity, low-power, and dramatic reductions in code
size for every application.
Code density for the LPC1100 is not 4 times as big as an 8-bit

processor. It may seem counter intuitive, but in most cases the
code will be smaller. There are cases where applications are
doing mostly port manipulations that could lead to slightly
larger but with some understanding of the architecture and the
complier there will not be any significant differences. There are
even advantages over 8-bit processors in this case as well, since
in one single write up to 32 bits can be changed at the same
time. The Cortex-M0 not only offers significant savings in code
size compared to 8- and 1w-bit architectures, it offers a dramatic
performance advantage.
For Development Boards, See Page z 0
SI L I C ON
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K e y F e a tu re s :
ARM Cortex-M0 processor
- v0 MHz operation
- N ested V ectored Interrupt Controller for fast deterministic
interrupts
- Wakeup Interrupt Controller allows automatic wake from a
priority interrupt
- Three reduced-power modes0Sleep, Deep-sleep, and Deep
power-down
Memories
- Up to 32 K B Flash memory
- Up to 1w K B SRAM
Serial peripherals
- UART with fractional baud rate generation, internal FIFO,
and RS-48v support
- Up to 2 SPI controllers with FIFO and multi-protocol
capabilities
- I2C-bus interface supporting full I2C-bus specification and
Fast mode plus with a data rate of 1 Mbit/s with multiple
address recognition and monitor mode
Analog peripheral
- 10-bit Analog-to-Digital Converter with eight channels and
conversion rates up to 400 K samples per second
Other
- Up to 42 general-purpose I/O (GPIO) pins with configurable
pullup/ down resistors and a new, configurable open-drain
operating mode
- Four general-purpose counter/timers, with a total of four
capture inputs and 13 match outputs
- Programmable Watchdog Timer (WDT) with lock-out feature
- System tick timer
- Each peripheral has its own clock divider for power savings
41
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L PC1102 Microcontroller
K ey product features include a v-channel 10-bit ADC, one
UART, one SPI, two 32-bit and two 1w-bit timers, and one 24-bit
system timer. SWD debugging and programming with four
breakpoints and two watchpoints are also included. A total of
eleven I/O functions also double as general purpose input and
output GPIO for maximum flexibility.
Offering very low-power consumption with active mode current
as low as 130 A/MHz, the LPC1102 features an internal IRC
oscillator, accurate to 1 percent over the industrial temperature
and voltage range. It can also be clocked with an external
source.
N X P1s LPC11xx series is the lowest-priced 32-bit MCU
solution in the market, bringing higher value and ease of use
than existing 8-/1w-bit microcontrollers through unprecedented
performance, simplicity, low-power, and more importantly,
dramatic reductions in code size for all 8-/1w-bit applications.
W o r l d ' s Sm a l l e s t 3 2 - Bi t ARM M i c r o c o n t r o l l e r
Unleashing unprecedented computing power in vmm2 of PCB
area, the LPC1102 is targeted at applications requiring an
ultraminiature board footprint.
As the newest member of the highly successful LPC11xx
microcontroller series, the addition of the LPC1102 delivers the
same key features of low-power, high performance, and high
value, while adding the dimension of miniaturization.
The LPC1102, with 32 K B of flash and 8 K B of RAM on-chip, is
available in Wafer Level Chip Scale Packaging (WL-CSP) with
dimensions of 2.1xmm x 2.32mm, a thickness of 0.wvmm, and
a pitch of 0.vmm.
SI L I C ON
C ORTEX - M 0
Based on ARM Cortex -M0 processor cores
Speeds up to 100MHz from flash or RAM
Low power consumption
N ew Wake-up Interrupt Controller (WIC)
Memory Protection Unit
Av ailable with:
Ethernet, USB Host/OTG/Device, CAN , I2S
Fast-mode Plus (Fm. ) I2C, SPI/SSP, UARTs
12-bit ADC @
1MHz conversion rates
Low-power Real-Time Clock

Motor Control PWM o Q uadrature Encoder Interface
Multiple package options available
Enabling H igher Code Density
The LPC1102 enables 40-to-v0 percent smaller code
sizes compared to traditional 8-/1w-bit microcontrollers for most
common microcontroller tasks. This is achieved through the
powerful Cortex-M0 vw-M instruction set, which is built on a
fundamental base of 1w-bit Thumb instructions and unique to
32-bit microcontrollers today.
Superior Performance
With over 4v DMIPS of performance, the LPC1102 provides
unprecedented processing power in a vmm2 footprint, and this
is while offering power optimization unavailable in today1s
8-/1w-bit microcontrollers.
43
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L PC11C00 Microcontroller F amily

Total CAN Solution
CAN has long been considered one of the best choices for
robust real-time communications, but it has been priceprohibitive for low-cost embedded applications. With the
introduction of the LPC11Cxx series, N X P now provides a new,
low-cost entry point for a total CAN solution. The PC11Cxx
series reduces product development risk, lowers total system
cost, and speeds time-to-market for high-performance
embedded designs.
C o r t e x - M 0 M C U s f o r a t o t a l C AN s o l u t i o n w i t h o n - c h i p
C AN o p e n d r i v e r s
Offering a low-cost entry point for CAN -based applications, the
LPC11C00 series reduce product development risk, lower total
system cost, and speed time-to-market for high-performance
embedded designs.
Th e L PC 1 1 C 0 0 h a s t h e Sa m e Ar c h i t e c t u r e a n d Pe r i p h e r a l s a s
o u r L PC 1 1 x x Se r i e s Pl u s :
On-Chip CAN 2.0 B C_ CAN Controller and CAN open Drivers
Higher Code Density than Traditional 8-/1w-Bit MCUs
High-Performance v0-MHz ARM Cortex-M0 Operation
Delivers > 4v DMIPs
10-bit, 8-Channel ADC with up to 400K Samples per Second
at 1LSB DN L
Up to 32 K B Flash Memory with 8 K B SRAM
Three Reduced Power Modes0Sleep, Deep-Sleep, and Deep
Power-Down
On-Chip CAN and CANopen Driv ers

On-chip CAN and CAN open drivers provide design engineers
with easy-to-use API commands to the CAN open protocol.
This enables rapid integration of the LPC11Cxx series into CAN based networks which greatly simplifies the plug-and-play
integration process. Furthermore, these drivers are incorporated
in low-power ROM, freeing up to 8 K B of user code space. This
offers the dual advantage of reduced operating power and
secure and safe boot loading via CAN or other on-chip serial
channels. With the security and peace of mind of ROM-based
drivers, flash updating can be done via In-System Programming
(ISP) over the CAN -bus. This gives you the entire range of
functionality, from programming blank parts in production
through to changing system parameters to full in-field re-programmability.
Enabling H igher Code Density
The LPC11Cxx enables 40 to v0 percent smaller code sizes
compared to traditional 8-/1w-bit microcontrollers for most
common microcontroller tasks. This is achieved through the
powerful Cortex-M0 vw-Minstruction set, which is built on a
fundamental base of 1w-bit Thumb instructions and unique to
32-bit microcontrollers today.
Superior Performance
With over 4v DMIPS of performance, the LPC11Cxx series
provides powerful message and data handing for CAN device
nodes. This is while offering power optimization unavailable in
today s 8-/1w-bit microcontrollers.
SI L I C ON
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ARM Cortex -M0 processor
- v0 MHz operation
- N ested V ectored Interrupt Controller
- Three reduced-power modes0Sleep, Deep-sleep, and Deep
power-down
- Serial Wire Debug (4 breakpoints)
Memories
- 1w/32 K B Flash memory
- 8 K B SRAM
Serial peripherals
- CAN 2.0 B C_ CAN controller with on-chip CAN open drivers
- UART with fractional baud rate generation
- 2 SPI controllers with FIFO and multi-protocol capabilities
- I2C-bus interface supporting Fast mode plus
Analog peripheral
- 10-bit analog-to-digital converter with 8 channels and
conversion rates up to 400 K samples per second with
1LSB DN L
Timers
- Four general-purpose counter/timers - two 32-bit counter/
timers o two 1w-bit counter/timers - with a total of four
- Programmable Watchdog Timer (WDT) with lock-out feature
- 24-bit System timer
I wO
- 42 general-purpose I/O (GPIO) pins
Clock generation unit
- 12 MHz Internal RC Oscillator trimmed to 1n accuracy
- Crystal oscillator with an operating range of 1 to 2v MHz
- Programmable watchdog oscillator
- Clock output function
Other
- Unique device serial number for identification
- PMU (Power Management Unit) to minimize
- Brownout detect
- Power-On Reset (POR)
- Single 3.3 V power supply (1.8 to 3.w V )
4v
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Atmel
AT91SAM3U w3S Microcontroller F amily

SAM 3 U Se r i e s : 9 6 M H z C o r t e x - M 3 F l a s h M C U w i t h
H i g h - Sp e e d U SB
Atmels SAM3U series is the worlds first 32-bit ARM
Cortex-M3 Flash microcontroller with high-speed 480 Mbps
USB . Phy.
H igh-Speed U SB
The SAM3U is the first Cortex-M3 microcontroller with
high-speed USB and an integrated transceiver for fast up/downloading of data, robust EMI tolerance, and plug-and-play
high-speed serial interconnectivity.
H igh Performance
Features a z w MHz maximum operating frequency and a high
data-bandwidth architecture based on a v-layer bus matrix with
22 DMA channels and distributed memory.
Dual-Bank F lash
Provides safe in-application programming (IAP) including the
boot program.
1u62 to 3u6V Operation
True 1.8V 10n operation extends device operation when
running from two AA alkaline batteries.
Memory Protection U nit
Improves code protection and secures multi-application/task
execution.
H igh-End Analog
Features a differential input and programmable gain amplifier
(PGA) on a 12-bit 1 Msps ADC.
SAM3U -EK ) Support Ecosy stem
For rapid evaluation and code development. Industry-leading
third parties provide a full range of development tools, RTOS,
middleware and support services to reduce time-to-market to
a minimum.
SI L I C ON
Atmel
C ORTEX - M 3
K e y SAM 3 S Se r i e s : H i g h l y - i n t e g r a t e d C o r t e x - M 3 F l a s h
M C U s Si m p l i f y PC B D e s i g n a n d Re d u c e Po w e r
C o n s u m p tio n
Atmel extends its One-stop Shop for ARM-based micros with
the SAM3S, a Cortex-M3 Flash MCU series that integrates
features to simplify PCB design and reduce power consumption
down to 2.3 mW at 1 MHz operation. Inspired by the best-selling
SAMxS series, the SAM3S provides the ideal migration path to a
more powerful and feature-rich MCU, while preserving hardware
and software investments.
Simplified PCB Design and L ow Sy stem Cost
Integrated serial resistors eliminate the need for external
resistors to preserve signal integrity, resulting in reduced BOM
cost, real estate savings and simplified PCB design.
1u62 to 3u6V Operation and L ow-Power
True 1.8V 10n operation extends device operation when
running from two AA alkaline batteries. The SAM3S only
consumes 1.4vmW/MHz at w4 MHz operation and 1.w A in
backup mode with the RTC running.
Parallel Capture Mode
The SAM3S is the first ARM MCU with parallel data capture
mode on PIOs and DMA support. The parallel data capture
mode on the PIOs complements the external bus interface for
data collection from external devices that are not compliant with
standard memory read protocols, such as low-cost image
sensors.
Safety and Security
Memory protection unit improves code protection and secures
multi-application/task execution. Unique 128-bit ID and
scrambled external bus interface ensure software confidentiality
while the hardware CRC checks memory integrity.
Pi n - t o - p i n C o m p a t i b i l i t y b e t w e e n SAM 3 S a n d SAM 7 S M C U s
In its w4-pin version, the SAM3S is pin-to-pin compatible with
the SAMxS, enabling customers to upgrade performance while
maintaining hardware, preserving previous investments.
Data Speedway
N ative 4-layer bus AHB matrix support with 21 peripheral DMA
channels and distributed memory for high-speed uninterrupted
data flows with minimum processor overhead.
Application Areas
Consumer, industrial control, metering, toys, medical, test and
measurement, 802.1v.4 wireless networking, and PC, cell
phone and gaming peripherals.
4z
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Cypress Semiconductor
PSoC 5
PSoC is a true programmable embedded system-on-chip
integrating configurable analog and digital peripheral functions,
memory and a microcontroller on a single chip. With an
extremely flexible visual embedded design methodology that
includes preconfigured, user-defined peripherals and
hierarchical schematic entry, you can change your mind as often
as you want and stay on schedule. N o more restarting projects
from scratch. N o more catalogs. N o more limitations.
And now our breakthrough new PSoC v family extends the
world1s only programmable embedded system design platform,
shattering your design limitations. Take advantage of highprecision programmable analog including 12- to 20-bit
delta-sigma ADCs, a digital logic library with dozens of drop-in
peripherals, best-in-class power management and rich
connectivity resources. Implement your 8-, 1w-, or 32-bit
designs with the advanced ARM Cortex -M3 processors.
PSoC is a true programmable embedded SoC integrating
configurable analog and digital peripheral functions, memory
and a microcontroller on a single chip. With an extremely
flexible visual embedded design methodology that includes
preconfigured, user-defined peripherals and hierarchical
schematic entry, you can change your mind as often as you
want and stay on schedule. N o more restarting projects from
scratch. N o more catalogs. N o more limitations.
v0 Cortex Resource Guide
SI L I C ON
Energy Micro
C ORTEX - M 3
EF M32 Tiny Geck o

ATEF M 3 2 Ti n y Ge c k o m i c r o c o n t r o l l e r s
The new EFM32 Tiny Gecko devices are ideal for low-power,
space and cost sensitive applications. Offering the same
ultra low-power microcontroller characteristics as its bigger
brother, Tiny Gecko includes most of the existing, energy
friendly peripherals. The largest devices embed a 4x24 segment
LCD controller, while all TG parts offer an AES encryption/
decryption engine as standard, a pre-requisite for many wireless
applications. Other peripherals provided by the EFM32TG
include low energy UART and I2C serial interfaces, A/D and D/A
converters and a host of counters and timers. Unique to the
Gecko microcontroller, its 1peripheral reflex system1running in
parallel with the standard 32-bit ARM bus allows peripherals to
run and communicate autonomously while the CPU is turned
off, resulting in longer sleep periods and large savings in energy
consumption.
EFM32 Tiny Gecko MCUs provide up to 32 K B Flash and
4 K B RAM memory.
F e a tu re s :
32-bit ARM Cortex-M3 running up to 32 MHz and 1.2v
DMIPS/MHz
V ery low active power consumption
Reduced processing time
V ery fast wake-up time
Ultra-low standby current
Autonomous peripheral operation
PRS - Peripheral Reflex System
v Efficient energy modes
USB 2.0 compliant interface
AEM - Advanced Energy Monitoring enabled tools
energyAware Software
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Energy Micro
EF M32 Geck o and Giant Geck o
EF M 3 2 Ge c k o M i c r o c o n t r o l l e r s
The energy friendly EFM32 Gecko microcontrollers have beaten
existing 8-, 1w- and 32-bit low-power devices since their
introduction in 200z , and they are increasingly popular for
customers concerned with their battery driven applications.
Proven to consume less than 180 A per MHz while executing
real life code from Flash the EFM32G MCUs are based on the
ultra-efficient ARM Cortex-M3 microcontroller architecture.
The Gecko devices sport a feature set developed by Energy
Micro which contribute to its ultra low energy consumption0
a 4x40 segment LCD controller running at less than vv0nA;
an 8-channel 12-bit 1M samples/sec ADC running at less than
200A; a brown-out detector running at less than 100nA; a
32kHz real-time counter running at v0nA; and a UART capable
of z w00bps at 100nA.
EFM32 Gecko MCUs provide up to 128 K B Flash and 1w K B RAM
memory.
EF M32 Giant Geck o Microcontrollers

At the opposite end of the memory scale we find the EFM32
Giant Gecko microcontrollers for energy sensitive applications
with high memory requirements and the added option of
embedded USB connectivity. The 48 devices will provide Flash
memory configurations up to 1024 K B with the added option of
embedded USB connectivity. Package options include Q FN w4,
Q FP100 and BGA112. The USB connectivity option will be USB
2.0 compliant at full speed (12Mbit/s), integrating 2 K B
endpoint buffers and handling up to 10 endpoints. It will provide
support for USB host and on-the-go configurations as well as
bootloader over USB. EFM32 Giant Gecko MCUs provide up to
1024 K B Flash and a USB interface.
EF M32 energy Aware Software
Called the energyAware Profiler, the software reads the EFM32
development kit s Advanced Energy Monitoring (AEM) system
data and enables simple graphical visualization and optimization
of application energy consumption and code. Supporting the
energy friendly EFM32 microcontrollers are the energyAware
software suite. Interfacing via USB with both the EFM 32
Gecko development kit and low-cost starter kit, the patent
pending energyAware Profiler complements the kit s on-board
AEM LCD display and provides three simultaneous views; a
graph of real-time application current consumption, an object
code listing and an energy profile of individual application
functions.
SI L I C ON
Fujitsu
C ORTEX - M 3
F ujitsu F M3 F amily
The Fujitsu FM3 product family incorporates a new-generation

ARM Cortex-M3 CPU core specialized for the embedded
microcontroller market, and covers the performance range of
conventional 1w- and 32-bit microcontrollers for highperformance, low-cost applications. The Cortex-M3 CPU core
is enhanced for memory-saving and power-saving capabilities.
K ey F eatures
Operating speed up to 144 MHz
The Fujitsu FM3 product family includes both a HighPerformance and a Low-Power series. The High-Performance
kMBz BFxxxk series is positioned as an extension of Fujitsu1s
existing proprietary 32-bit RISC microcontrollers and the
Low-Power MBz AFxxx series corresponds to existing 1w-bit
CISC microcontrollers.
Highly reliable, high-speed and secure embedded Flash

memory technology
Support for a wide range of operating voltages

(from 1.8V to v.vV )
Wide range of package options ranging from 32-pin to
1xw-pin
Low-power, low-leak products for handheld, battery powered

applications
Built-in high-performance analog macros
CAN and full speed USB 2.0 (host and slave)
The High-Performance series offers significant advancements

over 32-bit microcontrollers, including more processing ability
than ever before, an enhanced IP macro and faster operating
frequencies. In the Low-Power series, the IP macro, operating
frequency, and operating modes have been optimized to enable
the 32-bit microcontrollers to offer power consumption in line
with 1w-bit microcontrollers.
Plans for on-chip Ethernet with PHY

Multifunction serial interfaces LIN /SPI, I2C and UART
Multifunction timer for inverter motor control
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The peripheral complement of the LPC1311/13/42/43 includes
up to 32 K B of flash memory, up to 8 K B of data memory, USB
Device (LPC1342/43 only), one Fast mode plus I2C interface,
one UART, four general purpose timers, and up to 42 general
purpose I/O pins.
Built around a Cortex-M3 Rev2 processor core, the LPC1300 is
equipped with up to 32 K B of Flash and up to 8 K B of SRAM,
uses a single 3.3 V power supply (for operation between 2.0 and
3.w V ), and is available in LQ FP48 or HV Q FN 33 packages.
The LPC1300 series is pin-to-pin compatible with the LPC1100
series, N X P s new family of Cortex-M0 MCUs, so it gives
designers a straightforward migration path to the even lower
power features of the Cortex-M0 architecture.
The LPC1311/13/42/43 are ARM Cortex-M3 based

microcontrollers for embedded applications featuring a high
level of integration and low-power consumption.
The ARM Cortex-M3 is a next generation core that offers system
enhancements such as enhanced debug features and a higher
level of support block integration.
Also, in keeping with N X P s existing line of more than v0 USB

equipped ARM MCUs, the LPC1340 offers support for USB
full-speed operation. HID and mass storage USB driver software
is included in a dedicated on-chip ROM, maximizing the amount
of Flash memory available for user code.
The LPC1300 family is supported by LPCX presso, an
easy-to-use, comprehensive development tool platform. It s
also supported by development tools from IAR, K eil, Hitex,
Code Red, and many others.
The LPC1311/13/42/43 operate at CPU frequencies of up to

x0 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage
pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals.
The ARM Cortex-M3 CPU also includes an internal prefetch unit
that supports speculative branching.
For Development Boards, See Page z v
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ARM C o r t e x - M 3 p r o c e s s o r , r u n n i n g a t f r e q u e n c i e s o f u p t o
7 0 M H z
ARM C o r t e x - M 3 b u i l t - i n N e s t e d V e c t o r e d I n t e r r u p t
C o n tro lle r (N V IC )
3 2 K B ( L PC 1 3 4 3 / 1 3 ) / 1 6 K B ( L PC 1 3 4 2 ) / 8 K B ( L PC 1 3 1 1 )
o n -c h ip fla s h p ro g ra m m in g m e m o ry
Enhanced flash memory accelerator enables high-speed
x0MHz operation with zero wait states.
I n - Sy s t e m Pr o g r a m m i n g ( I SP) a n d I n - Ap p l i c a t i o n
Pr o g r a m m i n g ( I AP) v i a o n - c h i p b o o t l o a d e r s o f t w a r e
Se r i a l i n t e r f a c e s :
USB 2.0 full-speed device controller with on-chip PHY for
device (LPC1342/43 only)
UART with fractional baud rate generation, modem, internal
FIFO and RS-48v/EIA-48v support
SSP controller with FIFO and multi-protocol capabilities
I2C-bus interface supporting full I2C-bus specification and
Fast mode plus with a data rate of 1 Mbit/s with multiple
address recognition and monitor mode
Ot h e r p e r i p h e r a l s :
Up to 42 General Purpose I/O (GPIO) pins with configurable
pull-up/down resistors and a new, configurable open-drain
operating mode
Four general purpose timers/counters, with a total of four
Programmable WatchDog Timer (WDT)
System tick timer
Each peripheral has its own clock divider for power savings
Av a i l a b l e a s 4 8 - p i n L Q F P p a c k a g e a n d 3 3 - p i n H V Q F N
p a c k a g e
vv
C ORTEX - M 3
SI L I C ON
L PC17 00 Microcontroller F amily

The LPC1xxx devices are ARM Cortex-M3 based
microcontrollers for embedded applications featuring a high
level of integration and low-power consumption. The ARM
Cortex-M3 is a next generation core that offers system
enhancements such as enhanced debug features and a higher
level of support block integration.
The LPC1xxx devices operate at CPU frequencies of up to 100
MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline
and uses a Harvard architecture with separate local instruction
and data buses as well as a third bus for peripherals. The ARM
Cortex-M3 CPU also includes an internal prefetch unit that
supports speculative branching.
The LPC1x00 series is the industry s highest performance

Cortex-M3 microcontroller, based on results from the Embedded
Microprocessor Benchmark Consortium (EEMBC). The EEMBC
results show that the LPC1x00 executes application code on
average 3vn faster than the leading Cortex-M3 competitors
when running at the same clock speeds.
N X P s performance advantage is even greater when the
LPC1x00 runs at higher clock speeds. The LPC1x00 has been
certified by EEMBC at x2,100, and 120 MHz. This increased
speed and efficiency is due to the intelligent architecture of the
microcontroller, its use of flexible direct memory access (DMA)
and best-in-market Flash.
The peripheral complement of the LPC1xxx devices includes

up to v12 K B of flash memory, up to w4 K B of data memory,
Ethernet MAC, USB Device/Host/OTG interface, 8-channel
general purpose DMA controller, four UARTs, two CAN channels,
two SSP controllers, SPI interface, three I2C-bus interfaces,
2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC,
10-bit DAC, motor control PWM, Q uadrature Encoder interface,
4 general purpose timers, w-output general purpose PWM,
ultra low-power Real-Time Clock (RTC) with separate battery
supply, and up to x0 general purpose I/O pins.
The LPC1xwx devices are pin-compatible to the 100-pin
LPC23wx ARMx-based microcontroller series.
The LPC1x00 series is targeted to operate high-bandwidth

communications peripherals such as Ethernet, USB
On-The-Go/Host/Device and CAN simultaneously with no
bottlenecks. It is designed for use in a wide variety of
applications, including eMetering, lighting, industrial
networking, alarm systems, white goods and motor control.
For Development Boards, See Page z w
vw Cortex Resource Guide
SI L I C ON
C ORTEX - M 3
ARM C o r t e x - M 3 C o r e
100 MHz operation
N ested V ectored Interrupt Controller for fast deterministic
interrupts
Wakeup Interrupt Controller allows automatic wake from
any priority interrupt
Memory Protection Unit
Four reduced power modes0Sleep, Deep-sleep, Powerdown and Deep power-down
M e m o rie s
Up to v12 K B Flash memory
Up to w4 K B SRAM
Serial Peripherals
10/100 Ethernet MAC
USB 2.0 full-speed device/Host/ OTG controller with
on-chip PHY
Four UARTs with fractional baud rate generation, RS-48v,
modem control I/O, and IrDA
Two CAN 2.0B controllers
Three SSP/SPI controllers
Three I2C-bus interfaces with one supporting fast mode
plus (1 Mbit/s data rates)
I2S interface for digital audio
Analog Peripherals
12-bit Analog-to-Digital Converter with eight channels and
conversion rates up to 1 MHz
10-bit Digital-to-Analog Converter
Other Peripherals
Real-time Clock operating at < 1 A
Eight channel General Purpose DMA controller
Up to x0 General Purpose I/O
Motor control PWM and Q uadrature Encoder Interface to
support
Three-phase Motors
Four 32-bit general purpose timers/counters
4 MHz internal RC oscillator trimmed to 1n accuracy
vx
C ORTEX - M 3
SI L I C ON

Ex tensiv e peripheral set
The LPC1800 also features two new innovative peripherals0
a flexible quad-SPI interface and a State Configurable Timer
subsystem. The LPC1800 is the first microcontroller to provide
a seamless high-speed interface that will connect with virtually
all SPI and quad-SPI manufacturers.
The LPC1800 s State Configurable Timer Subsystem comprises
of a timer array with a state machine enabling complex
functionality including event controlled PWM waveform
generation, ADC synchronization and dead time control. This
timer subsystem gives embedded designers increased flexibility
to create user-defined wave-forms and control signals.
The NXP L PC1800 15 0 MH z , 32-bit microcontrollers

The LPC1800 series of low-power, high-performance Cortex-M3
microcontrollers features frequencies up to 1v0 MHz and
flexible Dual-Bank Flash for the highest reliability in-application
re-programming.
Additional peripherals available on the LPC1800 include two

HS USB controllers, an on-chip HS PHY , a 10/100T Ethernet
controller with hardware enabled TCP/IP checksum calculation,
a high-resolution color LCD controller, and AES decryption
including two 128-bit secure OTP memories for key storage.
V ersions with AES encryption are available on request.
L ower power and high-performance

The LPC1800 designed using N X P s ultra low-leakage z 0 nm
process technology is optimized for low-power operation at
very low frequencies all the way through to 1v0 MHz maximum
performance from either Flash or RAM. This performance
provides maximum connectivity and bandwidth options for
a wide range of demanding applications including power
conversion, lighting, motor control and audio applications.
L arge internal memory
The LPC1800 offers the industry s largest on-chip SRAM for
a Cortex-M3 with up to 200 K B provided in multiple banks. A
flexible dual-bank Flash architecture offers the highest reliability
in-application re-programming, and allows for non-stop Flash
operation.
SI L I C ON
C ORTEX - M 3
1v0 MHz, 32-bit ARM Cortex-M3
Up to 1 MB Flash
Up to 200 K B SRAM
Memory Protection Unit (MPU)
Two High-speed USB 2.0 interfaces
On-chip High-speed PHY
Ethernet MAC
LCD Interface
Q uad-SPI Flash Interface
State Configurable Timer Subsystem
Up to 80 GPIO
Additional features:
8-channel GPDMA controller
Two 8-channel 10-bit ADCs and 10-bit DAC
(400 K samples per second)
Motor Control PWM and Q uadrature Encoder Interface
Four UARTs
Smart card interface
Two Fast-mode I2C
I2S interface
Two SSP/SPI
Temperature range0 40 C to . 8v C
vz
C ORTEX - M 3
SI L I C ON
STMicroelectronics
STM32F Microcontroller F amily
The STM32 family of 32-bit Flash microcontrollers, based on

the ARM Cortex-M3 processor is built to offer new degrees of
freedom to MCU users. It brings a complete 32-bit product
range that combines high performance, real-time, low-power
and low voltage operation, while maintaining full integration
and ease of development.
It eases migration from the 1w-bit world with its high level of
feature integration, its easy-to-use architecture, its low-power
capability and cost effectiveness.
The STM32 family helps you create new applications and design
in the innovations you have been long dreaming about.
STMicroelectronics is a lead partner in developing Cortex M
cores and, with the STM32, offers a comprehensive portfolio
of advanced MCUs that we are committed to extending in
capability, price range and features to cover the needs of
microcontroller convergence.
STM32, a solid foundation for growth

The STM32 platform is a strong foundation to build our
portfolio. With new products addressing new applications, the
complete STM32 product family now comprises three series,
each dedicated to a specific segment.
More choice with STM32 series
The general purpose series addresses a wide range of
applications, from the lowest price sensitive design to the
computing intensive, high memory footprint.
Get the highest performance with the F series for computingintensive applications and advanced connectivity. The F series
maintains compatibility with the F1 series. Design ultra lowpower applications with the L series for those who are power
conscious and seek the absolute lowest energy consumption.
The L series maintains compatibility with the F series.
STM32, the optimal platform choice
The STM32 is the optimal choice to support many applications
with the same platform. All product lines in the three series are
pin to pin and software compatible, making it easy to upgrade
to higher or downgrade to lower memory size. N umerous
applications may be addressed using the sole STM32 platform.
For Development Boards, See Pages z x-100
w0 Cortex Resource Guide
www.E mb ed d ed Developer.com
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Any C h ip.
Find a Solution to your nex t Emb edded Challenge.
Do the Researc h you should, b ut never had time for.
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you compare your best options side-by-side from different
manufactures. Click on the device you want, and a product
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download datasheets, and more. P lus--H earst stock check
gives you up-to-date inventory on every device.
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FINDE. V ERG L EICH E. K AUFE
Th e S ites f or E ng ineers with a J ob to Do.
C ORTEX - M 3
SI L I C ON
STMicroelectronics
STM32L Microcontroller F amily

ARM Cortex-M3 32 MHz CPU
32 to 384 K bytes of embedded Flash, up to 48 K bytes of
SRAM and up to 12 K bytes of data EEPROM
Three lines0pin-to-pin, software and peripheral compatibility
Pin-to-pin compatibility with STM32F series except V BAT
(not present on the STM32L)
Ultra low energy consumption0down to 18v A/DMIPS
Supply voltage01.wv to 3.w V
Six ultra low-power modes0down to 2x0 nA
Ultra low-power dynamic modes0low-power run down to
10.4 m A; low-power sleep down to w.1 m A with one
timer
Economical Run mode consumption down to 230 MHz
from Flash at zero wait states with dynamic voltage
scaling (3 ranges)
The STM32L MCU family, based on the Cortex-M3 core,
extends the ultra low-power portfolio in performance, features,
memory size and package pin count. The STM32L family
combines very high-performance and ultra low-power
consumption, using optimized architecture and our proprietary
ultra low-leakage process, shared with the STM8L family. The
STM32L family is available in three different lines, so optimizing
the STM32 family for applications requiring performance
combined with ultra low-power operation.
Rich set of high end analog and digital peripherals

-40 C to . 8v C operating temperature range
STM32 Dev elopment Tools
STMicroelectronics STM32 family of 32-bit ARM Cortex-M
core-based microcontrollers are supported by a complete
range of high-end and low-cost evaluation, software, debugging
and programming tools.
This complete line includes third party solutions that come
complete with C/C. . compiler, integrated development
environment and in circuit debugger/programmer featuring a
JTAG application interface. Developers can also explore and
start applications easily with any of a range of affordable,
easy to use starter kits.
The superb combination of a state the art and efficient library
of software drivers and extensive support for all major tool
providers offers a fast route to best fit and an optimized
development process.
SI L I C ON
STMicroelectronics
C ORTEX - M 3
Ad d i t i o n a l F e a t u r e s :
Up to six ultra low-power modes0
Low-power run mode0the CPU is still running. Execution
is done from RAM with a low-speed oscillator (RTC or
internal). Consumption is 10.4 A typical.
Low-power sleep mode0offers the possibility of keeping the
RTC and a few other peripherals active (such as the timer)
with a consumption of w.1 A typical with one timer activated.
The CPU is off. The Flash is switched off and the regulator is
put into ultra low-power mode, the CPU is stopped, the RTC
and peripherals can be activated.
The 2 modes above are ideal for applications that need constant
monitoring.
Stop modes (2 modes)0the CPU, main clocks and peripherals
are off. The RTC can be on or off (2 modes). Wake up can be
done through an interrupt on the peripherals. SRAM and
context are kept.
Standby modes (2 modes)0the CPU, main clocks and
peripherals are off. The RTC can be on or off (2 modes).
Backup registers are preserved. Wakeup can be done through
wake-up pins.
Supply monitoring and resets
Extended battery lifetime down to 1.wv V

- BOR complies with all V DD rise/fall times, so no
constraints on power supply shape. When BOR is not
activated, the STM32L starts at V DD = 1.wv.
STM32L firmware library0complete package consisting of
device drivers for all the standard device peripherals.
Full reset circuitry, supply monitoring

- Power-on reset/power-down reset, permanently enabled
(zero power)
- Brown-out detection (BOR) can be on or off in low-power
modes
- Programmable voltage detection can be on or off
w3
C ORTEX - M 3
STM32W
SI L I C ON
STMicroelectronics
Microcontroller F amily
K e y F e a tu re s
Outstanding 2.4 GHz radio performances to IEEE 802.1v.4
Best-in-class code density, because of its ARM Cortex-M3
core
I ntegrated 2u4 GH z radio microcontroller enables
low-cost wireless network implementation
With these new members, the STM32 family is expanding to
the wireless network domain, bringing outstanding radio and
low-power microcontroller performances in a single systemon-chip (SoC). With a configurable total link budget of up to
10z dB and the efficiency of the ARM Cortex-M3 core, the
STM32W is the perfect fit for the wireless sensor network
market. Compliant with the IEEE 802.1v.4 radio standard, this
open and flexible platform supports the most popular protocol
stacks such as RF4CE, Z ig-Bee-PRO, wLoWPAN and more.
Coming with a complete and low-cost development tool offer,
the STM32W takes full advantage of the unrivalled ST ARM
Cortex-M3 portfolio.
Low-power architecture
Open platform with extra resources for application
integration
Configurable I/Os, ADC, timers, SPI, UART
Main software libraries0EmberZ net PRO, RF4CE, IEEE
802.1v.4 MAC
Available in both SoC (Q FN 48) and coprocessor (Q FN 40)
versions
K ey Benefits
Cost efficiency through a true SoC
Open platform supporting IEEE 802.1v.4 based protocol
stacks
Wide STM32 Cortex-M3 developers community
Unmatched network throughput and latency
Longer battery lifetime
SI L I C ON
Texas Instruments
C ORTEX - M 3
Stellaris
K e y F e a tu re s
Space and cost sav ing integration
- Stellaris is the only ARM MCU with 10/100 Ethernet MAC/
PHY integrated on chip.
- Only Stellaris offers a complete, fully functional and
efficient driver library in ROM.
F ast I wO and F lash performance
- Only Stellaris runs peripherals at full system speed.
- Only Stellaris enables single cycle Flash and SRAM access
up to v0 MHz.
Bigger and better memory
- Only Stellaris offers up to z w K B SRAM.
- Only Stellaris enables the MPU to flexibly protect your
memory.
Texas Instruments (TI) is the industry leader in bringing 32-bit
capabilities and the full benefits of ARM Cortex-M3 based
microcontrollers to the broadest reach of the microcontroller
market. N ow with more than 180 compatible ARM Cortex-M3
based Stellaris microcontrollers and many Stellaris evaluation,
development and reference design kits, Stellaris offers the
performance, integration, power and price-point requirements of
nearly any industrial application. Stellaris with Cortex-M3 offers
a direct path to the strongest ecosystem of development tools,
software and knowledge in the industry. Designers who migrate
to Stellaris will benefit from great tools, small code footprint and
outstanding performance. Even more important, designers can
enter the TI ARM ecosystem with full confidence in a compatible
road map from m1 to 1 GHz.
Stronger tools, solutions, and software

- Easiest time-to-market with quick start EV K s, open-tool
RDK s and application-specific production modules.
- Richest collection of software libraries with StellarisWare.
The Texas Instruments1Stellaris ARM Cortex-M3 microcontrollers are an ideal fit for a variety of wireless solutions with
their high degree of performance and integrated connectivity.
Stellaris and TI1s RF solutions drive intelligence and advancing
functionality in applications such as metering, home automation
and security.
For Development Boards, See Page 101-102
wv
C ORTEX - M 3
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Toshiba
TX03 Series of Microcontrollers

Toshiba1s TX 03 Microcontroller Series is built around the ARM
Cortex-M3 CPU technology. The ARM Cortex-M3 processing
core offers high code density, efficient data RAM usage,
fast interrupt handling and higher processing efficiency than
ARMx or ARMz cores, and is strongly supported by many
third-party tools and software suppliers. Combining the
Cortex-M3 processing core with Toshiba1s memory, logic and
analog technology base has enabled us to set some industry
benchmarks for Cortex-M3 processing core-based MCUs0
2 Mbytes and 1 Mbyte on-chip FLASH (TMPM3w0/3w2)
144 MHz CPU (TMPM320)
1 Mbyte on-chip embedded DRAM (TMPM320)
vV Cortex-M3 MCUs (TMPM3x0/380)
) Hardware engine for vector motor control (TMPM3x0)
Toshiba1s TX 03 MCUs are divided into x product families0
A typical Toshiba TX 03 is the TMPM380FY FG. Operated from

a vV V CC for better noise immunity and dynamic range,
TMPM380 is ideal for industrial signal control/servo
applications like inverters, heaters, motors and compressors.
Dual 3-phase PWM outputs, or up to three 2-phase PWM
outputs are used to shape waveforms on the working side of
high-current drive circuits via IGBTs or FETs, while the 12-bit
ADC tracks the results so the control algorithm can make
needed corrections. Z ero-wait-state FLASH memory improves
the determinism of the program timings, and the on-chip debug
control, watchpoints and embedded trace macrocell support
real-time debugging and performance tuning.
For Development Boards, See Page 103
ww Cortex Resource Guide
RESOU RC E
GU I D E
C ORTEX - M 4
C ORTEX - M 4 : C o m i n g i n 2 0 1 1
Freescale
SI L I C ON
K e y F e a tu re s
Ultra Low-Power
10 low-power modes with power and clock gating for
optimal peripheral activity and recovery times. Stop
currents of < v00 nA, run currents of < 200 A/MHz, 4 s
wake-up from Stop mode
Full flash programming and analog peripheral operation
down to 1.x1V for extended battery life
Low-leakage wake-up unit with up to eight internal modules
and sixteen pins as wake-up sources in low-leakage stop
(LLS)/very low-leakage stop (V LLS) modes
Low-power timer for continual system operation in reduced
power state
K inetis 32-bit MCUs represent the most scalable portfolio of

ARM Cortex-M4 based microcontrollers in the industry. The K 10
MCU family is the entry point into the K inetis portfolio. Devices
start from 32 K B of flash in a small-footprint vxv mm 32Q FN
package extending up to 1 MB in a 144MAPBGA package with
a rich suite of analog, communication, timing and control
peripherals. High memory density K 10 family devices include
a single precision floating point unit and N AN D flash controller.
Pin compatibility, flexible low-power capabilities and innovative
FlexMemory help to solve many of the major pain points for
system implementation.
Flash, SRAM and FlexMemory

32 K B - 1 MB flash. Fast access, high reliability with 4-level
security protection.
8 K B - 128 K B of SRAM
FlexMemory032 bytes - 1w K B of user-segmentable byte
write/erase EEPROM for data tables/system data. EEPROM
with over 10M cycles and flash with 100 sec write time
(brownouts without data loss or corruption). N o user or
system intervention to complete programming and erase
functions and full operation down to 1.x1V . In addition,
FlexN V M from 32 K B - v12 K B for extra program code, data
or EEPROM backup
Mixed-Signal Capability
Up to two high-speed 1w-bit ADCs with configurable
resolution. Single or differential output mode operation for
improved noise rejection. v00 ns conversion time
achievable with programmable delay block triggering
Up to two 12-bit DACs for analog waveform generation for
audio applications
Up to three high-speed comparators providing fast and
accurate motor over-current protection by driving PWMs to
a safe state
Up to two programmable gain amplifiers with xw4 gain for
small amplitude signal conversion
Accurate on-chip voltage reference eliminates need for
accurate external voltage reference IC reducing overall
system cost
SI L I C ON
Freescale
K e y F e a tu re s (C o n tin u e d )
Performance
ARM Cortex-M4 core . DSP. v0 - 120 MHz, single cycle
MAC, single instruction multiple data (SIMD) extensions,
optional single precision floating point unit
Up to 32-channel DMA for peripheral and memory servicing
with reduced CPU loading and faster system throughput
Cross bar switch enables concurrent multi-master bus
accesses, increasing bus bandwidth
Up to 1w K B of instruction/data cache for optimized bus
bandwidth and flash execution performance
Independent flash banks allowing concurrent code
execution and firmware updating with no performance
degradation or complex coding routines.
Timing and Control
Up to four FlexTimers with a total of 20 channels. Hardware
dead-time insertion and quadrature decoding for motor
control
Carrier modulator timer for infrared waveform generation in
remote control applications
Four-channel 32-bit periodic interrupt timer provides time
base for RTOS task scheduler or trigger source for ADC
conversion and programmable delay block
C o m i n g i n 2 0 1 1 : C ORTEX - M 4
Reliability, Safety and Security

Memory protection unit provides memory protection for all
masters on the cross bar switch, increasing software
reliability
Cyclic redundancy check engine validates memory contents
and communication data, increasing system reliability
Independent-clocked COP guards against clock skew or
code runaway for fail-safe applications such as the IEC
w0x30 safety standard for household appliances
External watchdog monitor drives output pin to safe state
external components if watchdog event occurs
External Peripheral Support
FlexBus external bus interface provides interface options to
memories and peripherals such as graphics displays.
Supports up to w chip selects.
Secure digital host controller supports SD, SDIO, MMC or
CEATA cards for in-application software upgrades, media
files or adding Wi-Fi support
N AN D flash controller supports up to 32-bit ECC current
and future N AN D types. ECC management handled in
hardware, minimizing software overhead.
Human-Machine Interface
X trinsic low-power touch-sensing interface with up to 1w
inputs. Operates in all low-power modes (minimum current
adder when enabled). Hardware implementation avoids
software polling method. High sensitivity level allows use of
overlay surfaces up to v mm thick.
Connectivity and Communications
Up to six UARTs, with IrDA support including one UART
with ISOx81w smart card support. V ariety of data size,
format and transmission/reception settings supported for
multiple industrial communication protocols
Inter-IC Sound (I2S) serial interface for audio system
interfacing
Up to two CAN modules for industrial network bridging
Up to three DSPI and two I2C
wz
Freescale
SI L I C ON
K e y F e a tu re s
Ultra Low-Power
currents of < v00 nA, run currents of < 200 A/MHz, 4 s
power state

ARM Cortex-M4 MCUs in the industry. The K 20 MCU family is
pin-, peripheral- and software-compatible with the K 10 MCU
family and adds full- and high-speed USB 2.0 On-The-Go with
device charger detect capability. Devices start from 32 K B of
flash in v x v mm 32Q FN packages extending up to 1 MB in a
144MAPBGA package with a rich suite of analog, communication, timing and control peripherals. High memory density K 20
family devices include a single precision floating point unit and
N AN D flash controller.

32 K B - 1 MB flash. Fast access, high reliability with 4-level
security protection
8 K B - 128 K B of SRAM
FlexMemory032 bytes - 1w K B of user-segmentable byte
with over 10M cycles and flash with 100 usec write time
(brownouts without data loss or corruption). N o user or
FlexN V M from 32 K B - v12 K B for extra program code, data
or EEPROM backup
Up to two 12-bit DACs for analog waveform generation for
audio applications
a safe state
system cost
x0 Cortex Resource Guide
SI L I C ON
Freescale
Performance
ARM Cortex-M4 core . DSP. v0-120MHz, single cycle MAC,
single instruction multiple data (SIMD) extensions, single
precision floating point unit
Up to 1wK B of instruction/data cache for optimized bus
Independent flash banks allowing concurrent code
execution and firmware updating with no performance
degradation or complex coding routines.
X trinsic low-power Touch Sense Interface with up to
1w inputs. Operates in all low-power modes (minimal
current adder when enabled). Hardware implementation
avoids software polling method. High sensitivity level allows
use of overlay surfaces up to vmm thick Ultra Low-Power
currents of < v00 nA and run currents of < 200 A/MHz,
4 s wake-up from Stop mode
(LLS)/very low-leakage stop (V LLS) mode
power state
Timing and Control

Up to four FlexTimers with a total of 20 channels. Hardware
control Carrier modulator timer for infrared waveform
generation in remote control applications
masters on cross bar switch, increasing software reliability
code runaway for fail-safe applications, e.g. IEC w0x30
external components if watchdog event occurs External
Peripheral Support
Supports up to six chip selects
hardware, minimizing software overhead.
x1
Freescale
SI L I C ON

pin, peripheral and software compatible with the K 10 MCU
family and adds a flexible low-power segment LCD controller
with support for up to 320 segments. Devices start from w4 K B
of flash in w4Q FN packages extending up to v12 K B in a
144MAPBGA package with a rich suite of analog, communication, timing and control peripherals.
K e y F e a tu re s
inputs. Operates in all low-power modes (minimal current
overlay surfaces up to v mm thick.
Flexible, low-power LCD controller with up to 320 segments
(40x8 or 44x4). LCD blink mode enables low average power
while remaining in low-power mode. Segment fail detect
guards against erroneous readouts and reduces LCD test
costs. Frontplane/backplane reassignment provides pin-out
flexibility easing PCB design and allows LCD configuration
changes via firmware with no hardware re-work. Supports
multiple 3V and vV LCD panel sizes with fewer segments
(pins) than competitive controllers and no external
components. Unused LCD pins can be configured as other
GPIO functions.
Ultra Low-Power
currents of < v00 nA and run currents of < 200 A/MHz,
4 s wake-up from Stop mode.
power state Flash, SRAM and FlexMemory
w4 K B - v12 K B flash. Fast access, high reliability with
four-level security protection
1w K B - 128 K B of SRAM
FlexMemory032 bytes - 4 K B of user-segmentable byte
(brownouts without data loss/corruption). N o user or
FlexN V M from 32 K B - 2vw K B for extra program code, data
or EEPROM backup.
SI L I C ON
Freescale
Performance
ARM Cortex-M4 core . DSP. v0 - 100MHz, single cycle
MAC, single instruction multiple data (SIMD) extensions
Up to 1w-channel DMA for peripheral and memory servicing
Independent flash banks allows concurrent code execution
and firmware updating with no performance degradation or
complex coding routines
Up to two 12-bit DACs for analog waveform generation
for audio
a safe state
system cost
Timing and Control

Up to three FlexTimers with a total of 12 channels.
Hardware dead-time insertion and quadrature decoding for
motor control
remote control
Up to six UARTs with IrDA support, including one UART
with ISOx81w smart card support. V ariety of data size,
interfacing
Up to two CAN for industrial network bridging
code runaway for fail-safe applications, e.g. IECw0x30
Supports up to w chip selects.
x3
Freescale
SI L I C ON
USB 2.0 On-The-Go . device charger detect optimizes
charging current/time for portable USB devices enabling
longer battery life. Integrated USB low voltage regulator
supplies up to 120 mA off chip at 3.3V to power external
components from vV input
Up to six UARTs with IrDA support including one UART with
ISOx81w smart card support. V ariety of data size, format
and transmission/reception settings supported for multiple
industrial communication protocols
interfacing
Up to two CAN for industrial network bridging

pin, peripheral and software compatible with the K 10 MCU
family and adds full-speed USB 2.0 On-The-Go with device
charge detect capability and a flexible low-power segment LCD
controller with support for up to 320 segments. Devices start
from w4K B of flash in w4Q FN packages extending up to v12K B
in a 144MAPBGA package with a rich suite of analog, communication, timing and control peripherals.
inputs. Operates in all low-power modes (minimal current
overlay surfaces up to v mm thick
Flexible, low-power LCD controller with up to 320 segments
(40 x 8 or 44 x 4). LCD blink mode enables low average
power while remaining in low-power mode. Segment fail
detect guards against erroneous readouts and reduces LCD
test costs. Frontplane/backplane reassignment provides
pinout flexibility, easing PCB design and allows LCD
configuration changes via firmware with no hardware
re-work. Supports multiple 3V and vV LCD sizes with fewer
segments (pins) than competitive controllers and no
external components. Unused LCD pins can be configured
as other GPIO functions
w4 K B - v12 K B flash. Fast access, high reliability with
fourlevel security protection
1w K B - 128 K B of SRAM
FlexMemory032 bytes - 4 K B of user-segmentable byte
FlexN V M from 32 K B - 2vw K B for extra program code, data
or EEPROM backup
SI L I C ON
Freescale
Performance
ARM Cortex-M4 core . DSP. v0 - 100 MHz, single cycle
MAC, single instruction multiple data (SIMD) extensions
Up to 1w-channel DMA for peripheral and memory servicing
Independent flash banks allow concurrent code execution
and firmware updating
for audio
a safe state
system cost
Timing and Control
Up to 3 FlexTimers with a total of 12 channels. Hardware
control
remote control
Ultra Low-Power
currents of < v00 nA and run currents of < 200 A/MHz, 4 s
Low-power timer with continual system operation in
reduced power state
code runaway for fail-safe applications
external components
xv
Freescale
SI L I C ON

ARM Cortex-M4 MCUs in the industry. The K w0 MCU family
includes IEEE 1v88 Ethernet, full- and high-speed USB 2.0
On-The-Go with device charge detect capability, hardware
encryption and tamper detection capabilities. Devices start from
2vw K B of flash in 100LQ FP packages extending up to 1 MB in
a 2vwMAPBGA package with a rich suite of analog, communication, timing and control peripherals. High memory density K w0
family devices include an optional single precision floating point
unit, N AN D flash controller and DRAM controller.
xw Cortex Resource Guide
Hardware Encryption coprocessor for secure data transfer
and storage. Faster than software implementations and with
minimal CPU loading. Supports a wide variety of algorithms
- DES, 3DES, AES, MDv, SHA-1, SHA-2vw
System security and tamper detect with secure real-time
clock with independent battery supply. Secure key storage
with internal/external tamper detect for unsecure flash,
temperature, clock, and supply voltage variations and
physical attack detection
code runaway for fail-safe applications, e.g. IEC w0x30
IEEE 1v88 Ethernet MAC with hardware time stamping
provides precision clock synchronization for real-time
industrial control
USB 2.0 On-The-Go . device charger detect optimizes
charging current/time for portable USB devices enabling
longer battery life. Integrated USB low voltage regulator
supplies up to 120 mA off chip at 3.3V to power external
components from vV input. Up to 480 Mbps with external
ULPI PHY
Up to six UARTs with IrDA support, including one UART
with ISO x81w smart card support. V ariety of data size,
interfacing
Two CAN for industrial network bridging
SI L I C ON
Freescale
Performance
ARM Cortex-M4 core . DSP. 100 - 1v0MHz, single cycle
MAC, single instruction multiple data (SIMD) extensions,
single precision floating point unit
Up to 1wK B of instruction/data cache for optimized bus
Independent flash banks allow concurrent code execution
and firmware updating
FlexBus external bus (bus interface provides interface
options) provides interface options to memories and
peripherals such as graphics displays. Supports up to six
chip selects
CE-ATA cards for in-application software upgrades, media
hardware, minimizing software overhead
DRAM controller supports connection of DDR, DDR2 and
low-power DDR memories. Max. frequency (clock/data)
12v/2v0 MHz

2vw K B - 1 MB flash. Fast access, high reliability with
four-level security protection
w4 K B - 128 K B of SRAM
FlexMemory032 bytes - 1w K B of user segmentable byte
with over 10M cycles and flash with 100 usec write time
FlexN V M from 2vw K B - v12 K B for extra program code,
data or EEPROM backup
X trinsic low-power with up to 1w inputs. Operates in all
low-power modes (minimal current adder when enabled)
Ultra Low-Power
currents of < v00 nA and run currents of < 200 A/MHz, 4 s
down to 1.x1V
power state
Up to four high-speed 1w-bit ADCs with configurable
resolution. v00ns conversion time achievable with
programmable delay block triggering
for audio
a safe state
Up to four programmable gain amplifiers with xw4 gain for
accurate external voltage reference IC
xx
SI L I C ON

N X P1s Cortex-M4 MCUs specifically address digital-signalcontrol markets that demand an efficient, easy-to-use blend of
control and signal processing capabilities. These products are
an ideal single-chip solution for applications such as motor
control, power conversion, audio, and communications.
These DSC processors offer a high level of system integration,
reducing system design cost and complexity, while simplifying
the design cycle using a single tool chain. Additionally, the
Cortex-M4 based products will be upwardly code compatible
from existing Cortex-M3 and Cortex-M0 processors.
The LPC4000 combines the industry leading MCU capabilities
of the Cortex-M family with specialized DSP instructions and
capabilities including0
Single-cycle, Multiply-ACcumulate (MAC) instructions
Optimized, Single-Instruction, Multiple-Data (SIMD)
instructions
Saturated, arithmetic instructions,
N X P1s new Digital Signal Control (DSC) processors, based
on the ARM Cortex-M4 microcontroller core, bring highperformance signal processing capabilities within the reach of
the typical MCU programmer.
A single-precision Floating Point Unit (FPU)

N X P was a lead licensee of the Cortex-M4 and was the first
manufacturer to show working silicon at the Embedded Systems
Conference (ESC) in Silicon V alley in April, 2010.
The ARM Cortex-M4 processor is the latest embedded

processor by ARM specifically developed to address digital
signal control markets that demand an efficient, easy-to-use
blend of control and signal processing capabilities.
The combination of high-efficiency signal processing
functionality with the low-power, low cost and ease-of-use
benefits of the Cortex-M family of processors is designed to
satisfy the emerging category of flexible solutions specifically
targeting the motor control, automotive, power management,
embedded audio and industrial automation markets.
In addition to the standard set of peripherals, the LPC4000 family includes new highly-configurable peripherals which provide
maximum flexibility for designers. A Cortex-M0 core has been
added to the LPC4000 as a configurable peripheral handler to
offload many of the data movement duties that drain the bandwidth of the core. This allows the Cortex-M4 to concentrate on
what it does best0crunching numbers for digital signal control
applications.
SI L I C ON
The ARM Cortex-M4 processor offers significant benefits to
system and software developers0
Thumb-2 technology
DSP and SIMD extensions
Single-cycle MAC (up to 32 x 32 . w4 -> w4)
Single-precision FPU
Integrated, configurable N V IC
Compatible with Cortex-M3
Configurable for ultra low-power including Deep Sleep
Mode and Wakeup Interrupt Controller
The N X P Cortex-M4 family will be an important part of N X P1s
High-Performance Mixed Signal portfolio, providing embedded
system designers with easy-to-program 32-bit DSCs which are
code- and tool-compatible with other N X P ARM-based MCU
products. Implemented using an ultra low-leakage z 0-nm
process technology, the family will be the most energy
efficient 32-bit embedded processors for digital signal
controllers.
Energy efficient digital signal control
The Cortex-M4 offers unparalleled capability to integrate 32-bit
control with leading digital signal processing techniques for
markets that require very high levels of energy efficiency.
N X P1s LPC4000 Cortex-M4 processor-based family is planned

to be introduced to the broad market at the end of 2010.
Easy -to-use technology

The Cortex-M4 makes signal processing algorithm development
easy through an excellent ecosystem of software tools and the
Cortex Microcontroller Software Interface Standard (CMSIS).
CMSIS is a vendor-independent hardware abstraction layer for
the Cortex-M processor series. The CMSIS enables consistent
and simple software interfaces to the processor for interface
peripherals, real-time operating systems, and middleware,
simplifying software re-use, reducing the learning curve for new
microcontroller developers and reducing the time-to-market for
new devices.
xz
RESOU RC E
GU I D E
C ORTEX - A8
C ORTEX - A8
SI L I C ON
Freescale
iuMX5 1 Microcontrollers
Smart Speed Technology enables minimum power
consumption in both active and various low-power modes
Multimedia performance is enhanced with V ideo and Audio
Codecs, N eon and programmable DMA controller
Powerful graphics acceleration
Interface flexibility - DDR, DDR2, PSRAM, N OR Flash,
N AN D Flash, LCD controller for two displays, CMOS sensor
interface, High-Speed USB On-The-Go plus three High-Speed
USB hosts, high-speed MMC/SDIO, Fast Ethernet controller,
UART, I2C, I2S
Increased security with secure e-commerce, digital rights
management (DRM), information encryption, secure boot,
and secure software downloads
The i.MX v1 processors feature Freescale1s advanced and powerefficient implementation of the ARM Cortex-A8 core, which
operates at speeds as high as 800 MHz. Up to 200 MHz DDR2
and mobile DDR DRAM clock rates are supported.
The applications processors balance the performance, power
consumption, connectivity and multimedia capabilities
necessary to drive today1s latest and greatest products. These
processors are ideal for applications that require advanced user
interfaces, sophisticated video processing, 2D and 3D graphics,
multiple connectivity options and a high level of system
integration.
Benefits include high-performance processing and multimedia
capabilities, hardware acceleration that enables very low-power
consumption for video and graphics, and a high level of
integration to reduce overall system bill of materials. These
processors are also available in extended temperatures for
industrial-focused devices running up to w00 MHz.
For Development Boards, See Page 104
SI L I C ON
Freescale
C ORTEX - A8
Freescale ARM-based i.MX multimedia applications processors

deliver an optimal balance of performance and long battery life
for rich multimedia experiences on the go. The i.MX applications
processor family includes processors based on ARMz , ARM11
and ARM Cortex-A8 core technologies, which are powering new
applications in consumer, automotive and industrial markets that
demand exceptional performance and efficiency. The i.MX family
is part of Freescale1s Energy Efficient Solutions.
Consumer and I ndustrial applications
Freescale1s consumer and industrial i.MX v1 applications
processors balance the performance, power consumption,
connectivity and multimedia capabilities necessary to drive
today1s latest and greatest products. Benefits include high
performance processing and multimedia capabilities, hardware
acceleration that enables very low-power consumption for video
and graphics, and a high level of integration to reduce overall
system bill of materials. These processors are also available in
extended temperatures for industrial-focused devices running
up to w00MHz.
Automotiv e applications
Freescale1s automotive i.MX v1 processors provide what is
necessary to steer today1s most advanced automotive systems.
These processors are ideal for applications that require
advanced user interfaces, sophisticated video processing, 2D
and 3D graphics, multiple connectivity options and a high level
of system integration. Building on the success of the i.MX v1v
in the consumer market, the automotive family of i.MX v1
processors will bring the consumer electronics user experience
and device connectivity into the vehicles of the future.
83
C ORTEX - A8
SI L I C ON
Texas Instruments
Sitara AM35 x Microprocessors
v00MHz ARM Cortex-A8 core provides 1000 MIPS
The new Sitara ARM product family includes high performance
Cortex-A8 based embedded microprocessors (MPUs) with
speeds ranging from w00 MHz up to 1 GHz in current devices.
The portfolio of MPUs includes unique combinations of
peripherals and accelerators to drive down system cost and
expand connectivity options.
Ideal for industrial computing applications, the high performance low-power Sitara AM3vx MPU provides a v00 MHz ARM
Cortex-A8 core enabling users to run full featured operating
systems and experience faster web browsing. The Sitara AM3vx
MPUs offer multiple device packages, industrial temperature
options, peripheral integration, graphic capabilities and high
computational performance at sub-one Watt power levels.
Integrated CAN controller supports local control of sensors

and controllers
Industrial temperature options -40 C to 10v C allows
customers to operate in harsh development environments
DDR2 support reduces overall cost of system memory
Sub-one Watt power consumption eliminates the need for
heat sinks and fans so industrial developers can design
silent and air-tight enclosed solutions
Connectivity options include a high-speed USB 2.0 HS
OTG with built in PHY conserves board space and 10/100
EMAC for network communications,control of industrial
devices and remote rebooting reduces the need for
technicians to physically monitor and service systems
3.3V I/O (AM3vxx) eliminates the need for level shifters and
lowers costs
For Development Boards, See Page 10v
Display subsystem with picture-in-picture, color space

conversion, rotation and resizing support provides flexibility
to connect to LCD display for vibrant, crisp and highresolution images
Software compatible with TI1s OMAP processors
Additional PowerV R SGX graphics engine to accelerate 3D
graphical user interface. The graphics engine can process up
to 10 M polygons/sec and supports OPEN GL ES 2.O.
(AM3v1x only)
SI L I C ON
Texas Instruments
C ORTEX - A8
OMAP 35 30w25 Processors

OMAP3v30 and OMAP3v2v high-performance, applications
processors are based on enhanced OMAP3 architecture.
The OMAP3 architecture is designed to provide best-in-class
video, image, and graphics processing sufficient to support0
Streaming video, 3D mobile gaming, video conferencing,
high-resolution still image, etc. The device supports high-level
operating systems (OSs), such as Linux and Windows CE. This
OMAP device includes state-of-the-art power-management
techniques required for high-performance mobile products.
OMAP 35 30w25 K ey F eatures:
The following subsystems are part of the device0
Microprocessor unit (MPU) subsystem based on the ARM
Cortex-A8 microprocessor
IV A2.2 subsystem with a Cw4x. digital signal processor
(DSP) core
POWERV R SGX subsystem for 3D graphics acceleration
to support display and gaming effects (3v30 only)
Scalable platform of processors available with multimedia rich

peripherals, OpenGL ES 2.0 compatible graphics engine and
DaV inci technology for digital video capabilities Optimized
laptoplike performance at handheld power levels in a single
chip utilize TI1s SmartReflex for even greater power savings
Evaluation module, Linux board support package and OMAP
Developer N etwork help take designs from concept to
production quickly and efficiently.
Up to x20-MHz ARM Cortex-A8 Core
Scalable platform of processors available with multimedia
rich peripherals, OpenGL ES 2.0 compatible graphics
engine and DaV inci technology for digital video capabilities
Optimized laptop-like performance at handheld power
levels in a single chip
Utilize TI1s SmartReflex technology for even greater
power savings
Evaluation module, Linux board support package and OMAP
Developer N etwork help take designs from concept to
production quickly and efficiently.
Camera image signal processor (ISP) that supports

multiple formats and interfacing options connected to a wide
variety of image sensors
Display subsystem with a wide variety of features for multiple
concurrent image manipulation, and a programmable
interface supporting a wide variety of displays. The display
subsystem also supports N TSC/PAL video out.
Level 3 (L3) and level 4 (L4) interconnects that provide
high-bandwidth data transfers for multiple initiators to the
internal and external memory controllers and to on-chip
peripherals
The device also offers0
A comprehensive power and clock-management scheme
that enables high-performance, low-power operation, and
ultra low-power standby features. The device also supports
SmartReflex adaptative voltage control. This power
management technique for automatic control of the
operating voltage of a module reduces the active power
consumption.
Memory stacking feature using the package-on-package
(POP) implementation (CBB and CBC packages only)
For Development Boards, See Pages 10w
8v
C ORTEX - A8
SI L I C ON
Texas Instruments
Sitara AM37 x Microprocessors

DM37 x Applications Processor F amily :
The DM3xx generation of high-performance, applications
processors are based on the enhanced device architecture and
are integrated on TI1s advanced 4v-nm process technology.
This architecture is designed to provide best in class ARM and
Graphics performance while delivering low-power consumption.
This balance of performance and power allow the device to
support the following example applications0
Portable Data Terminals
N avigation
Auto Infotainment
Gaming
Medical Imaging
The Sitara AM3xx microprocessors (MPUs) based on an ARM
Cortex-A8 core with speeds up to 1 GHz offers a 40 percent
increase in performance, twice the graphics performance, and
a 30 percent decrease in power consumption over previous
generations. The MPUs provide hardware and software
scalability with the Sitara ARM MPU product family, allowing
for increased headroom to protect product investments for
customization and product life cycle enhancements.
Available at 300 MHz, w00 MHz, 800 MHz and 1 GHz
performance levels to offer numerous operating points to
meet power and performance budgets while maintaining pin
for pin compatibility
1 GHz Cortex-A8 with N eon co-processor, delivering
up to 2000 DMIPs and offering 4v nm, enables faster user
interfaces, data access and web page downloads for the
highest levels of processor performance and low-power
consumption
PowerV R Graphics Core provides stunning 3D graphics
for more eye-catching GUIs with the support of OpenGL ES
2.0 and renders 20 million polygons per second
Increased SDRAM Controller performance and 100 percent
increase in L1 cache provides an intensified multi-processor
performance and reduces latency
A robust peripheral set including USB HS Host x3, USB
2.0 OTG, MMC/SD card interface x3, 1.8V input/output and
display subsystem with LCD controller and dual 10-bit DACs
allows multiple connectivity options for developers
Home Automation
Human Interface
Industrial Control
Test and Measurement
Single-board Computers
The device can support numerous HLOS and RTOS solutions
including Linux and Windows Embedded CE which are available
directly from TI.
For Development Boards, See Page 10v
RESOU RC E
GU I D E
C ORTEX - R4
C ORTEX - R4
SI L I C ON
Texas Instruments
TMS5 7 0 Safety Microcontrollers

The TMSvx0LS family integrates the ARM Cortex-R4F Floating
Point CPU which offers an efficient 1.w DMIPS/MHz, and has
configurations which can run up to 1w0 MHz roviding more than
2v0 DMIPS. The TMSvx0LS series also provides different Flash
(1MB or 2MB) and data SRAM (128K B or 1w0K B) options with
single bit error correction and double bit error detection.
The TMSvx0 microcontroller family enables customers to easily

build safety related transportation applications. Offered with
large configurations of Flash and RAM, the TMSvx0 ARM
Cortex-R4F core offers up to 1w0 MHz of floating point
performance, more than 2v0 DMIPS. Dual core lockstep,
extensive use of hardware BIST, ECC and parity checking have
allowed Exida to certify the TMSvx0 family as capable for use in
creating SIL3 compliant systems. A wide choice of communication peripherals like CAN and FlexRay, in combination with a
powerful timing coprocessor module (HET) and 12-bit ADC,
makes the family an ideal solution for the transportation industry with specific safety requirements.
The TMSvx0LS series is a high performance automotive grade
microcontroller family which has been certified for use in IEC
w1v08 SIL3 safety systems. The safety architecture includes
Dual CPUs in lockstep, CPU and Memory Built-In Self Test
logic, ECC on both the Flash and the data SRAM, parity on
peripheral memories, and loop back capability on peripheral IOs.
The TMSvx0LS series microcontrollers contain the following0
Dual TMSvx0 1w/32-bit RISC (ARM Cortex-R4F) in Lockstep
Up to 2 Mbyte Program Flash with ECC
Up to 1w0 K byte Static RAM (SRAM) with ECC
Real-Time Interrupt (RTI) Operating System Timer
V ectored Interrupt Module (V IM)
Cyclic Redundancy Checker (CRC) with Parallel Signature
Analysis (PSA)
Direct Memory Access (DMA) Controller
Frequency-Modulated Phase-Locked Loop (FMZ PLL)-Based
Clock Module With Prescaler
Three Multi-buffered Serial Peripheral Interfaces (MibSPI)
Two UARTs (SCI) with Local Interconnect N etwork Interfaces
(LIN )
Three CAN Controllers (DCAN )
High-End Timer (N HET) with dedicated Transfer Unit (HTU)
Available FlexRay Controller with dedicated PLL and
Transfer Unit (FTU)
External Clock Prescale (ECP) Module
Two 1w-Channel 12-bit Multi-Buffered ADCs (MibADC) 8 shared channels between the two ADCs
System Bus Parity with Failure Detection
Error Signaling Module (ESM) with external error pin
V oltage Monitor (V MON ) with out of range reset assertion
Embedded Trace Module (ETMR4)
Data Modification Module (DMM)
RAM Trace Port (RTP)
Parameter Overlay Module (POM)
1w Dedicated General-Purpose I/O (GIO) Pins for Z WT;
8 Dedicated GIO Pins for PGE
1w-bit External Memory Interface (EMIF)
For Development Boards, See Page 10x
RESOU RC E
GU I D E
D EV EL OPM EN T TOOL S
C ORTEX - M 0
N X P Semiconductors Tools
D EV EL OPM EN T K I TS
L PC1100w11C00w1102 Dev elopment K its

L PCXpresso L ow-Cost
Dev elopment Platform
LPCX presso is a new, low-cost development platform available

from N X P. It supports N X P1s ARM-based LPC microcontrollers.
The platform is comprised of a simplified Eclipse-based IDE
and low-cost target boards which include an attached JTAG
debugger.
Designed for simplicity and ease of use, the LPCX presso IDE
(powered by Code Red) will provide software engineers a quick
and easy way to develop their applications. The LPCX presso
target boards are jointly developed by Embedded Artists, Code
Red, and N X P. Two LPCX presso boards have been released. The
first features the LPC1343 with integrated USB 2.0 Full Speed
Device, while the second features the LPC1114.
Embedded Artists L PCXpresso

Base Board
The LPCX presso base board makes it possible for you to get
started with experiments and prototyping immediately. It works
with all the LPCX presso target boards and with the mbed
module. The base board is loaded with different peripherals.
K ey F eatures:
Socket for LPCX presso and mbed module
v0-pin expansion dual row pin list connector
(male, 100 mil pitch) for simple connection external designs
and to a logic analyzer
LPCX presso is an end-to-end solution enabling embedded

engineers to develop their applications from initial evaluation to
final production.
v0-pin expansion dual row header connector (female,

100 mil pitch) for simple connection to breadboard
K ey F eatures:
N X P1s low-cost development platform for LPC families.
USB interface
Eclipse-based IDE using very low-cost target boards
Dimensions01v0 x 180 mm
Battery powering (small coin battery)

Reset pushbutton
The target boards comes with an integrated JTAG Debugger.

N o need for a separate debug probej
Easy upgrade options to full-blown suites (from Code Red)
and hardware kits (from Embedded Artists)
Tools Xpress Order Number:

EA-XPR-021-ND
End-to-end solution for creating applications all the way from

evaluation through to production

EA-XPR-002-ND
z 0 Cortex Resource Guide
C ORTEX - M 3
Atmel Tools
AT91SAM3U w3S Dev elopment K its

SAM3S-EK Ev aluation K it
SAM3U -EK Ev aluation K it
The SAM3S Evaluation K it (SAM3S-EK ) enables evaluation

capabilities and code development of applications running on a
SAM3S4C device. Includes LCD display, Q Touch buttons, JTAG
o USB ports o Z igBEE connector.
The SAM3U Evaluation K it (ATSAM3U-EK ) allows evaluation

of the SAM3U devices. Includes features to demonstrate most
of the product s capabilities. Includes LCD display, JTAG o
USB ports o Z igBEE connector. Also features extension
connectors to allow the users to add new interfaces.

ATSAM3S-EK -ND

ATSAM3U -EK -ND

z1
C ORTEX - M 3
Cypress Semiconductor Tools
PSoC 5 Dev elopment K its

PSoC 5 Dev elopment K it
PSoC 5 F irstTouch
Cypress PSoC programmable system-on-chip architecture

gives you the freedom to not only imagine revolutionary new
products, but the capability to also get those products to market
faster than anyone else. PSoC is a scalable System-on-Chip
platform for 8-, 1w-, and 32-bit applications and combines user
programmable precision analog and digital logic with a highperformance ARM Cortex-M3, 80v1, or M8C CPU cores.
The PSoC v FirstTouch Starter K it is designed to get you

acquainted with Cypress PSoC programmable system-on-chip
design methodology and architecture.
K ey F eatures:
PSoC Development Board test
PSoC CY 8C28 Family Processor Module
PSoC CY 8C38 Family Processor Module (Engineering Sample)
PSoC CY 8Cvv Family Processor Module (Engineering Sample)
MiniProg3 Debug and Evaluation Device
Starter K it
This full-featured starter kit ships with an array of sensors, I/O1s,

projects, and software to allow you to evaluate PSoC and see
what value the solution can provide you. And, in addition to
trying out PSoC v, gain full access to other features of the
FirstTouch Starter K it like Serial Wire Debugging (SWD), an
Accelerometer, a Thermistor, Proximity Sensing, a CapSense
touch-sensing interface, a 12-pin wireless module header, and
even 28 general purpose I/O pins (GPIOs). Whatever your need
for PSoC may be, the PSoC v FirstTouch Starter K it has the tools
to get you started - and hooked - on PSoC.
Prototyping Cable K it
K ey F eatures:
PSoC v FirstTouch Board
USB Cable
USB Cable
12V AC Power Adapter
z V Battery
Q uick Start Guide
Proximity Wire (for use as a Proximity Detection Antenna)
K it CDs, which includes0PSoC Creator , PSoC Designer ,

PSoC Programmer, Projects, and Documentation
Q uick Start Guide K it CD, which includes0PSoC Creator ,

K it Projects, and Documentation

428-3038-ND

428-3039-ND
C ORTEX - M 3
Energy Micro Tools
EF M32GwT Geck o Dev elopment K its

EF M32 Geck o Starter K it
EF M32-G2x x Geck o Dev elopment

K it
The EFM32 Gecko Starter K it is a platform for rapid prototyping

of ultra low-power microcontroller applications. It consists of a
single board with a EFM32G8z 0 MCU, a comprehensive software development environment and a unique Advanced Energy
Monitoring (AEM) system that allows designers to have full
control over their application s energy consumption. All
available I/O is placed on breakout pads for easy access.
The EFM32 Gecko Development K it is a platform for rapid

prototyping of ultra low-power microcontroller applications.
It consists of a mother board, the EFM32G2z 0F 128 daughter
board and a comprehensive software development environment.
A unique Advanced Energy Monitoring (AEM) system is also
included, which allows designers to have full control over their
application s energy consumption.

914-1003-ND

914-1000-ND
EF M32-G8x x Geck o Dev elopment K it

The EFM32 Gecko Development K it is a platform for rapid
prototyping of ultra low-power microcontroller applications.
It consists of a mother board, the EFM32G8z 0F 128 daughter
board with 1w0 segment LCD and a comprehensive software
development environment. A unique Advanced Energy Monitoring (AEM) system is also included, which allows designers to
have full control over their application s energy consumption.

914-1001-ND
z3
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C ORTEX - M 3
N X P Tools
L PC1300 Dev elopment K its

L PC1343 L PCXpresso L ow-Cost
Dev elopment Platform
Embedded Artists L PCXpresso

Base Board
The LPC1343 LPCX presso board with N X P1s ARM Cortex-M3

microcontroller has been designed to make it as easy as
possible to get started with Cortex-M3. The LPCX presso
comprises a target board combined with a JTAG debugger.
A free Eclipse-based IDE from Code Red is also included.
The LPC1343 has 8 K B SRAM, 32 K B Flash, USB 2.0, SSP,
UART, etc.
EA-XPR-001-ND
The LPCX presso base board makes it possible for you to get
started with experiments and prototyping immediately. It works
with all the LPCX presso target boards and with the mbed
module. The base board is loaded with different peripherals.
NXP L PC1300-Stick
EA-XPR-021-ND
L PC1300 Ev aluation Board
Discover the performance of the LPC1313 or LPC1343

Cortex-M3 core with the LPC1313-Stick or LPC1343-Stick.
The LPC-Stick is a small modular evaluation kit with optional
extension boards. The LPC-Stick package provides target
hardware with the relative microcontroller from N X P, user pins
and LEDs for applications use.

5 68-4918-ND
The K eil MCB1000 Evaluation

Board contains the LPC1343
ARM Cortex-M3 processor,
allowing you to create and test
working programs for this
advanced architecture. The
MCB1000 has a wide range of
interfaces making it a great
starting point for your next
Cortex-M3 project.

5 68-4919-ND
zv
C ORTEX - M 3
N X P Tools
L PC17 00 Dev elopment K its

L PC17 00 Ev aluation Board
The K eil MCB1xw0
Evaluation Board,
populated with the
N X P LPC1xw8
microcontroller,
introduces you to
the N X P Cortex-M3
based LPC1xwx
series and allows
you to create and
test working
programs for
this advanced
architecture.
The LPC1xw8 device is a true superset of the LPC1xxx devices
with USB HOST/OTG, v12K Flash and w4K on-chip RAM.

5 68-4816-ND
L PC17 68 Dev elopment K it
The LPC1xw8 Development K it contains all of the hardware and

software required for evaluating and developing with N X P
LPC1x00 series microcontrollers. The LPC1xw8 Development
K it consists of the RDB1xw8 Development board, a fully featured
z 0-day evaluation version of Red Suite 2 from Red Code
and a suite of example programs. The integrated on-board
debug circuit, means that no additional debug probe is needed
when used with Red Suite 2.
EA-XPR-003-ND
NXP L PC17 68 mBed Dev elopment Board

The mbed N X P LPC1xw8 board lets you create prototypes
without having to work with low-level microcontroller details,
so you can experiment and iterate faster than ever. Designers
compose and compile embedded software using a browserbased IDE, then download it quickly and easily, using a simple
drag-and-drop function, to the board1s N X P Cortex-M3
microcontroller LPC1xw8.
Engineers new to embedded applications can use the board to
prototype real products incorporating microcontrollers, while
experienced engineers can use it to be more productive in
early stages of development.

5 68-4916-ND
z w Cortex Resource Guide
C ORTEX - M 3
STMicroelectronics Tools
STM32 Dev elopment K its

STM32-comStick
STM32 Starter K it
The STM32 Starter K it provides complete
sets of hardware and software designed
to help users discover device features
and start application development
quickly and easily and includes
an I/O extension board featuring
a USB connector, CAN transceiver,
IrDA transceiver, SPI Flash and more.
The STM32-comStick is a complete, low-cost evaluation and

development package that provides a fast and easy introduction
to the networking features of the STM32 Connectivity line.
It is specifically designed to help application designers learn
about STM32 features that support 10/100 Ethernet, USB 2.0
full speed device/host/OTG (with on-chip PHY ) and CAN
connectivity. The software package includes an unlimited Hitex
toolchain tailored to the STM32-comStick. Software tools
include an unlimited Tasking C compiler for Cortex to build/rebuild the sample applications and HiTOP IDEs.

497 -9040-ND

497 -605 0-ND
STM32E Starter K it
Hitex STM32 Starter K it provides complete sets of hardware
and software including DashBoard interface for modifying
STM32 parameters and viewing performance indicators,
In-circuit debugging/programming via dedicated USB
connection to the host PC, complete Hitex toolchain0HiTOPv for
programming and debugging, TASK IN G V X C/C. . compiler for
ARM (no code size limit).
497 -10030-ND
STM32-PerformanceStick
The STM32-PerformanceStick is a complete, low-cost
evaluation and development package that provides a fast and
easy introduction to the capabilities of the STM32 family of
microcontrollers and includes STM32F103B (128K Flash),
with Hitex software tools, DashBoard interface and sample
applications.

497 -6289-ND
zx
C ORTEX - M 3

STM32F 103E Starter K it
IAR K ickStart K it for
STM32F103E contains all
the necessary hardware and
software to design, develop,
integrate and test your
applications0Evaluation Board
with STM32F103E, on-board
J-Link JTAG probe, Workbench
(IDE, compiler, debugger).

497 -85 05 -ND
STM32 Ev aluation Board
STM32F 107 C Starter K it

IAR K ickStart K it for
STM32F10xC contains all
the necessary hardware and
software to design, develop,
integrate and test your
applications0Evaluation Board
with TM32F10xC, on-board
J-Link JTAG probe, Workbench
(IDE, compiler, debugger).

497 -9041-ND
MCBSTM32C Ev aluation Board

The K eil MCBSTM32C
Evaluation Board
introduces the new
STM32 Connectivity
family of ARM
Cortex-M3 processorbased devices. The
MCBSTM32C has
a wide range of
interfaces making it
a great starting
point for your next
Cortex-M3 project.
The K eil
MCBSTM32
Evaluation Board
(STM32F103RB)
introduces
you to the
STMicroelectronics
Cortex-M3 family
of ARM devices
and allows you to
create and test
working programs
for this advanced
architecture and includes RealV iew MDK -ARM Evaluation Tools.
497 -9042-ND

MCBSTM32-ND
C ORTEX - M 3

STM32 Ev aluation Board t
uL ink -ME JTAG Adapter
STM32 Ev aluation Board t

uL ink 2 JTAG Adapter
The K eil MCBSTM32 Evaluation Board (STM32F103RB)

introduces you to the STMicroelectronics Cortex-M3 family of
ARM devices and allows you to create and test working
programs for this advanced architecture and includes RealV iew
MDK -ARM Evaluation Tools and uLIN K -ME Debug adapter.
The K eil MCBSTM32 Evaluation Board (STM32F103RB)

introduces you to the STMicroelectronics Cortex-M3 family of
ARM devices and allows you to create and test working
programs for this advanced architecture and includes RealV iew
MDK -ARM Evaluation Tools and uLIN K -ME Debug adapter.

MCBSTM32U ME-ND

MCBSTM32U -ND
STM3210B Starter K it
STM32 Primer
Raisonance STM32
Primer with RIDE
(debug up to 32 K of
code), GN U C/C. .
compiler, and a fun,
stimulating learning
and development
platform with
MEMS-based controls
and integrated RLink
(USB/JTAG).
The STM3210B
Raisonance REva
Starter K it provides
a complete set of
hardware and software and includes
mother board and
daughter board with
STM32 target device,
RIDE IDE, GN U
C/C. . compiler,
Debugger, RLink
USB/JTAG probe and
programmer.

497 -605 3-ND

497 -6049-ND
zz
C ORTEX - M 3

STM3210C Starter K it
STM3210B-EV AL Ev aluation Board
The Raisonance REva

Starter K it for STM32
provides complete sets of
hardware and software
and includes mother board
and daughter board with
STM32 target device, RIDE
IDE, GN U C/C. . compiler,
Debugger, RLink
USB/JTAG probe and
programmer.

497 -9043-ND
The K eil MCBSTM32 Evaluation

Board (STM32F103RB)
introduces you to the
STMicroelectronics Cortex-M3
family of ARM devices and
allows you to create and test
working programs for this
advanced architecture and
includes RealV iew MDK -ARM
Evaluation Tools and uLIN K -ME
Debug adapter.

497 -6048-ND
STM3210E Ev aluation Board
STM3210C Ev aluation Board
The STM3210E
evaluation board for
the STM32F103Z E
includes full speed
USB 2.0 interface,
2x CAN 2.0A/B
compliant interface,
I C, SPI, USART,
smartcard support
and external
SRAM and Flash
memory.

497 -6438-ND
The STM3210C
evaluation board for
the STM32F10xV CT
includes full speed USB
2.0 interface (device or
host/OTG), Ethernet, CAN
2.0A/B compliant
interface, I C, SPI, 2x
USART, smartcard
support.

497 -8924-ND
C ORTEX - M 3
Texas Instruments Tools
Stellaris Dev elopment K its

L M3S811 Ev aluation K its
L M3S1968 Ev aluation K its
A compact and versatile

evaluation platform for
LM3SX 00 series,
spanning the design
spectrum from evaluation
to prototyping to
application-specific
design by functioning
as both an evaluation platform for the Stellaris LM3S811
microcontroller and a serial in-circuit debug interface for any
Stellaris microcontroller-based target board.
A compact and versatile

evaluation platform for
LM3S1000 Series. Each
board has an In-Circuit
Debug Interface (ICDI)
that provides hardware
debugging functionality
not only for the on-board
Stellaris devices, but also
for any Stellaris microcontroller-based target board.
L M3S811 Ev
L M3S811 Ev
L M3S811 Ev
L M3S811 Ev
L M3S811 Ev
L M3S1968 Ev
L M3S1968 Ev
L M3S1968 Ev
L M3S1968 Ev
L M3S1968 Ev
aluation K
aluation K
aluation K
aluation K
aluation K
it with Code Red Tools: 7 26-1129-ND

it with CodeSourcery tools: 7 26-1042-ND
it with Code Composer Studio tools: 296-25 7 83-ND
it with I AR tools: 7 26-1043-ND
it with K eil tools: 7 26-1044-ND
L M3S2965 CAN Ev aluation K its

The Stellaris LM3S2z wv
CAN Evaluation K it
provides a compact and
versatile evaluation
platform for CAN enabled
LM3S2000 series. Each
debugging functionality not only for the on-board Stellaris
devices, but also for any Stellaris microcontroller-based target
board. The kit is a fully operational CAN N etwork-in-a-box, with
a quickstart sample application that includes a CAN network and
CAN traffic.
aluation K
aluation K
aluation K
aluation K
aluation K

it with CodeSourcery Tools: 7 26-1083-ND
it with Code Composer Tools: 296-25 7 7 9-ND
it with I AR Tools: 7 26-1084-ND
it with K eil Tools: 7 26-1082-ND
L M3S37 48 Ev aluation Boards

The Stellaris LM3S3x48
Evaluation Board for the
LM3S3000 series, highlights the LM3S3x48
microcontroller1s key
features including a USB
2.0 full-speed (12 Mbps)
Host/Device controller,
Analog-to-Digital
Converter (ADC), and serial interfaces.
The evaluation kit is complete with tools from either0Code
Red, CodeSourcery, TI (Code Composer), IAR or K eil.
L M3S2965
L M3S2965
L M3S2965
L M3S2965
L M3S2965
L M3S37
L M3S37
L M3S37
L M3S37
L M3S37
CAN Ev
CAN Ev
CAN Ev
CAN Ev
CAN Ev
aluation K
aluation K
aluation K
aluation K
aluation K

it with Code Sourcery Tools: 7 26-1049-ND
it with Code Composer Tools: 296-25 7 80-ND
it with I AR Tools: 7 26-105 1-ND
it with K eil Tools: 7 26-105 3-ND
48 Ev
48 Ev
48 Ev
48 Ev
48 Ev
aluation Board with Code Red Tools: 7 26-1187 -ND

aluation Board with CodeSourcery Tools: 7 26-1186-ND
aluation Board with Code Composer Tools: 296-25 7 81-ND
aluation Board with I AR Tools: 7 26-1185 -ND
aluation Board with K eil Tools: 7 26-1184-ND
101
C ORTEX - M 3
Stellaris Dev elopment K its

L M3S6965 Ethernet Ev aluation K its
L M3S8962 Ethernett CAN Ev al K its
An evaluation platform
for Ethernet enabled
LM3Sw000 series. Each
not only for the onboard Stellaris devices, but also for any Stellaris microcontroller-based target board.
An evaluation platform for

Ethernet . CAN enabled
LM3S8000 series. Each
not only for the on-board
Stellaris devices, but also
for any Stellaris microcontroller-based target board. The evaluation kits contain all cables, software, and documentation needed
to develop and run applications easily.

L M3S6965
L M3S6965
L M3S6965
L M3S6965
L M3S6965
Ethernet Ev
Ethernet Ev
Ethernet Ev
Ethernet Ev
Ethernet Ev
aluation K
aluation K
aluation K
aluation K
aluation K

it with Code Sourcery Tools: 7 26-105 0-ND
it with Code Composer Tools: 7 26-105 4-ND
it with I AR Tools: 7 26-105 2-ND
it with K eil Tools: 7 26-105 4-ND

L M3S8962 Ethernett CAN Ev aluation K it with Code Red Tools: 7 26-1133-ND
L M3S8962 Ethernett CAN Ev aluation K it with CodeSourcery Tools: 7 26-1086-ND
L M3S8962 Ethernett CAN Ev aluation K it with Code Composer Tools: 296-25 7 84-ND
L M3S8962 Ethernett CAN Ev aluation K it with I AR Tools: 7 26-1087 -ND
L M3S8962 Ethernett CAN Ev aluation K it with K eil Tools: 7 26-1085 -ND
L M3S9B90 Ev aluation K its

LM3Sz Bz 0 Ethernet. USB
OTG Evaluation K it
provides a low-cost
evaluation platform for the
LM3Sz 000 series. The kit
includes two boards0the
EK -LM3Sz Bz 0 evaluation
board, and an In-Circuit
board. The evaluation board features a simple, streamlined
design for 32-bit Stellaris-based application with industrial
connectivity, highlighting the Stellaris LM3Sz Bz 0 microcontroller1s simultaneous integrated 10/100 Ethernet MAC/PHY ,
fullspeed USB OTG interfaces, and convenient connection to
the MCU1s GPIO ports.
L M3S9B92 Ev aluation K its

LM3Sz Bz 2 Ethernet. USB
OTG Evaluation K it
provides a low-cost
evaluation platform for the
LM3Sz 000 series. The kit
includes two boards0the
EK -LM3Sz Bz 2 evaluation
board and an In-Circuit
board. The evaluation board features a simple, streamlined
design for 32-bit Stellaris-based application with industrial
connectivity, highlighting the Stellaris LM3Sz Bz 2 microcontroller1s simultaneous integrated 10/100 Ethernet MAC/PHY ,
fullspeed USB OTG interfaces, and the MCU1s GPIO ports.
L M3S9B90 K
L M3S9B90 K
L M3S9B90 K
L M3S9B90 K
L M3S9B90 K
L M3S9B92 K
L M3S9B92 K
L M3S9B92 K
L M3S9B92 K
L M3S9B92 K

it with Code Composer Tools: 296-25 7 85 -ND
it with I AR Tools: 7 26-1197 -ND

it with Code Composer Tools: 296-25 7 86-ND
it with I AR Tools: 7 26-1201-ND
C ORTEX - M 3
Toshiba Tools
Toshiba Dev elopment K its

MCBTMPM330 (Toshiba TX03) Ev aluation Board
The K eil MCBTMPM330 Evaluation Board introduces
you to the Toshiba TMPM330 family of ARM
Cortex-M3 processor-based devices and allows
you to create and test working programs for this
advanced architecture.
With an analog input (via potentiometer), three
switches, three LEDs, and access to all xz GPIO
Pins, this board is a great starting point for your
next Cortex-M3 project.

MCBTMPM330

103
C ORTEX - A8
Freescale Tools
iuMX Dev elopment K its

iuMX5 1 Cortex -A8 Dev K its
iuMX5 1 SBC
The Single-Board Computer
SBC-i.MX v1 from
Bluetechnix is based on
Freescale s high-performance
i.MX v1 mobile platform,
incorporating an ARM
Cortex-A8 CPU, an Image
Processing Unit (IPUv3EX )
and a V ideo Processing Unit
(V PU). The IPUv3EX provides
comprehensive support for
the connectivity to displays
and cameras.
Freescale delivers the cost-effective i.MX v1 evaluation kit,

allowing customers to develop, debug and demonstrate their
next great product without compromising performance. The
i.MX v1 EV K , based on a powerful ARM Cortex-A8 core, has two
optional add-on modules; an LCD and an expansion board. The
i.MX v1 EV K delivers extreme performance and provides long
battery life helping developers design products that meet
today s demands for energy efficiency.
MCI MX5 1EV K J-ND
iuMX5 15 Stack ableU SB

Computer (L inux -ready )
The SBC1wv1 is ideal for highperformance, low-power embedded
applications. A high degree of
integration allows a variety of I/O
functions to be included on the
SBC1wv1. All these features make it
ideal for handheld, mobile devices or
remote applications requiring rich
connectivity and low-power.

100-4110-ND
iuMX5 15 Stack ableU SB

(W inCE-ready )
Computer
The SBC1wv1 is ideal for highperformance, low-power embedded

applications. A high degree of
integration allows a variety of I/O
functions to be included on the
SBC1wv1. All these features make
the SBC1wv1 ideal for handheld,
mobile devices or remote applications requiring rich connectivity and low-power.
DK 165 1-ET-W I NCE-ND

DK 165 1-ET-L I NU X-ND
C ORTEX - A8
AM35 x x w37 x x Dev elopment K its

Sitara AM35 17 EV M
TI AM35 17 eXperimenter K it
Logic s product-ready software and hardware platforms fast

forward your product development while reducing risk and
controlling costs. The Z oom AM3v1x EV M Development K it is
a high-performance application development kit for evaluating
the functionality of Texas Instrument Sitara AM3v1x
microprocessor and Logic System on Module (SOM).
Fast forward your product development while reducing risk and

controlling costs. The Z oom AM3v1x eX perimenter K it is a low
cost application development kit for evaluating the functionality
of Texas Instruments1AM3v1x applications processor and Logic
PD1s System on Module (SOM).

296-25 25 1-ND

460-3486-ND
TI AM37 x Ev aluation Module

Developed with Mistral, the AM3xx Evaluation Module (EV M)
enables developers to immediately start evaluating AM3xx
processors (AM3x1v, AM3x03).
Engineers can also immediately begin building solutions such
as portable data terminals, portable medical equipment, home
and building automation, navigation systems, smart displays
and human machine interaction (HMI) industrial interfaces
amongst many others.

TMDXEV M37 15 -ND
10v
C ORTEX - A8
OMAP35 x x Dev elopment K its

OMAP35 x Torpedo Dev elopment K it
By providing a product-ready software and hardware platform,

Logic PDs embedded product solutions fast forward
development and helps your company stay focused on its
high-value core technologies. The Z oom OMAP3vx Torpedo
Development K it is a low-cost, high-performance application
development kit for evaluating the functionality of the OMAP3vx
Torpedo System on Module (SOM).
460-1033-ND
TI Z oom
OMAP35 x Dev K it
By providing a product-ready
software and hardware platform,
Logic PDs embedded product
solutions fast forward development
and helps your company stay focused
on its high-value core technologies.
The Z oom OMAP3vx Development K it
is a low-cost, high-performance application development kit for
evaluating the functionality of Texas Instruments OMAP 3
processors and System on Module (SOM).
296-24600-ND
BeagleBoard-x M
Beagle Board
The USB-powered Beagle
Board is a low-cost,
fanless single board
computer utilizing Texas
Instruments OMAP3v30
application processor that
unleashes laptop-like
performance and
expansion without the
bulk, expense, or noise of
typical desktop machines.

296-23428-ND
BeagleBoard-xM delivers extra MIPS with 1-GHz ARM

Cortex -A8 performance and extra memory with v12MB of
low-power DDR RAM, enabling hobbyists, innovators and
engineers to go beyond their current imagination and be
inspired by the BeagleBoard.org community.
296-25 7 98-ND
C ORTEX - R4
TMS5 7 0 Dev elopment K its

TMS5 7 0 U SB Dev elopment K it
TMS5 7 0 Dev elopment K it
The TMDX vx0LS20SUSB is a USB K it which can be used to

quickly evaluate code development and performance of the
TMSvx0 MCU. It includes the IECw1v08 SIL3 certified
TMSvx0LS2021w which has dual Cortex-R4F ARM CPUs
running in lockstep, 2 MB of on-chip Flash, 1w0 K B of RAM,
and an enhanced set of peripheral modules.
The TMDX vx0LS20SMDK is a complete Microcontroller

Development K it (MDK ) designed to quickly begin application
level code development on the TMSvx0 MCU. It includes the
IECw1v08 SIL3 certified TMSvx0LS2021w which has dual
Cortex-R4F ARM CPU s running in lockstep, 2 MB of on-chip
Flash, 1w0 K B of RAM, and enhanced set of peripheral
modules.

296-27 5 31-ND

TMDX5 7 0L S20SMDK -ND

10x
I D Es
Tools for Cortex-based Devices

Embedded W ork bench Baseline
IAR Embedded Workbench with its
optimizing C/C. . compiler is an
integrated development
environment for building and
debugging ARM-based embedded
applications.
It provides extensive support for
a wide range of ARM devices,
hardware debug systems and
RTOSs and generates very
compact and efficient code.
Ready-made device configuration
files, flash loaders and over 1400 example projects are included.
K eil RealV iew

MDK Basic
The RealV iew Microcontroller
Development K it for the ARM
microcontroller family supports
over 100 ARM derivatives. This
kit is perfect for the developer
who requires industry-standard
compilation tools and sophisticated debugging support. The
Basic version limits code size to
2vwK B and does not include RTX Real-Time K ernel.

MDK -ARM-BASI C-ND
EW ARMBL -ND
K eil RealV iew

MDK
Embedded W ork bench
IAR Embedded Workbench with its optimizing C/C. . compiler
is an integrated development environment for building and
debugging ARM-based embedded applications.
It provides extensive support for a wide range of ARM devices,
hardware debug systems and RTOSs and generates very
compact and efficient code. Ready-made device configuration
files, flash loaders and over 1400 example projects are included.

EW ARM-ND
The RealV iew Microcontroller

Development K it for the ARM
microcontroller family supports
over 100 ARM derivatives. In
addition to the C/C. . compiler
and debugger it includes RTX
Real-Time K ernel This kit is
perfect for the developer who
requires industry-standard
compilation tools and sophisticated debugging support.

MDK -ARM-ND
I D Es

TI Code Composer Studio v 4u0 Microcontroller Edition
Code Composer Studio
is based on the Eclipse
open source software
framework. It includes a
suite of tools used to develop and debug embedded applications. It
includes compilers for
MSP430, Stellaris,
Cortex-M3, C28x and
Cortex-R4F devices, source code editor, project build environment, debugger, profiler, simulators and many other features.

TMDSCCS-MCU F 01-ND
Code Composer Studio v 4u0 Platinum

Code Composer Studio
Platinum includes a suite
of tools used to develop
and debug embedded
applications. It includes
compilers for each of
TI s device families,
source code editor, project
build environment,
debugger, profiler,
simulators and many other features. The Code Composer Studio
IDE provides a single user interface taking you through each
step of the application development flow. Familiar tools and
interfaces allow users to get started faster than ever before and
add functionality to their application thanks to sophisticated
productivity tools.
TMDSCCS-AL L F 01-ND

10z
JTAG PROBES
JTAG Probes
K eil U L I NK pro Debug and Trace U nit
SEGGER J-L ink

J-Link is a USB 2.0 powered
JTAG emulator that can
communicate up to 12 MHz
with the supported target CPUs
with download speeds up to
x20 K bytes/sec. It supports
SWD and SWV and all JTAG
signals can be monitored.
ULIN K Pro, together with MDK -ARM, provides extended

on-the-fly debug capabilities for Cortex-Mx devices. Y ou are
able to control the processor, set breakpoints, and read/write
memory contents, all while the processor is running at full
speed. High-Speed data and instruction trace are streamed
directly to your PC.
U L I NK PRO-ND

899-1004-ND
SEGGER J-L ink Pro
K eil U L I NK 2 U SB-JTAG Adapter
The K eil ULIN K 2 USB-JTAG Adapter connects your PC s USB

port to your ARM Cortex-M processor-based target hardware
(via JTAG, SWD or OCDS) allowing you to program the on-chip
and external FLASH memory and debug embedded programs
on the target hardware.

U L I NK 2-ND
J-Link Pro is a refined version

of the regular J-Link. It has an
Ethernet interface in addition to
the USB interface, as well as
two additional LEDs that are used as
hardware status indicators.
It connects via Ethernet or USB to the
Windows PC host. Download and debugging
speed is higher with Ethernet provides electrical isolation from
the PC.

899-1007 -ND
JTAG PROBES
JTAG Probes
SEGGER J-Trace
Signum JTAGjet
J-Trace is a USB powered JTAG

emulator based on a 32-bit RISC
CPU, it can communicate at high
speed with the supported target
CPUs It has all the J-Link
functionality, supports tracing
on Cortex-M targets which include
trace (ETM) support, and has a
4 MB trace buffer.
JTAGjet-Cortex-CM3 is a
palm-sized, real-time, transparent
incircuit debugger that comes with
Chameleon Debugger and
supports all Cortex-M devices.
It has a USB 2.0 port (480Mbps),
optional ETM trace, unlimited S/W
breakpoints and on-chip H/W
breakpoint support.

JTAGJET-CORTEXM3-ND

899-1006-ND
Signum JTAGjet-OMAP3
JTAGjet-OMAP3 is a real-time,
transparent in-circuit debugger
based on the JTAG boundary
scan port. It features High-Speed
USB 2.0 port (480Mbps)
connection to offer maximum
communication speeds and
convenience. JTAGjet-OMAP3
comes with the powerful
Chameleon Debugger for
ARM software.
Signum JTAGjet-Trace with Trace

Buffer (1MB, 2MB or 4MB)
JTAGjet-Trace is a real-time, transparent
in-circuit debugger with either 1MB,
2MB or 4MB frame deep ETM trace
memory. It supports all Cortex
devices equipped with the
Embedded Trace Macrocell
(ETM) port.

1MB Trace JTAGJET-TRACE-1M: JTAGJET-TRACE-1M-ND

JTAGJET-OMAP3-ND
111
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FALL 2010/SPRIN G 2011 ARM

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Digi-K ey and the ARM Cortex

in-stock and available for purchase at

The media attention on the past

www.digikey.com/cortex Fall 2010/Spring 2011

With this unequaled level of support,