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CSO Cheat Sheet

by mathildapurr via cheatography.com/33013/cs/10300/


Byte ordering of 0x01234567

2's complement

Normalized encoding example

Converting 2's C to decimal


Byte representation of ints

Denormalized encoding

Bit operations (integral data type)

Floating Point Rep

Logical operators
Specialized encoding

Encoding

Unsigned integers

Precision

2's complement

movq operand combo

Address computation
Normalized encoding

By mathildapurr

Published 22nd December, 2016.

Sponsored by ApolloPad.com

cheatography.com/mathildapurr/

Last updated 22nd December, 2016.

Everyone has a novel in them. Finish Yours!

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CSO Cheat Sheet

by mathildapurr via cheatography.com/33013/cs/10300/


Multiplication

one operand instructions

Explicitly setting condition codes


cmpl b, a

a-b result not stored anywhere

testq b, a

a&b result not stored anywhere

When are local variables in stack?


useful instruction for division

Enough registers
No reference to & so no need to go to memory
No arrays, structures

Division

When P(caller) calls Q


Setting condition codes

SetX dest: only set lower 1 byte of register

Implicitly setting condition code: addq src,


dest

Structure representation

Jumping

Bad cases for conditional move

Procedure data flow

2 operand instructions

Effect of operations
Logical

CF=0, OF=0

Operations
shift

CF=value of last bit shifted


out; OF=0

INC, DEC

OF and ZF may change, CF


unchanged

By mathildapurr

Published 22nd December, 2016.

Sponsored by ApolloPad.com

cheatography.com/mathildapurr/

Last updated 22nd December, 2016.

Everyone has a novel in them. Finish Yours!

Page 2 of 4.

https://apollopad.com

CSO Cheat Sheet

by mathildapurr via cheatography.com/33013/cs/10300/


Register usage

Cache structure

Source code to execution

Cache calculation

Register usage contd

Cache miss

Resolving symbols

3 cases

compulsory, capacity, conflict

How to

block size++, associativity++,

reduce

cache size++

miss
Reducing

write through (update all) vs write

miss

back (update when needed)

penalty
multilevel cache (optimize hit

Popq dest (for stack)


Replaceme

Why VM

rate L1, miss rate L2)

memory

permission bits; uses main

LRU, LFU, FIFO, rand

management

efficiently(send unneeded to

and protection

disk)

Process

own add spaces; can't

isolation/memor

interfere with another's

y protection

memory

nt policies
Cache access time

loading linking simplified

Why Linkers

Array access

VP partitioned to 3 subsets
Unallocated

not yet created, no data, no


space

Uncached/cach

currently cached/not cached

ed
Address translation w page table

By mathildapurr

Published 22nd December, 2016.

Sponsored by ApolloPad.com

cheatography.com/mathildapurr/

Last updated 22nd December, 2016.

Everyone has a novel in them. Finish Yours!

Page 3 of 4.

https://apollopad.com

CSO Cheat Sheet

by mathildapurr via cheatography.com/33013/cs/10300/


Page hit

mem alloc challenges


memory utilization (sum of malloc'd data/heap
size)
good performance (malloc/free calls return
quick)
constraints: can't modify malloc'd memory;
can't move malloc'd block

page fault
implicit free list with footer and header

Speed: TLB hit, mem access-1

explicit free list (pointer don't space+)

TLB miss (rare with high assoc): 3 mem


accesses

Seg list

size-- multilevel page table

classes of exceptions

exception examples
cache and VM
cache uses PA, since with VA, although can be
accessed asap, aliasing, 2 VA may map to
same block, would not know which one
By mathildapurr

Published 22nd December, 2016.

Sponsored by ApolloPad.com

cheatography.com/mathildapurr/

Last updated 22nd December, 2016.

Everyone has a novel in them. Finish Yours!

Page 4 of 4.

https://apollopad.com