Shift Registers using Verilog HDL

with Quartus Prime

L.M.P.Villalba, C.B.Maghamil, A.J.W. Lomoya
Fourth Year, Bachelor of Science in Electrical Engineering

I. INTRODUCTION
II. OBJECTIVES
A register is a group of binary storage cells
capable of holding binary information. A group of
flip-flops constitutes a register, since each flip-flop
can work as binary cell. An n-bit register, has n flipflops and is capable of holding n-bits of information.
In addition to flip-flops a register can have a
combinational part that performs data-processing
tasks.
Various types of registers are available in MSI
circuits. The simplest possible register is one that
contains no external gates, and is constructed of only
flip flops. All flip-flops in a register has a common
clock pulse that enables all flip-flops at the same
instant so that the information available can be
transferred. The clock pulse transition is either edgetriggered type or the master-slave type. A group of
flip-flops sensitive to the pulse duration is
commonly called a gated latch. Latches are suitable
to temporarily store binary information that is to be
transferred to an external destination. They should
not be used in the design of sequential circuits that
have feedback connections.
A register capable of shifting its binary contents
either to the left or to the right is called a shift
register. The shift register permits the stored data to
move from a particular location to some other
location within the register. Registers can be
designed using discrete flip-flops such as S-R, J-K,
and D-type.
The data in a shift register can be shifted in two
possible ways, serial shifting or parallel shifting.
The serial shifting method shifts one bit at a time for
each clock pulse in a serial manner, beginning with
either LSB or MSB. On the other hand, in parallel
shifting operation, all the data, input or output, gets
shifted simultaneously during a single clock pulse.
Hence, we may say that parallel shifting operation is
much faster than serial shifting operation.
There are two ways to shift data into the register
and similarly, there are two ways to shift data out of
the register thus leading to four basic types of
registers. Serial in/Serial out, Serial in/Parallel out,
Parallel in/Serial out, Parallel in/Parallel out, this are
the four basic types of registers.[1]
In this experiment, we are going to use the
Serial in/Parallel out, shift right, shift register to be
coded in Verilog and synthesized and upload in the
DE-1 SoC board.

The objectives of this experiment are, first, to

be able to use the shift register megafunction,
second, to import and use previous codes to drive
hex display, third, to code and upload shift register
into the DE-1 SoC board.

III. CODE

Figure 1. Code Heirarchy.

Figure 2. Shift register top level code.

Figure 3. Shift register megafunction

Verilog code.

Figure 4. HEX display module.

IV. DATA AND RESULTS

Based on the codes above, we have compiled
and synthesized the following RTL below that
represents our logic circuit within the FPGA. It
consists of the individual modules that are in the top
level module. Each of the module is represented by
a box, while the I/O are represented by bullet sign.
We will also notice that the data bus q is connected
towards two hex displays where their bits is divided
into four each, [3:0] for hex 1 and [7:4] for hex 2.
The LEDR is assigned equivalent to the value of
each bit in the 8 bit register in order to keep track of
the data shifting. The hex module takes care of the
BCD to 7 segment display.

Figure 5. Register-Transfer Level of the shift

register code.
With the code compiled and uploaded, the
following figures are the result where in every high
state of the clock the data is shifted to the right as
displayed in the leds and the BCD as shown in the 7
segment display.

Figure 6. Shifting data from 01111111 to

00000000.

V. ANALYSIS AND CONCLUSION

A 8 bit serial in parallel out shift register is
divided into two parts. The first 4 bits from the first
input is directed towards the first hex display while
the other 4 bits is towards the second hex display.
We can see from figure 5 that we have a pushbutton
to simulate a clock pulse and a slide switch as an
input data. The data is fed towards the shift register

module as the first box and the output data bus q is

then used as an input to hex 1 and hex 2. In
accordance to this, LED is assigned the values of
each data bit in the shift register in order for the LED
to illuminate everytime the shift register shifts its
data to the right since each output is paralleled out.
As the push button is pressed, the state of the
slide switch is being used as an input data towards
the shift register. With either 0 or 1 in the slide
switch, as long as the clock pulse is in high state, the
data from the first bit is transferred in serial manner
to the right as we will see in the LED lights. The 4
bit data is displayed in the hex using binary coded
decimal equivalents.
Based on figure 6, our initial data in the shift
register is 01111111, where the 7 segment display
shows 7 and 0, 0 for hex 2 since we have default it
to 0 when it does not coincide within 0000 and 1001.
Inputting 0 everytime the clock pulse goes up, we
will see it change to 0011 1111, 0001 1111, 0000
1111, 0000 0111, 0000 0011, 0000 0001, and
00000000. Where the pair hexes displays (7,0),
(3,0), (1, 0), (0,0), (0,7), (0,3), (0,1), and (0,0).
In sum, using megafunctions makes coding
easier and neater. It also, provides simpler modeling
of the logic circuits where only the specifications
and the pins are required. Also, using modules and
importing it makes coding more organized. Lastly,
registers stores data and has a common clock that
shifts the data depending on the circuit as stated in
the four basic types above.

VI. REFERENCE
[1] Manna, N., & Saha, A. Digital Principles and
Logic Design. Infinity Science Press, MA,
2007.