Kuwait University

Computer Engineering Department

Computer Architecture Lab
Lab 3: Implementing the Single Cycle Version of the MIPS Processor

1. LEARNING OBJECTIVES

Understanding the single cycle architecture advantages and disadvantages.

Knowing how to use Quartus Software to evaluate the implementation performance and cost.

2. THE SINGLE CYCLE ARCHITECTURE

As mentioned in the previous labs, the MIPS processor can be implemented in three
different ways, as any processor can be. The single cycle version, the multi cycles version, and the
pipelined version. We will discuss shortly the three different versions in the following subsections.

2.1. The single cycle MIPS architecture

The simplest version is the single cycle MIPS processor. In this implementation, the
processor executes each instruction in one clock cycle. Although that sounds so fast, but since the
clock period depends only in the longest path in the circuit, the clock period for such design is too
long so it fits all possible paths an instruction can take. Such an architecture can be used for a small
instructions set computers. With small number of instructions, the difference between all possible
paths will be small. Another disadvantages of this implementation is the duplicated components.

2.2. The pipelined MIPS architecture

As for the multi cycles implementation , in a pipelined processor, the data path is partitioned
into set of stages. However, it is not only one instruction that is executing in every clock cycle. To
utilize the whole processor, in every stage there is an instruction that may perform some
computation. If an instruction leave a stage, the next instruction will enter it. This implementation
has the following advantages: First, it utilizes most of the processor in every clock cycle. Second, it
increase the throughput by finishing more instruction with a given time. Also, its controller is as
simple as the single cycle implementation. The disadvantages of this implementation are: it
increases the latency an instruction takes by adding registers and obliging every instruction to enter
every stage even if it does not need it. We will discuss the pipelined version of our MIPS processor
in the next two labs in more details.

Figure 1. Single Cycle MIPS Processor.

LAB EXERCISE #3:

BUILDING THE SINGLE CYCLE MIPS PROCESSOR
Name:
ID:

Section:

1. PROBLEM STATEMENT
Design and implement the MIPS single cycle processor shown in Figure 1.

2. DESIGN STEPS
1. Open the project created in the previous labs.
2. Create symbols for the ALU, the Register file, and the control unit.
3. The MIPS processor shown in Figure 2 does not include the logic of the JAL and the
RET instructions. Modify the figure so it includes the logic of these instructions.
4. Create a BDF file, call it SingleProcessorMIPS.
5. Using the mega wizard, create the following:
a. 3-bits 2-to-1 multiplexer.
b. 16-bits 2-to-1 multiplexer.
c. 16-bits 4-to-1 multiplexer.
d. Two 64Kx16 memories. Call the first one InstructionsMemory and the second
DataMemory.
e. 16-bits comparator.
f. 16-bits Flip-Flop.
g. 16-bits adders. One with constant input with value 1.
6. After generating the components, use them with the components created in the previous
labs to build the processor shown in the figure after the modifications.
7. Load the Instruction memory and the Data Memory with the MIF files that the instructor
gave it to you.
8. For verification purposes, take all the registers, the PC, the instruction as an output from
the whole design.
9. Run the Analysis and Synthesis for the whole design.
10. Create a vector waveform file and insert all the inputs and outputs of your design.

11. Generate functional simulation netlist and simulate the design. The simulation result
should be similar to what is shown in Figures 3 & 4.