Processor Organization and performance

One of the charateristics that influence ISA is the number of addresses & Adress
ing modes
NB: the number of instructions needed to execute increases as we reduce the
number of addresses, the lower the number of memory accesses, the better
Load/Store achitecture are use to move data between registers and memory (RISC)
Horizontal Microcode does not impose any restrictions on the concurrent use of t
he
recourses in the datapath. (higher performance but hardware costly). But the ver
tical microcode opposite.
--------------------------------------------------------------------------------Things to do:
execution time calculation
Seven-segmention
Information presentation
Coding practice
Literature Reviews
----------------------------------------How we measure performance?
Through:
Specification: processor type, speed, memory and size
Disadvantage of this is that it can be manipulated, requires knowlwdge of how co
mponenets affect the way programs work.
Does not give the complete picture
MIPS and MFLOPS: How
Disadvantage of this
on, I/O operation is
all instructions are

fast the computer can run. It is easy to quote!

is that it does not tell the type of instruction or conditi
not considered,
not equal. Takes long to load memory instruction

Benchmarks: Standard programs used to simulate the load that will be generated d
uring use of
computer for particular application. It is the best! Use test programs for diffe
rent computer systems and application
Advantge is that test program is mixture of different instruction, it also unifo
rm!
Disadvantage is that it is a simulation, not actual test!
Thus, there may be difference between the benchmark and the actual application
Live Test: Run the test in actual environment. It gives the best picture.
Disadvantage is that it requires complete set up!
Spec virt sc 2013 can be use to measure the performance of:
Webservers, mailservers, batch servers, application servers
-------------------------------------------------------------------------------------------------------------------------------------Process Architecture
RISC, CISC, Vector, and VWIS
Memory Architecture:
harvard (sperate instruction and data memory) and Non Neumann Architecture (they
are together/common)
ISA is an abstract view of the computer's hardware from programmers point of vie
w
Types of instruction:

ALU, Flow Control, Procedure, Multiple Data Float, SIMD, Logical instruction
Address Type describes the number of data sources and destination an instruction
refers to.
Number of Addresses in Instruction are:
three memory: Three address for three data items (common with RISC)
two memory: Two addresses, one for source and one for destination
one memory (accumulator/ fixed register): Instruction has one address for source
and destination
zero memory: instruction contains no memory, data is fetched from Stack
Instruction Format:
Fixed length or variable length
Two ways of generating control signals:
Hardware FSM (for each instruction, one FSM needs to be design) or Software
Five Processor State:
Fetch, Decode, Operand, Execute, and Write
Operand Type:
Size, Integer, Float, character, sign, and unsigned.
Parallel Processing:
a mode of operation in which a process is split into parts, which are executed s
imultaneously on
different processors attached to the same computer.
Examples of parallel processing architectures:
SISD, SIMD, MIMD, MISD
---------------------------------------------------------------------------------------------------------------------------------Pipelining!
Purpose of pipelining is to keep components of the processor busy!
components of a processor
instruction fetch, decode, operand, execute, write
What makes Pipeling easy?
All instructions the smae length.
Just few instruction set.
memory operands appear only in loads and store
What makes it difficult:
Structural Hazard: only one memory, or adder (needing the same resource at the s
ame time)
Solution: more resources and buffering!
Data Hazard: Uses data from previous instruction (update issue)
Solution: register interlocking! or direct forwarding!
Control Hazard: Need to aorry about branching conditions (subsequent instruction
in pipeline not executed)
Solution: flush the pipeline, or insert a useful instruction at the delay slot a
nd use the time!
-------------------------------------------------------------------------------------------------------------------------------------------

main challenges of x86 virtualization are efficient OS isolation and virtualizat

ion overhead

problems of virtualization include execution speed, security, memory management,

multiplexing, and isolation of devices such as network cards.
Popek and Goldberg principles of virtualization [1, 2] define a set of specifica
tions for efficient processor virtualization. The standard suggests the ideal mo
dels and expectations of privileged instructions. Ideal instructions should beha
ve in expected ways no matter what the current operating privilege level is and
should trap any problems.