CHAPTER 1.

INTRODUCTION
1.1 Introduction
Multilevel inverter is based on the fact that sine wave can be approximated to a stepped
waveform having large number of steps. The unique structure of multilevel inverter allows them
to reach high voltages and therefore lower voltage rating device can be used. Multilevel inverter
includes an array of power semiconductor devices and capacitors voltage sources, the output of
which generates voltages with stepped waveforms. A multilevel converter can switch either its
input or output nodes (or both) between multiple (more than two) levels of voltage or current.
The output voltage of the multilevel inverter has many levels synthesized from several DC
voltage sources. The quality of the output voltage is improved as the number of voltage levels
increases, so the quantity of output filters can be decreased. A multilevel converter can be
implemented in many different ways. The simplest techniques involve the parallel or series
connection of conventional converters to form the multilevel waveforms. More complex
structures effectively insert converters within converters. The voltage or current rating of the
multilevel converter becomes a multiple of the individual switches, and so the power rating of
the converter can exceed the limit imposed by the individual switching devices. The elementary
concept of a multilevel converter to achieve higher power is to use a series of power
semiconductor switches with several lower voltage DC sources to perform the power conversion
by synthesizing a staircase voltage waveform.
Power electronic converters, especially DC/AC PWM inverters have been extending their range
of use in industry because they provide reduced energy consumption, better system efficiency,
improved quality of product and easy maintenance. For a medium voltage grid, it is troublesome
to connect only one power semiconductor switches directly. As a result, a multilevel power
converter structure has been introduced as an alternative in high power and medium voltage
applications. As a cost effective solution, multilevel converter not only achieves high power
ratings, but also enables the use of low power application in renewable energy sources such as
photovoltaic, wind, and fuel cells which can be easily interfaced to a MLI system for a high
power application. The most common initial applications of multilevel converters has been in
traction, both in locomotives and track-side static converters. More recent applications have been
for power system converters for VAR compensation and stability enhancement, active filtering,
1

high-voltage motor drive and most recently for medium voltage induction motor variable speed
drives [1].
The aim of this dissertation is to group and review recent contributions of MLI along with their
importance in high and medium voltage applications. This chapter first presents an introduction
of well-established multilevel inverters. Multilevel inverters have been attracting increasing
interest recently the main reasons are; increased power ratings, improved harmonic performance,
and reduced electromagnetic interference (EMI) emission that can be archived with multiple DC
levels that are synthesis of the output voltage waveform. The inverters in high voltage
application areas as stated above should be able to handle high voltage and large power. For this
reason, two-level high-voltage and large-power inverters have been designed with series
connection of switching power devices such as gate turn-off thyristor (GTOs), insulated gate
commutated transistors (IGCTs), and insulated gate bipolar transistors (IGBTs), because the
series connection allows reaching much higher voltages. However, the series connection of
switching power devices has big problems, namely, non-equal distribution of applied device
voltage across series-connected devices that may make the applied voltage of individual devices
much higher than blocking voltage of the devices during transient and steady-state switching
operation of devices. As alternatives to effectively solve the above-mentioned problems, several
circuit topologies of multilevel inverter and converter have been researched and utilized.
Capacitors, batteries, and renewable energy voltage sources can be used as the multiple DC
voltage sources. The commutation of the power switches aggregate these multiple DC sources in
order to achieve high voltage at the output; however, the rated voltage of the power
semiconductor switches depends only upon the rating of the DC voltage sources to which they
are connected.
A multilevel converter has several advantages over a conventional two-level converter that uses
high switching frequency pulse width modulation (PWM). The attractive features of a multilevel
converter can be briefly summarized as follows.
1. Staircase waveform quality: Multilevel converters not only can generate the output
voltages with very low distortion, but also can reduce the
electromagnetic compatibility (EMC) problems can be reduced.
2

dv
dt

stresses; therefore

2. Common-mode (CM) voltage: Multilevel converters produce smaller CM voltage;

therefore, the stress in the bearings of a motor connected to a multilevel motor drive can
be reduced. Furthermore, CM voltage can be eliminated by using advanced modulation
strategies such as that proposed in.
3. Input current: Multilevel converters can draw input current with low distortion.
4. Switching frequency: Multilevel converters can operate at both fundamental switching
frequency and high switching frequency PWM. It should be noted that lower switching
frequency usually means lower switching loss and higher efficiency.
1.2 Necessity
The current energy arena is continuously changing. The feeling of dependence on fossil fuels and
the progressive increase of its cost is leading to the investment of huge amounts of resources,
economical and human, to develop new cheaper and cleaner energy resources not related to fossil
fuels. In fact, for decades, renewable energy resources have been the focus for researchers, and
different families of power inverters have been designed to make the integration of these types of
systems into the distribution grid a current reality. Besides, in the transmission lines, high-power
electronic systems are needed to assure the power distribution and the energy quality. Therefore,
power electronic inverters have the responsibility to carry out these tasks with high efficiency.
The increase of the world energy demand has entailed the appearance of new power converter
topologies and new semiconductor technology capable to drive all needed power. A continuous
race to develop higher-voltage and higher-current power semiconductors to drive high-power
systems still goes on. However, at present there is tough competition between the use of classic
power converter topologies using high-voltage semiconductors and new converter topologies
using medium-voltage devices.
The power electronics research community and industry have reacted to this demand in two
different ways: developing semiconductor technology to reach higher nominal voltages and
currents (currently 8 kV and 6 kA) while maintaining traditional converter topologies (mainly
two-level voltage and current source inverters); and by developing new converter topologies,
with traditional semiconductor technology, known as multilevel inverters. The first approach
inherited the benefit of well-known circuit structures and control methods. Adding to that, the
newer semi-conductors are more expensive, and by going higher in power, other power-quality
requirements have to be fulfilled, thereby there may be need of additional power filters.
3

Therefore it will be quite feasible to choose to build a new converter topology based on
multilevel concept. This is the challenging issue right now.
Multilevel inverters are composed of series of power electronics switches which can generate the
output voltage with stepped waveform. Out of various topologies available diode clamped and
cascaded MLI are most common structures used for the industrial applications. Both the diode
clamped as well as cascaded MLI need to be simulated in MATLAB/Simulink to study their
performance in medium and high voltage application, also the performance of MLI depends on
the switching technique employed. So fast computational controller like dSPACE 1104 is used
which can generate the switching pulses in real time from the simulation in MATLAB/Simulink.
1.3 Objectives
In this Dissertation work, various MLI structure, their operating principles, various switching
techniques and their real time implementation are studied. Following are the objectives identified for
this dissertation work.

1. To study various multilevel power inverter configurations.

2. To study and simulate cascaded type of five level multilevel inverter configuration in
MATLAB/Simulink.
3. To study and simulate diode clamped type of five level multilevel inverter configuration
in MATLAB/Simulink.
4. Comparison between cascaded and diode clamped multilevel inverter.
5. To study different switching techniques, simulate APOD and POD techniques in
MATLAB/Simulink.
6. To study generalized functional simulation for five level inverter using switching
function concept.
7. To study the effect of change in total harmonic distortion (T.H.D.) of output voltage with
respect to variation in the modulation index (M.I.)
8. To demonstrate the switching pulses generation using dSPACE 1104 controller.
1.4 Theme
In this dissertation work various multilevel inverter topologies are studied and compared for their
performance. The simulation of the diode clamped multilevel inverter and cascaded multilevel
inverter is carried out using MATLAB/Simulink. In addition to that various control techniques
4

required for the multilevel voltage source inverter are studied and presented briefly. The dSPACE
1104 controller is used for the real time implementation of switching pulses. All the results are
summarized to validate the advantages of multilevel inverter technique against the classical
inverter technique.
1.5 Organization
The dissertation is divided in five chapters. The basic principle of multilevel inverter technology
and its classification, control scheme and real time implementation are discussed in relevant
chapters.
Chapter 1 briefs about the introduction to multilevel inverter technology, its necessity in present
scenario, theme and objectives of the dissertation.
Chapter 2 gives an exhaustive literature survey about multilevel inverter technology, its
classification, control techniques and real time implementation using dSAPCE 1104.
Chapter 3 briefs about the cascaded and diode clamped multilevel inverter for three and five
level. The chapter gives a clear idea about the general structure of both the types of multilevel
inverter and their principle of operation. Further the modelling of five level cascaded and diode
clamped multilevel inverter is presented by using MATLAB/Simulink as a tool.
Chapter 4 presents Performance Analysis of cascaded and diode clamped multilevel inverter in
MATLAB/Simulink. The same simulation is integrated with dSPACE 1104 controller to generate
the switching pulses for the real time application.
Chapter 5 gives the conclusion and some recommendations for future works employing realtime implementation of cascaded and diode clamped MLI for medium voltage applications.

CHAPTER 2. LITERATURE SURVEY

2.1 Introduction
Exhaustive literature survey carried out on multilevel inverter technology, various topologies,
control scheme and area of application. The literature review is classified in two categories.
Firstly basic topologies for multilevel inverter are discussed in detail and then control schemes
used for the MLI structure and its real time implementation are presented. Major consultations
were technical papers from the last 10 years in the field of multilevel inverter technology and
applications.
2.2 Multilevel Inverter Topologies and their Applications
Multilevel inverter are popular over the years in medium and high power applications. There are
various topologies available which offers better performance compared to classical inverter.
Practically, multilevel inverters present great advantages compared with conventional and very
well-known two-level converter. These advantages are fundamentally focused on improvements
in the output signal quality (Voltage & Current) and a nominal power increase in the converter.
2.2.1

Classical Inverters (Two-Level Inverters)

There are different power converter topologies and control strategies used in inverter designs.
Different design approaches address various issues that may be more or less important depending
on the way that the converter is intended to be used. The issue of waveform quality is one the
important concern and it can be addressed in many ways. In practice capacitors and inductors can
be used to filter the waveform. If the design includes a transformer, filtering can be applied to the
primary or the secondary side of the transformer or to both sides. Low-pass filters are applied to
allow the fundamental component of the waveform to pass to the output while limiting the
passage of the harmonic components. Thus quality of waveform can be adjusted. Note that,
normal inverters always generate very low quality output waveforms. To make the output
waveform qualitative, low pass (LC filter) are often added in the circuit.
6

2.2.2

Summary of Power Inverters

Consider Table 2.1, which presents the important applications from low power to high power
range. From Table 2.1 it is quite predictable that, power inverter is a developed technology. They
are potentially useful for a wide range of applications like; low power devices, home appliances,
electric vehicles, photovoltaic, transport (train traction, ship propulsion, and automotive
applications), and energy conversion, manufacturing, mining, and petrochemical applications.
The inverters mentioned in Table 2.1 are available in a wide range. Note that, either it may be
suited for DC or AC. But, at present industries are in chase of finding new type of power
converter for medium to high power range, moreover it seems to be challenging issues for
present generation researchers.
TABLE 2.1
Summary of Power Inverters
Low Power

Power Range

Usual Converter

Topologies
Typical Power
Semiconductors

Up to 2kW
AC/DC, DC/DC
MOSFET

Topology Trend

AC/DC, DC/DC,
DC/AC
MOSFET, IGBT

More than 500 kW

AC/DC, DC/AC
MOSFET, IGBT,

Small Volume and

Weight, Low cost

the Converter, High

and High

Power Quality and

Efficiency

Stability

Home-appliances

Roof top PV

Renewable Energy

Low-Power

Electric vehicles

Density, High
Efficiency

2-500 kW

High Power

Thyristor
High Nominal Power of

High Power

Medium Power

Typical
Applications

Devices
7

Power Transmission

Although research pioneers have built a numerous power inverters, but still researchers are in
look for a new sort of architecture which can produce high quality waveform with less number of
components. In other terms improving power quality is the greatest requirement. By considering
above aspects, let us make an outline regarding the demanding aspects of power inverters,
particular in Medium and high power range. At present there is tough competition between the
use of classic power converter topologies using high-voltage semiconductors and new converter
topologies using medium-voltage devices. This idea is shown in Figure. 2.1, where inverters are
built by adding devices in series. [2]

Figure 2.1 Classical representation of Multilevel Inverter

In past, these inverters are only viable options for medium and high-power applications. But in
present scenario, multilevel technology with medium voltage semiconductors are fighting in a
development race with classic power inverters using high-power semiconductors, which are
under continuous development and are not mature. Although, classical inverters are good for low
power applications, but they fail to fill the requirements of high-power levels. [1,3] Multilevel
inverters are a good alternative for power applications due to the fact that, they can achieve high
power using mature medium power semiconductor technology.

2.2.3

Medium and High Voltage Applications

The properties of multilevel inverters are proven very attractive to the industry and, nowadays,
researchers all over the world are spending great efforts trying to improve multilevel converter
performances such as the control simplification and the performance of different optimization
algorithms in order to enhance the THD of the output signals, the balancing of the DC capacitor
voltage, and the ripple of the currents. For instance, nowadays researchers are focused on the
harmonic elimination using pre-calculated switching functions, harmonic mitigation to fulfill
specific grid codes, the development of new multilevel converter topologies (hybrid or new
ones), and new control strategies. However, before introducing about the multilevel inverters it is
necessary to address the problems of conventional inverters, one should have an idea about the
Medium to high-power range inverters and related challenging issues. Below are some of the
facts summarized.
1. At present, applications with power range of inverter circuits using the basic "inverter
1 kW

leg" building block is vast

2. Very large application area is in industrial (PWM controlled induction motor) drives
(See Table 2.1) are around 3 kW to 100 kW power range. IGBT devices are used almost
exclusively in this power range.
3. Recently the application area for these circuits has extended to power levels ( 1 MW )
, most importantly,
a) Railway locomotives (15 MW )
b) Ship propulsion (e . g . Frigate 20 MW )
c) Power systems applications, for example FACTS (Flexible AC Transmission
Systems)
4. Above all applications use devices like: IGBT (Insulated Gate Bipolar Transistor), GTO
(Gate Turn-off Thyristor), IGCT (Insulated Gate Commutated Thyristor). However,
design of these high power inverters (MW range) presents serious problems:
9

a) Single devices cant handle the required voltage and current.

b) Device voltage rating required 8-10 kV - not available.
c) Handling high currents by putting devices (or inverters) in parallel is fairly well
established. Getting the voltage handling capability remains the problem.
Thus to solve above mentioned problems some of the conventional solutions too available, and
solutions are;
1. Using standard converter topologies with devices in series.
2. Using alternative topology inverters which a number of low voltage devices and that
have some means for distributing the voltage stress amongst those devices (Multi-level
inverters).
Anyhow as demonstrated in Figure. 2.1. Observe the arrangement; it uses the semiconductor
devices in series. In other sense, by adding devices in series voltage capability is increasing.
Somehow with this arrangement inverters can meet high power demand. But one of the greatest
limitations is the output voltage quality. However with classical arrangement converter has the
potential to generate only two level output. In fact such kind of waveforms composes with huge
harmonic content. Particularly low order harmonics like 3rd, 5th, 7th, etc. This harmonics
drastically affects the equipment performance. Frequently, to suppress such harmonics several
low filters are used to improve the quality at the output end. But filter size is still greater in
extent if the quality is poor. Additionally, a well-known fact is that, designing Low Pass Filter is
a hectic job and it is bulky in nature too. Plenty of research is going on this subject i.e., to reduce
the filter size in the circuits. Overall from above prospects we can summarize some of the
problems of classical inverters as follows:
1. The entire DC voltage appears across each switch when it is off. This will be greater than
the voltage rating of the individual devices.
2. The devices will not automatically share the voltage in the off state because of
differences in leakage current - high value parallel resistors can be used to overcome this
(static sharing).
3. More seriously, the devices will not share the voltage during switching due to variations
in switching speed. Special gate drive techniques and/or special snubbers are required
(dynamic sharing). Not well established yet.

10

4. Two level output causes very large voltage steps on the load - can be a problem for motor
insulation.
5. Harmonic content (distortion) is larger for a given switching frequency than with multilevel techniques
On the flip side, classical inverters too have finite advantages those are:
1. Standard PWM techniques can be used.
2. Number of power circuit components is less as compared to other (multi-level) circuits.
3. Redundancy can be incorporated (to improve reliability) by using more series devices
than actually required, the circuit can then still work if one fails.
However with this demonstration it is clear that conventional inverters have huge drawbacks
than merits. So alternative solution to meet the high power demand is through multilevel
concept.
2.2.4

Multilevel Inverter Manufacturing Companies

TABLE 2.2
Manufacturing Companies of Classical and Multilevel Inverters

Converter
Configuration
Two-Level Inverter
(VSI)

Solid State Device

Power Range

IGBT

1.4 MVA-7.2 MVA

Manufacturer
Alstom
(VDM 5000)

0.3 MVA
GCT

5 MVA

ABB (ACS 1000)

3 MVA

(ACS 6000)

27 MVA
General Electric
NPC Inverter

GCT

3 MVA-20 MVA

(NPC VSI)

Cascaded H-Bridge

IGBT/IGCT

0.6 MVA-0.9 MVA

IGBT

0.4 MVA-4.5 MVA

GTO

2.5 MVA- 18 MVA

IGBT

0.3 MVA-22MVA
11

(Innovation Series
MV-SP)
Siemens
(SIMVERT-MV)
GE-Toshiba
(Dura-Bilt5 MV)
Toshiba
(Tosvert S650 )
Robicon

IGBT

0.5 MVA- 6 MVA

Inverter (VSI)

NPC H-Bridge
Flying Capacitor

(Perfect harmony)
Toshiba
(TOSVERT-MV)
General Electric

IGBT

Innovation MV-GP

IGBT

Type-H)
GE-Toshiba

6-26 MVA

IGBT
0.3-8 MVA
Alstom
Inverter
The inverters are commercialized by several manufacturers in the field, offering different power
ratings, front-end configurations, cooling systems, semiconductor devices, and control schemes,
among other technical specifications. There are a number of high-power drive manufacturers
around the world, including ABB (Switzerland), Siemens (Germany), Toshiba (Japan), Rockwell
Automation (Canada), General Electric (US), AS1 Robicon (US) and Alstom (France). These
companies use various power converter technologies, For instance, ABB produces three-level
neutral point clamped inverter fed drives, Rockwell manufactures GCT current source inverter
based drives, Robicon promotes cascaded H-bridge multilevel inverter technology, Toshiba uses
multilevel NPC/H-bridge hybrid inverters, and Alstom is developing flying-capacitor based
multilevel inverter. Further, the most relevant parameters and ratings for each of these classic
multilevel topologies that are published in recent past are listed in Table 2.2. The parameters for
each category are given for the different manufacturers. As can be observed from the Table 2.2,
the 3L-NPC-MLI and the CHB-MLI are the most popular multilevel topologies used in the
industry. It is not straightforward or fair to compare the commercially available 3L-NPC-MLI
with the 7L to 17L-CHB-MLI listed in Table 2.2 since the first will have worse power quality
and the second will have a more complex circuit structure. However, some evident differences
between them can be concluded from Table 2.2
1. The NPC-MLI features medium/high-voltage devices integrated gate commutated
thyristor (IGCT) and medium voltage/high-voltage insulated-gate bipolar transistors
(IGBTs)], whereas the CHB exclusively uses low-voltage IGBTs (LV-IGBTs).
2. The CHB-MLI reaches higher voltage and higher power levels.
3. The NPC-MLI is definitely more suitable for back-to-back regenerative applications. The
CHB-MLI needs substantially higher number of devices to achieve a regenerative option
(a three-phase two-level voltage source inverter (VSI) per cell).
12

4. The CHB-MLI needs a phase-shifting transformer usually to conform a 36-pulse rectifier

system. This is more expensive but improves input power quality.
Generally speaking, the medium-voltage range is considered in the power converter industry
from 2.3 to 6.6 kV and these inverters can be easily expandable. While distinguishing the three
most significant topologies for specific applications in terms of the losses and the output voltage
quality, the 3L-NPC-MLI has become well recognized architecture because of a simple
transformer rectifier power circuit structure, with a lower device count when considering both
the inverter and rectifier, and less number of capacitors. Although the NPMLI structure can be
extended to higher number of levels, these are less attractive because of higher losses and uneven
distribution of losses in the outer and inner devices. In particular, the clamping diodes, which
have to be connected in series to block the higher voltages, introduce more conduction losses and
produce reverse recovery currents during commutation that influence the switching losses of the
other devices even more. Moreover, DC-link capacitor voltage balance becomes unattainable in
higher level topologies with a passive front end when using conventional modulation strategies.
In this case, the standard multilevel stepped waveform cannot be retained, and higher

dv /dt

(more than one-level transitions) is necessary to balance the capacitors for certain modulation
indexes. On the other hand, the CHB-MLI is well suited for high-power applications because of
the modular structure that enables higher voltage operation with classic low-voltage
semiconductors. The phase shifting of the carrier signals moves the frequency harmonics to the
higher frequency side, and this, together with the high number of levels, enables the reduction in
the average device switching frequency

(500 Hz),

allowing air cooling and lower losses.

However, it requires a large number of isolated DC sources, which have to be fed from phaseshifting isolation transformers, which are more expensive and bulky, compared with the standard
transformer used for the NPC-MLI. Nevertheless, this has effectively been used to improve the
input power factor of this converter, reducing input current harmonics. Although the FC-MLI is
modular in structure, like the CHB-MLI, it has found less industrial penetration, compared to the
NPC and CHB, mainly because higher switching frequencies are necessary to keep the capacitors
properly balanced, whether a self-balancing or a control-assisted balancing modulation method is
used (e.g., greater than 1200 Hz ). These switching frequencies are not feasible for high-power
13

applications, where usually they are limited in a range of

500 700 Hz .

this topology also

requires initialization of the FC voltages.

2.2.5

Classification of Multilevel Inverter

At first, preliminary studies on multilevel inverters have been performed using three-level
inverter that has been proposed by Nabae. In the study, the third level has been constituted by
using neutral point of DC line and the topology has been defined as diode clamped converter.
Since the first multilevel converter was patented in 1975, many different multilevel inverter
topologies have been introduced and analyzed by different authors.

High Power Converter

Direct Conversion
(AC/AC)

Matrix
Converter

Indirect Conversion
(AC/DC/AC)

Cycloconverter

Voltage Source

High Power 2-level

VSI

Multilevel Matrix
Converter

Current Source

Multilevel

Flying capacitor

NPC

PWM current
source Inverter

Cascaded

Load Commutated
Inverter

Hybrid
Topologies

Stacked Flying capacitor

Figure 2.2 Classification of Multilevel Inverter Topologies [1]

Other high-power converter topologies like current source and matrix inverters are also observed
in the classification. Although they are capable of meeting high power demand, but they are less
preferred because of their limited merits. However, some of which have recently found practical
14

application and this content is not discussed in this dissertation as it is mentioned that, study is
confined to only multilevel structures. Operating principles, multilevel waveform generation,
special characteristics, modulation schemes, and other information related to the NPC and CHB
are demonstrated subsequently.
2.2.6

Concept of Multilevel Inverters [1]

Multilevel inverter includes an array of power semiconductor devices and capacitors voltage
sources, the output of which generates voltages with stepped waveforms. The commutation of
the switches permits the addition of the capacitor voltages to obtain high voltage at the output,
while the power semiconductors have to withstand only reduced voltages. Figure 2.4 shows a
schematic diagram of one phase leg of inverters with different numbers of levels, for which the
action of power semiconductors is represented by an ideal switch with several positions. Form
Figure 2.4, we can observe a two level inverter generates an output voltage with two values
(levels) with respect to negative terminal of the capacitor. While the three level inverter generates
three voltages, and a nine-level inverter generates a nine level output voltages. In all this cases
devices are not arranged in series but they are arranged in such way that, they gain the capability
to generate such kind of voltages. Here, we should remember one important thing i.e. as the
number of steps increases in the output waveforms; harmonic content comes down.

Figure 2.3 Multilevel Inverter

Thus power quality of such waveforms will increase drastically. However, in order to generate
step kind of waveforms in output side, different Multilevel based archetypes are successfully
15

built and verified. But general principle of multilevel inverters is the synthesis of the AC voltage
from several different voltage levels on the DC bus. As the number of voltage levels on the input
DC side increases, the output voltage adds more steps, which approach the sinusoidal wave.
However, from above thought, to present a general idea about the steps in the output waveform,
consider m to be the number of steps of the phase voltage with respect to the negative terminal of
the inverter, and then the number of steps in the voltage between two phases of the load K is
given by equation below
K=2 m+1
And the number of steps P in the phase voltage of a three phase load in wye connection is
P=2 k 1

The term multilevel starts with the three-level inverter introduced by the Nabae. However
topologically, multilevel inverters are largely divided into many configurations. The most
common multilevel converter topologies are the neutral-point-clamped converter (NPC), flying
capacitor converter (FC), and Cascade H-Bridge (CHB). The stepped waveform is synthesized
by selecting different voltage levels generated by the proper connection of the load to the
different capacitive voltage sources. This connection is performed by the proper switching of the
power semiconductors. Then number of levels of a converter can be defined as the number of
steps or constant voltage values that can be generated by the converter between the output
terminal and any arbitrary internal reference node within the converter. Typically, it is a DC-link
node, and it is usually denoted by N and called neutral. To be called a multilevel converter, each
phase of the converter has to generate at least three different voltage levels. This differentiates
the classic two-level voltage source converter (2L-VSC) from the multilevel family. Some
examples of this concept and their respective waveforms for different numbers of levels are
already discussed in previous section. However, it is worth to know more about their design in
details.
There are many ways to combine power semiconductors and capacitive DC sources to generate
multilevel output voltages. So for completeness and better understanding of the advances in
multilevel technology, it is essential to explore the classic multilevel inverters with
performances. Conversely, in order to focus the content of this dissertation on the most recent

16

advances and ongoing research lines, well-established topologies will only be briefly introduced
and referred to existing literature.
Andreas Nordvall [1] has primarily focused his work on Multilevel Inverter Topology Survey.
Multilevel inverters have become more popular over the years in electric high power application
with the promise of less disturbances and the possibility to function at lower switching
frequencies than ordinary two-level inverters. This report presents information about several
multilevel inverter topologies, such as the Neutral-Point Clamped Inverter and the Cascaded
Multicell Inverter. These multilevel inverters will also be compared with two-level inverters in
simulations to investigate the advantages of using multilevel inverters.

Figure 2.4 P2 Five level generalized multilevel inverter

Modulation strategies, component comparison and solutions to the multilevel voltage source
balancing problem are also presented in this work. It is shown that multilevel inverters only
produce 22% and 32% voltage THD while the two-level inverter for the same 1kHz test produces
115% voltage THD. For another simulation, while using lower switching frequency, it is shown
17

that when the two-level inverter generates 25.1W switching losses, the tested multilevel inverters
only produce 2.1W and 2.2W switching losses.
Fang Zheng Peng, [2] discussed on A Generalized Multilevel Inverter Topology with Self
Voltage Balancing. His paper suggests multilevel power converters that provide more than two
levels of voltage to achieve smoother and less distorted AC-to-DC, DC-to-AC, and DC-to-DC
power conversion, have attracted many contributors. This paper presents a generalized multilevel
inverter (converter) topology with self-voltage balancing. The existing multilevel inverters such
as diode-clamped and capacitor-clamped multilevel inverters can be derived from the generalized
inverter topology. Moreover, the generalized multilevel inverter topology provides a true
multilevel structure that can balance each DC voltage level automatically without any assistance
from other circuits, thus, in principle, providing a complete and true multilevel topology that
embraces the existing multilevel inverters. From this generalized multilevel inverter topology,
several new multilevel inverter structures can be derived. Some application examples of the
generalized multilevel converter will be given. This paper has presented a generalized multilevel
inverter topology.

18

Figure 2.5 Generalized P3 Multilevel Inverter

The existing multilevel inverters can be derived from this generalized structure. It has been
demonstrated that the generalized multilevel inverter has self-voltage-balancing ability that the
existing multilevel inverters do not have for the number of levels greater than three (i.e.,) and for
real power conversion. Although the generalized multilevel inverter needs a lot of clamping
switches, diodes, and capacitors, in principle, it is a true and complete multilevel inverter (or
converter).

Compared with the P2 multi-level converter, the P3 multilevel converters

advantageously use less switching devices, diodes, and capacitors. For example, the P2 five-level
inverter needs 20 switching devices/diodes and ten capacitors per phase leg, whereas the P3D
five-level inverter only uses 12 switching devices/diodes and six capacitors. It is possible to
construct a multilevel inverter using basic cells with more than three levels. However, voltage
balancing becomes an issue again.

19

Yuttana Kumsuwan, Suttichai Prem rudeep reechacharn and Vijit Kinnares, [3] discussed about
the a carrier based unbalanced PWM method for the four-leg voltage source inverter fed three
phase induction motor. This paper presents a carrier-based unbalanced pulse width-modulated
method for a three-phase four-leg voltage source inverter (VSI) and its realization for a threephase induction motor. A modulation strategy is developed to synthesize unbalanced two-phase
output voltage waveforms based on the unipolar modulation technique with open-loop V/f
control.

Figure 2.6 Three-phase four-leg voltage source inverter (VSI)

The proposed control scheme in this paper allows independent magnitude controllability and
quadrature phase angle for unbalanced two-phase output voltages. Thus, the modulation
algorithm makes the four-leg VSI inequitable with unbalanced two-phase loads. Simulation and
experimental results confirm the feasibility of the control method for the inverter.
Jun Mei, Bailu Xiao, Ke Shen, Leon M. Tolbert and Jian Yong Zheng [4] focused their work on
Modular Multilevel Inverter with New Modulation Method and Its Application to Photovoltaic
Grid-Connected Generator. This paper proposes a new selective virtual loop mapping (SVLM)
method based on phase disposition PWM (PDPWM) which has voltage balance capability. The
concept of virtual submodule (VSM) is established, and by changing the mapping routines
between the VSM and the real submodule (RSM) with SVLM, the capacitor voltages of the
upper and lower arms can be balanced even if the inverter loses its symmetry.

20

Figure 2.7 Control scheme of the single-phase PV grid-connected inverter.

In order to verify the validity of the modulation method, a five-level MMC PV single-phase gridconnected simulation model reference to the experimental system was built, while the SVLM
would be put into action at 0.5 s. In order to break the symmetry of the system, a resistor of 100
was paralleled to the capacitor of SM 1. The relative simulation and experiment parameters are
shown in Table VI. The PV panel is modeled according to the specification of the commercial
PV panel from Sanyo, HIP-195BA19. The control scheme as shown in Figure 2.7 The method
has been designed to consider the following situations
1. No extra signal should be added to the reference voltage to provide a good basis for the
suppression of the circulating current
2. The possibility of a large number of submodules in one arm
3. Retain the equivalent switching frequency of the PDPWM
4. It could be easily realized in field-programmable gate array (FPGA) for a large-scale
converter which has a large number of submodules. The method is verified through
simulations and experiments.
B. young-Kuk Lee and Mehrdad Ehsani [5] presented their work on A Simplified Functional
Simulation Model for Three-Phase Voltage-Source Inverter Using Switching Function Concept.
In this paper, a functional simulation model for the voltage-source inverter (VSI) using the
switching function concept is studied and the actual implementation of the model is proposed
with the help of MATLAB/Simulink. Also, this concept is extended to the voltage-doubler-type
pulse width-modulated (PWM) ACDC rectifier and the PWM ACDCAC converter. With the
developed functional model, the simplification of the static power circuits can be achieved so
that the convergence and long run-time problems can be solved. Also, in the functional model,
the design parameters, such as voltage and current ratings of the power semiconductor switches
and load current, can be easily calculated.
21

Figure 2.8 Dynamic analysis model of MLI fed Induction motor using volts/hertz control

The general switching function concept is reviewed in brief and the proposed functional models
for the VSI, voltage-doubler rectifier, and PWM ACDCAC converter and their
implementations using MATLAB/Simulink are explained in detail. Also, several informative
simulation results verify the validity of the proposed models. In this paper, a functional
simulation model for the voltage source inverter (VSI) is studied using the switching function
concept. Then, the model is simply implemented by using the functional block of
MATLAB/Simulink. The figure 2.9 shows the example of the implementation for the dynamic
analysis model using volt/hertz speed control algorithm. With the speed and voltage references,
the frequency modulation ratio are calculated. Therefore the dynamic response according to the
volt/hertz control can be effectively measured.
M. G. Hosseini Aghdam, S. H. Fathi [6] presented Modeling of Conduction and Switching
Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter. The designer of power
converters must model the losses of converter switches to optimize the performance of system.
This paper is focused on a model of a three-phase asymmetric multi-level cascaded inverter
losses using switching function concept. The suggested model is based on the semiconductor
characteristics. Simulation results are shown the simplicity, convergence, and reliability of the
suggested model Asymmetric multi-level inverters have exactly the same circuit topology as
22

symmetric multi-level inverters. They differ only in the used capacitor voltages. The properties
of asymmetric multi-level inverters are however quite different from those of their symmetric
versions. Especially the number of output-voltage levels can be dramatically increased. A
number of modulation strategies are used in multi-level power conversion applications. They can
generally be classified into three categorize: Multi-step, Space Vector PWM (SVPWM), and
Carrier-Based PWM (CBPWM). This paper focuses on carrier-based PWM (CBPWM)
techniques which have been extended for use in multi-level topologies by using multiple carriers.
V. T. Somasekhar, K. Gopakumar, M. R. Baiju, Krishna K. Mohapatra, and L. Umanand, [7]
have primarily worked upon A Multilevel Inverter System for an Induction Motor with OpenEnd Windings. In this paper, a multilevel inverter system for an open-end winding induction
motor is proposed. The proposed multilevel inverter system produces multilevel PWM
waveforms ranging from a two-level inverter waveform to a six-level inverter waveform,
depending on the range of modulation. In the power circuit topology proposed in this paper, an
open-end winding induction motor is fed with a three-level inverter at one end and a two-level
inverter at the other. Unequal DC-link voltages are employed for individual inverters. An
alternative circuit configuration is adopted to realize the three-level inverter, in which three-level
inversion is obtained by connecting two two-level inverters in cascade. The proposed inverter
scheme is capable of producing 512 voltage space-vector combinations distributed over 91
voltage space-vector locations. The total number of constituent sectors in this scheme is
enhanced to 150. Consequently, a further reduction of the switching ripple in the motor phase
voltage waveform is achieved with this circuit configuration, With the proposed scheme, the
motor phase voltage waveform shows a smooth six-level inverter waveform in the range of
higher modulation.
Leon M. Tolbert, Fang Zheng Peng, and Thomas G. Habetler, [8] discussed about Multilevel
Converters for Large Electric Drives. The paper suggested that the multilevel voltage source
inverters unique structure allows them to reach high voltages with low harmonics without the
use of transformers or series-connected synchronized switching devices. The general function of
the multilevel inverter is to synthesize a desired voltage from several levels of DC voltages. For
this reason, multilevel inverters can easily provide the high power required of a large electric
drive. As the number of levels increases, the synthesized output waveform has more steps, which
23

produces a staircase wave that approaches a desired waveform. Also, as more steps are added to
the waveform, the harmonic distortion of the output wave decreases, approaching zero as the
number of levels increases. As the number of levels increases, the voltage that can be spanned by
summing multiple voltage levels also increases. The structure of the multilevel inverter is such
that no voltage sharing problems are encountered by the active devices. This paper proposes two
multilevel inverter configurations where devices are switched only at the fundamental frequency
and the inverter output line voltage THD is 5% without the use of any filtering components. In
addition, a control scheme will be demonstrated in the multilevel diode-clamped converter that
obtains well-balanced voltages across the DC-link capacitors.
Alessandro Luiz Batschauer, Samir Ahmad Mussa, and Marcelo Lobo Heldwein, [9] focused on
Three-Phase Hybrid Multilevel Inverter Based on Half-Bridge Modules. The paper is structured
to emphasize on a novel hybrid multilevel converter able to achieve four, five or six level
operation has been proposed. The main advantage for this solution is the possibility of reduction
of the power ratings for insulated DC sources compared to the CHB and to other hybrid solutions
such as the VSI cascaded with full bridge converters. The operation principle of the converter
has been clarified and the achievable space vector spaces presented. A four-level hybrid
modulation scheme has been presented, which allows unidirectional power flow in all DC
sources for any modulation index and, thus, lowers the power demand on the insulated DC
sources for high modulation indexes. A pair of 12-pulse rectifiers to supply the converter is
proposed to minimize input current harmonics. The theoretical analysis of the output voltages
has been presented and experimentally verified. Furthermore, the modulation scheme is able to
generate, both, phase and line voltages with low THD. Experimental results based on a built
prototype have validated the performed analysis and shown the relevant operating characteristics
of the proposed converter.
Surin Khomfoi, Nattapat Praisuwanna, Leon M. Tolbert, [10] worked basically on A Hybrid
Cascaded Multilevel Inverter Application for Renewable Energy Resources Including a
Reconfiguration Technique. In this paper the hybrid cascaded multilevel inverter application for
renewable energy resources including a reconfiguration technique has been proposed. The
modified PWM technique has also been developed to reduce switching losses. Also, the
proposed topology can reduce the number of required power switches compared to a traditional
24

cascaded multilevel inverter. Simulation and experimental results have been validated including
efficiency evaluation. The switching losses of the HMI are less than the conventional multilevel
inverter; consequently, the system efficiency would be improved by utilizing the HMI. In
addition, 97.33% inverter efficiency has been achieved based on this particular load condition. A
possible reconfiguration technique after a fault condition has also been developed to improve the
system reliability. The results show that proposed hybrid inverter topology is a promising method
for a low voltage DC microgrid interfacing with renewable energy resources in a
telecommunication building.
2.3 Control Techniques for Multilevel Inverters
Pulse Width Modulation (PWM) techniques for two level inverters have been studied extensively
during the past decades. Many different PWM methods have been developed to achieve the
following aims; wide linear modulation range, reduced switching loss, lesser total harmonic
distortion in the spectrum of switching waveform, easy implementation, less memory space and
computation time on implementing in digital processors for the proposed work. The two most
widely used PWM schemes for multi-level inverters are the carrier based PWM (sine-triangle
PWM or SPWM) techniques and the space vector based PWM techniques. [11] These
modulation techniques are extensively studied and compared for the performance parameters
with two level inverters. The SPWM schemes are more flexible and simple to implement, but the
maximum peak of the fundamental component in the output voltage is limited to 50% of the DC
link voltage and the extension of the SPWM schemes into over-modulation range is difficult. In
the recent past the multilevel power converters have drawn a tremendous interest in the field of
high voltage and high power applications field in industries. The multilevel inverter approach
allows the use of high power and high voltage electric motor drive systems. Using the multilevel
inverter concept, a divide and conquer approach allows more flexibility and control over the
discrete components that makeup the system. In the researches on multilevel inverters, their
corresponding PWM control strategies are the emerging research areas. In high power and high
voltage applications, the two level inverters, however, have some limitations in operating at high
frequency mainly due to switching losses,

dv /dt

and

di/dt

stresses in power

semiconductor devices and constraint of the semiconductor power device ratings. For high
voltage applications two or more power devices can be connected in series to achieve the desired
25

voltage ratings and in parallel to achieve the current ratings. Multilevel inverters can increase the
power by (m1) times than that of two level inverter through the series connection of power
semiconductor devices. This research focuses on the different control strategies and a suitable
modulation strategy is selected based on the outputs obtained through the simulations on the
MATLAB/Simulink software environment.[12]

2.3.1

Multicarrier PWM Techniques

Sinusoidal pulse width
modulation

Modulating signal

Carrier signal

Pure sinusoidal

Phase disposition

Third harmonic
injection

Phase opposition
disposition

Dead band

Alternate POD

Hybrid

Phase shifted
Figure 2.9 Classification of Sinusoidal Pulse Width Modulation

2.3.2 Phase Disposition (PDPWM) [12, 14]

In this method all carriers have the same frequency, same amplitude and same phase but they are
just different in DC offset to occupy contiguous bands. Since all carriers are selected with the
same phase, this method is known as PD strategy.
Carrier arrangement for this strategy is shown in Figure 2.10

26

Figure 2.10 Phase Disposition

2.3.3 Alterative Phase Opposition Disposition (APOD) [12,

14]

Figure 2.11 Alternative Phase Disposition

This technique requires each of the

(m 1) carrier waveforms, for an m-level phase

waveform, to be phase displaced from each other by 180 alternately as shown in Figure 2.11. The
most significant harmonics are centered as sidebands around the carrier frequency fc and
therefore no harmonics occur at fc.

27

2.3.4 Phase Opposition Dispositions (POD) [12, 14]

The carrier waveforms are all in phase above and below the zero reference value however, there
is 180 phase shift between the ones above and below zero respectively as shown in Figure 2.12.
The significant harmonics, once again, are located around the carrier frequency fc for both the
phase and line voltage waveforms. The three disposition PWM techniques that are APOD, PD
and POD generate similar phase and line voltage waveforms. Furthermore, for all of them, the
decision signals have average frequency much lower than the carrier frequency.

Figure 2.12 Phase Opposition Disposition

2.3.5 Hybrid (H) [12, 14]

This technique, as mentioned earlier, combines the previously presented ones (disposition) and
the well-known phase shifted multicarrier technique. The bands used for modulation are only
two, however, each time the level of the power converter is increased, and more triangular
carriers are introduced and phase shifted accordingly. The two carriers above zero have the same
peak to peak value and the same frequency fc. However, there is an 1800 phase shift between
them. The same applies for the two carriers below zero. In the case that the number of converter
levels is higher, the carriers are phase shifted accordingly, that is 1200 for a 7 level system and
900 for a 9 level system and so on and so forth. It is important to note that the significant
harmonics are concentrated around multiples of (m - 1)/2 of the carrier frequency fc. For
instance, for a 5-level converter, the harmonics are located around 2fc, for a 7 level around 3fc
28

and for a 9 level around 4fc. The gap between the fundamental and the first significant
harmonics increases accordingly as shown in Figure 2.13

Figure 2.13 Hybrid Scheme

P. Senthilkumar, M. Balachandran, N. P. Subramaniam, [11] discussed primarily on Cascaded HBridge Multilevel Inverter Using SPWM. This paper presents the concert of flying capacitor
multilevel inverter and cascaded H-bridge multilevel inverter. To improve the performance of
Flying Capacitor Multilevel Inverter (FCMLI) the switching pattern selection scheme is used. By
this scheme the capacitor voltage fluctuation is reduced without using voltage feedback. The
elimination of harmonics in a cascaded multilevel inverter (MLI) by taking the unequal of
separated DC source is presented. DC sources may be batteries, solar cells, etc. A fundamental
switching scheme is used, which achieves the fundamental in the output voltage while
eliminating the lower order harmonics and to produce a nearly sinusoidal output. The FFT
spectrums for the outputs are presented to study the reduction in the harmonics. The circuit is
simulated using MATLAB/SIMULINK. The simulation results are verified. The flying capacitor
multilevel inverter uses a ladder structure of DC side capacitors where the voltage on each
capacitor differs from that of the next capacitor. The sinusoidal PWM scheme is used for
modulation control. In cascaded H-bridge multilevel inverter separated unequal DC sources are
used to generate sinusoidal output. A fundamental switching scheme is used and produces a
nearly sinusoidal output. This cascaded inverter design is to get the improved sinusoidal output
29

of an inverter and gives reduced THD%. The elimination of harmonics in a cascade H-bridge
multilevel inverter by considers the inequality of separated DC source. FFT spectrum shows the
reduction in the harmonics in the output voltage.
C.R. Balamurugan, S.P. Natarajan, and R. Revathy, [12] focused their work on Analysis of
Control Strategies for Diode Clamped Multilevel Inverter. This work presents the comparison of
various Pulse Width Modulation (PWM) strategies for the three phase Diode Clamped Multi
Level Inverter (DCMLI). The main contribution of this paper is the proposal of new modulation
schemes with Variable Amplitude (VA) and various new schemes adopting the constant
switching frequency and also variable switching frequency multicarrier control freedom degree
combination concepts are developed and simulated for the chosen three phase DCMLI. The three
phase DCMLI, is controlled in this paper with Sinusoidal PWM (SPWM) reference along with
triangular carriers and analysis is made among both without carrier overlapping and with Carrier
Overlapping (CO) techniques to choose the better strategy by performing simulation using
MATLAB/SIMULINK. The variation of Total Harmonic Distortion (THD) and fundamental
RMS output voltage is observed for various modulation indices. It is observed that among the
various equal amplitude PWM strategies, COPWM-C provides less THD and higher RMS
voltage. It is recognized that among the various variable amplitude PWM strategies,
VACOPWM-C provides less THD and VACOPWM-B provides higher RMS voltage. By
comparing the equal amplitude PWM strategies with the variable amplitude PWM strategies it is
inferred that VACOPWM-C provides less THD and VACOPWM-B provides higher RMS
voltage. It is also inferred that carrier overlapping techniques provides better results compared to
the without carrier overlapping techniques.
Rajesh K. Ahuja, Lalit Agarwal, Pankaj Kumar, [13] discussed about simulation of Single Phase
Multilevel Inverters with Simple Control Strategy Using MATLAB. This paper presents the
simulation of single phase three level, five level, seven level, nine level and eleven level
inverters. These different level inverters are realized by cascading one, two, three H- Bridges
respectively in MATLAB. A multilevel inverter achieves high power ratings and improves the
performance of the whole system in terms of harmonics. In this paper a simple control strategy is
applied for switching the switches at appropriate conducting angles with suitable delays. The
Multilevel inverter is used to reduce the harmonics. The inverters with a large number of steps
30

can generate high quality voltage waveforms. The simulation of single phase three level, five
level, seven level, nine level and eleven level inverters is done in MATLAB/Simulink. The FFT
spectrums for the outputs are compared and presented to validate the proposed control strategy.
Janyavula Deepthi, Dr S N Saxena, [14] worked on Study of Variation of THD in a Diode
Clamped Multilevel Inverter with respect to Modulation Index and Control Strategy. Due to the
ability to synthesize waveforms with better harmonic spectrum and attain higher voltages, multilevel inverters are receiving increasing attention in the past few years. The multilevel inverter
was introduced as a solution to increase the converter operating voltage above the voltage limits
of classical semiconductors. In this paper, a Diode Clamped Multilevel Inverter is controlled
with Sinusoidal PWM, Third Harmonic Injection PWM and Sixty degrees PWM and the
variation of Total Harmonic Distortion in their outputs are observed. Also, a Diode Clamped
inverter is controlled by Sinusoidal PWM technique and by varying the modulation index,
variation of Total Harmonic Distortion is observed.
Dr. Muhammad H. Rashid, [15] is author of Power Electronics: Circuits, Devices, and
Applications. In his book multilevel inverter topologies and their applications are briefly
presented. Multilevel inverter is based on the fact that sine wave can be approximated to a
stepped waveform having large number of steps. The steps being supplied from different DC
levels supported by series connected batteries or capacitors. The unique structure of multi- level
inverter allows them to reach high voltages and therefore lower voltage rating device can be
used. As the number of levels increases, the synthesized output waveform has more steps,
producing a very fine stair case wave and approaching very closely to the desired sine wave.
Normally, voltage or current converters, as they generate discrete output waveforms, forcing the
use of machines with special isolation, and in some applications large inductances connected in
series with the respective load are required. In other words, neither the voltage nor the current
waveforms are as expected. Also, it is well known that distorted voltages and currents waveforms
produce harmonic contamination, additional power losses, and high frequency noise that can
affect not only the power load but also the associated controllers. All these unwanted operating
characteristics associated with PWM converters can be overcome with multi-level converters.

31

CHAPTER 3. SYSTEM DEVELOPEMENT

3.1 Introduction
In the previous chapter, the exhaustive literature survey about the MLI topologies, various
manufacturing companies, detailed classification of high power inverter and commonly used
SPWM switching techniques and a scheme for their real time implementation are presented.
32

In this chapter, 5-level Diode clamped MLI and 5-level Cascaded MLI along with their
advantages, disadvantage and area of application are discussed in detail. The chapter is divided
in three sections. In first section, detailed simulation of 5-level diode clamped MLI in
MATLAB/Simulink is carried out using SPWM switching techniques. In second section, detailed
simulation of 5-level cascaded MLI in MATLAB/Simulink is carried out using the same
switching techniques. In third section switching function analysis of multilevel inverter is
presented which gives the generalized switching model for five level MLI.
3.2 Diode Clamped Inverter
The diode clamped converter proposed by Nabae, Takahashi, and Akagi in 1981 was essentially
a three-level diode-clamped inverter. In the 1990s several researchers published articles that have
reported experimental results for four, five, and six-level diode-clamped converters for such uses
as static VAR compensation, variable speed motor drives, and high-voltage system
interconnections. A three-phase six-level diode-clamped inverter is shown in Figure 3.1. Each of
the three phases of the inverter shares a common DC bus, which has been subdivided by five
capacitors into six levels. The voltage across each capacitor is VDC, and the voltage stress across
each switching device is limited to VDC through the clamping diodes. Figure 3.1 shows the
output voltage levels possible for one phase of the inverter with the negative DC rail voltage V 0
as a reference. State condition 1 means the switch is on, and 0 means the switch is off. Each
phase has five Complementary switch pairs such that turning on one of the switches of the pair
requires that the other complementary switch be turned off. The complementary switch pairs for
phase leg a are

(S a 1 , S a 1),(S a 2, S a 2) ,(S a 3 , S a 3) ,(S a 4 , S a 4),(S a 5 , S a 5) .

Figure 3.2 also shows that in a diode-clamped inverter, the switches that are on for a particular
phase leg are always adjacent and in series. For a six-level inverter, a set of five switches is on at
any given time. The line voltage

V ab

consists of a phase-leg a voltage and a phase-leg b

voltage. The resulting line voltage is an 11-level staircase waveform. This means that an m-level
diode-clamped inverter has an m-level output phase voltage and a
voltage.

33

( 2 m1 )

level output line

Figure 3.1: Power circuit of Diode Clamped Inverter

Figure 3.2 Switching logic of diode clamped inverter

Although each active switching device is required to block only a voltage level of V dc , the
clamping diodes require different ratings for reverse voltage blocking.
34

Figure 3.3 Working Scheme of Three Level Diode clamped Inverter

Figure 3.4 Three Level Output Voltage Waveform

Using phase A of Figure 3.1 as an example, when all the lower switches
S a5

block

are turned on, D4 must block four voltage levels, or

3 V dc , D2

must block 2V dc , and

D1

S a1

4 V dc . similarly,

through

D3

must

must block V dc . If the inverter is

designed such that each blocking diode has the same voltage rating as the active switches, D n
will require n diodes in series; consequently, the number of diodes required for each phase would
35

be

(m1)(m2) .

thus, the number of blocking diodes is quadratically related to the

number of levels in a diode-clamped converter.

The basic working of three level diode clamped inverter is demonstrated in the Figure 3.3
When switch S1a and S2a are ON, +VDC is connected to the load point A, and we get one voltage
level at the output. During the zero output switch S 2a and S3a are turned ON. In order to get the
negative level at the output, switch S3a and S4a are turned on. The detailed waveform of the output
voltage is shown in the Figure 3.4.
The Advantages and Disadvantages of diode clamped inverters are discussed below
Advantages:
a) All of the phases share a common DC bus, which minimizes the capacitance
requirements of the converter. For this reason, a back-to-back topology is not only
possible but also practical for uses such as a high-voltage back-to-back inter-connection
or an adjustable speed drive.
b) The capacitors can be pre-charged as a group.
c) Efficiency is high for fundamental frequency switching.
Disadvantages:
a) Real power flow is difficult for a single inverter because the intermediate DC levels will
tend to overcharge or discharge without precise monitoring and control.
b) The number of clamping diodes required is quadratically related to the number of levels,
which can be cumbersome for units with a high number of levels.
Applications:
a) Electric traction systems.
b) Medium voltage Industrial Drives
c) Reactive power compensation in wind energy systems.
3.3 MATLAB/Simulink Simulation of Five Level Diode Clamped Multilevel Inverter
MATLAB/Simulink is a high-level language and interactive environment for numerical
computation, visualization, and programming. Using MATLAB, we can analyze data, develop
algorithms, and create models and applications. The language, tools, and built-in math functions
enable us to explore multiple approaches and reach a solution faster than with spreadsheets or
traditional programming languages.
36

Figure 3.5 Power Circuit of Five Level Diode clamped Multilevel Inverter in MATLAB/Simulink

Figure 3.6 Switching Pattern of Five Level Diode Clamped Multilevel Inverter in MATLAB/Simulink

37

The following Figure 3.5 shows the MATLAB/Simulink simulation of five level diode clamped
multilevel inverter. In the following simulation each of the three limbs are connected to a
common DC bus of 400Voltage. The DC bus is subdivided by four capacitor to form four
separate DC voltage levels. The capacitors used is having capacity of 2200 F. the
complementary Switching pair for the phase a are a1 & a 5, a2 & a6, a3 & a7, a4 & a8. The same
is shown in the Figure. 3.6 The main drawback of this technique is that it requires different
ratings of diode for the clamping purpose because each diode has to block different reverse
voltages. Although the same ratings of capacitor can be used for this technique because each
switching devise has to block only same voltage of VDC.
3.4 Cascaded Type of Multilevel Inverter
A cascaded multilevel consists of a series of H-bridge inverter units.

Figure 3.7 Power circuit of Cascaded Multilevel Inverter

The general function of this multilevel inverter is to synthesize desired voltage from several
separate DC sources, which may be obtained from batteries, fuel cells, or solar cells. In cascaded
38

multilevel inverter each SDCS is connected to an H-bridge inverter. The AC terminal voltage of
different level inverter are connected in series.
A single-phase structure of an m-level cascaded inverter is illustrated in Figure 3.7
Each separate DC source (SDCS) is connected to a single-phase full-bridge, or H-bridge,
inverter. Each inverter level can generate three different voltage outputs,
V dc

switches,
whereas

+V dc , 0,

and

by connecting the DC source to the ac output by different combinations of the four

S 1, S 2 , S 3 ,
V dc

and

S 4.

To obtain

+V dc , switches S and S are turned on,

1
4

can be obtained by turning on switches

S 2 and

S 3 . By turning on

S 1S 2S 3S 4 , the output voltage is 0. The ac outputs of each of the different full-bridge

inverter levels are connected in series such that the synthesized voltage waveform is the sum of
the inverter outputs. The number of output phase voltage levels m in a cascaded inverter is
defined by m=2 s +1 , where s is the number of separate DC sources. The phase voltage
v an=v a 1+v a 2+v a 3+ v a 4+ v a 5.
The Fourier transform for this waveform is as follows
V ( wt )=
3.4.1

4 V dc
sin(nwt )
[cos ( 1) + cos ( 2 ) +.....+cos ( s ) ]

2
n

Five level Cascaded Multilevel Inverter

The basic structure of five level cascaded inverter is shown in the Figure 3.8

39

(2)

Figure 3.8 Basic Structure of Five Level Cascaded Multilevel Inverter.

40

Figure 3.9 Schematic Representation for Different Voltage Levels in Output

Each phase requires 8 switches to obtain five voltage levels output phase voltage. The logical
pattern for the switching is shown in the Figure 3.9
TABLE 3.1
Switching pattern for Cascaded multilevel inverter

Switches
Upper bridge
S1a and S2b

Lower bridge
S3a and S4b

V +V =2 V

S1a and S2b

S3a and S3b

V +0=V

S2a and S2b

S4a and S4b

0+0=0

S1a and S1b

S3a and S3b

0+0=0

S1b and S2a

S3a and S3b

V + 0=V

S1b and S2a

S3b and S4a

V V =2 V

Sr. no

Output voltage

The advantages and disadvantages of the cascaded inverters are listed below.
Advantages:
a) The number of possible output voltage levels is more than twice the number of DC
sources (m=2 s +1).
b) The series of H-bridges makes for modularized layout and packaging. This will enable
the manufacturing process to be done more quickly and cheaply.
Disadvantages:

41

a) Separate DC sources are required for each of the H-bridges. This will limit its application
to products that already have multiple SDCSs readily available
Applications:
a) Hybrid electrical vehicles
b) Solar PV systems.
c) Regenerative type induction motor drives.
3.5 MATLAB/Simulink Simulation of Five Level Cascaded Multilevel Inverter

Figure 3.10 Basic Block Diagram for Five Level Cascaded Multilevel Inverter

The figure 3.10 shows the development of the switching pulse generation for one phase (8
switches). Firstly a pure sinusoidal wave with 50 Hz of frequency and 0.8 as modulation index is
designed and then for 5-level output, (N-1) i.e. 4 carrier pulses are formulated in reference
generation block. These 4 carrier pulses are compared with sinusoidal reference wave to get 8
different switching patterns for driving the IGBT modules.

42

Figure 3.11 Power circuit of Five Level Cascaded Multilevel Inverter in MATLAB/Simulink

Figure 3.11 shows the power circuit of 5-Level cascaded multilevel inverter. The 24 different
pulses are generated using the pulse generation block shown in the figure 3.12. Here each Hbridge is characterized by its own DC source. For the sake of simulation we have considered
equal DC source of 100V in each H-bridge. The main advantage of such configuration is, if we
want to have 400V as a peak value of output line-line voltage then 100V source is required in
each bridge. Use of small voltage source allows us to use switches with low voltage ratings. The
output of the inverter is star connected and then given to three-phase VI measurement block
followed by three phase R-L load. The VI measurement block records the line and phase voltage
as well as current of the cascaded MLI which is later used to calculate the THD value.

43

Figure 3.12 Switching Pattern of Five Level Cascaded Multilevel Inverter in MATLAB/Simulink

The Figure 3.12 shows the 8 switching pluses pattern for driving one phase of the output. The
accuracy of the SPWM is dependent on the frequency of carrier signal selected. We have used
the carrier signal frequency as 1500 Hz. But the use of high frequency SPWM leads to the
disadvantage of higher switching losses in the inverter bridge causing more heating. So a proper
selection of carrier frequency is require to be done. It is clearly seen that pulse no 1, 3, 5, 7 are
opposite to the 2, 4, 6, 8. This care has taken in order to avoid the short-circuit of the DC source
connected to both legs of H-bridge module.
3.5.1 MATLAB/Simulink Simulation of 5-level MLI using POD and APOD Technique
Level-shifted PWM (LSPWM) is the natural extension of bipolar PWM for multilevel inverters.
Bipolar PWM uses one carrier signal that is compared to the reference to decide between two
different voltage levels, typically the positive and negative busbars of a VSI. By generalizing this
idea, for a multilevel inverter, m1 carriers are needed. They are arranged in vertical shifts
instead of the phase-shift used in PS-PWM. Each carrier is set between two voltage levels; hence
the name B level shifted. Since each carrier is associated to two levels, the same principle of
bipolar PWM can be applied, taking into account that the control signal has to be directed to the
44

appropriate semiconductors in order to generate the corresponding levels. The carriers span the
whole amplitude range that can be generated by the converter. They can be arranged in vertical
shifts, with all the signals in phase with each other, called phase disposition (PD-PWM); with all
the positive carriers in phase with each other and in opposite phase of the negative carriers,
known as phase opposition disposition (POD-PWM); and alternate phase opposition disposition
(APOD-PWM), which is obtained by alternating the phase between adjacent carriers. An
example of these arrangements for a five-level inverter (thus four carriers) is given in Fig. 3.13,
respectively.

Figure 3.13 Phase shifted and Level shifted PWM (a)

Phase shifted PWM (b) PD, (c) POD, (d) APOD

In brief, rather than level shifted PWM, phase shifted PWM technique has finite merits like, no
rotation in switching, less switching losses and easy to implement. Indeed, in present article all
productive topologies are implemented with sinusoidal PWM approach. Next sections provide

45

the details of conventional CMI topology and performance verifications and challenging aspects
to resolve.
3.6 Control of Multilevel Inverter
The cascaded multilevel inverter was first introduced for motor drive applications, in which an
isolated and separate DC source is needed for each H-bridge unit. However, another paper
presented the idea of using cascade multilevel inverter for reactive and harmonic compensation,
from which isolated DC sources can be omitted. Additional work further demonstrated that the
cascaded inverter is suitable for universal power conditioning of power systems, especially for
medium voltage systems. The inverter provides lower costs, higher performance, less
electromagnetic interference (EMI), and higher efficiency than the traditional PWM inverter for
power line conditioning applications, both series and parallel compensation. Although the
cascaded inverter has an inherent self-balancing characteristic, because of the circuit component
losses and limited controller resolution, a slight voltage imbalance can occur.

Figure 3.14 Schematic of control scheme for multilevel inverter

A simple control scheme, which ensures DC voltage balance, has been proposed for reactive and
harmonic compensation Figure 3.14 shows its control block diagram that contains a
proportionalintegral (PI) regulator to adjust the trigger angle and to ensure zero steady-state
error between the reference DC voltage and the DC bus voltage.

46

3.7 Switching Function Analysis of Multilevel Inverter

As shown in Figure 3.15, the static power converters/inverters can be modeled as a black box
with the input and output ports. The DC and AC variables can be input and output according to
the operation mode. Then, the transfer function is obtained to describe the task to be performed
by the circuits. In particular, the transfer function can be used to compute a dependent variable in
terms of its respective independent circuit variable.

Figure 3.15 Static power converter

Also, in PWM, the waveform to be modulated is considered the independent variable and the
resulting modulated waveform is the dependent variable. For example, in the case of a VSI, the
output voltage is dependent variable and it depends on the input voltage, which is the
independent variable. Therefore, the general transfer function can be defined as
Transfer function=

Dependent varable
Independent variable

Unmodulated waveform
Modulated waveform

With the applied control strategy, each transfer function consists of the various particular
switching functions. Using the switching function theory, the detailed relationship between the
input and output variables can be obtained. Therefore, obtaining the proper switching function is
very important in order to describe the role of the static power converters/inverters. The detailed
theoretical explanation of the switching function is well addressed in the following analysis.
3.7.1

Switching Function for VSI

47

Based on the transfer function theory, in the VSI, input current

V
( ab , V bc , V ca )

I
( a , I b , I c )

are the dependent variables and input voltage

I
( ) and output voltage

(V d )

and output current

are the independent variables. Therefore, the relationship between the input and

output variables can be expressed as

V
( ab , V bc , V ca )=TF V d

(4)

I
I
T
[ a , I b , I c ]
( )=TF

(5)

In order to define the switching function, a control strategy to be applied should be selected.
Here SPWM technique is considered as a control strategy. Based on SPWM the switching
functions are designed also they are used to calculate inverter line-to-line voltages and phase-tophase voltages. Based on the switching function, a functional model for the 5-level VSI is built
by using MATLAB Simulink and then later on it is integrated with dSPACE 1104 controller.
Each

phase

has

four

switching

functions

SF 1 , SF 2 , SF3 , SF 4 , SF 1 , SF 2 , SF3 , SF 4 SF 1 , SF2 , SF 3 , SF4 .

a

the V a 0 ,V b 0 , V c 0
Can be obtained as

48

such

as

Using switching functions

Vd
An sin(nwt )
2
Vd
V a 0=
2

SF a=

SF b=

SF c =

(6)

Vd
An sin(n (wt 120))
2
Vd
V b0=
2

Vd
A n sin(n(wt +120))
2
V
V c 0= d
2

(7)

(8)

V
Then inverter line-to line voltages ( ab , V bc , V ca ) can be derived as

V ab=V a 0 V b 0=

V bc =V b 0V c0=

V ca =V c 0V a 0=

3V d
2

3 V d
2

3V d
2

A n sin(n(wt + 30))

(9)

A n sin(n( wt90))

(10)

A n sin (n( wt +150))

(11)

Figure 3.16 Switching function implementation for generating A phase voltage

49

Based on the equations 6,7 and 8 switching functions are modelled for generating A phase
voltage. Similar analysis is done to get the three phase-to-phase voltages using equations 9, 10
I

a
,
I b , I c) .
(
and 11. Next, the load current block is used to obtain the load currents

Assuming the load consist of an R-L load and balanced one, the load currents are derived as
ratios of the phase-to-phase voltages and respective impedances as,
I a=

V an
V an
=
Z (R+ jwL)

(12)

I b=

V bn
V bn
=
Z (R+ jwL)

(13)

I c=

V cn
V cn
=
Z (R+ jwL)

(14)

Figure 3.17 Switching function implementation for generating phase currents

50

Figure 3.18 switching function implementation for separation of switch and diode currents

The switching currents for all switches can be calculated by the product of load currents with the
corresponding switching function. The switch current consists of two parts viz. pure switch
current and diode current. The algorithm used in figure 3.18 both pure switch as well as diode
current from the switching current.

51

CHAPTER 4. PERFORMANCE ANALYSIS

4.1 Introduction
In the previous chapter, MATLAB simulation of both 5-level diode clamped MLI and 5-level
cascaded MLI are discussed in detail, also the generalized switching function model of 5-level
MLI is presented using switching function theory.
In this chapter, the output voltage and current waveform obtained from the MATLAB simulation
are presented. This chapter is divided in three sections. In the first section, simulation results
obtained from 5-level diode clamped MLI are discussed. In the second section, simulation results
obtained from 5-level cascaded MLI are presented. In the third section simulation results from
the generalized switching function model are presented for 5-level MLI. The results from
generalized switching function theory are validated by comparing them with the results shown in
first two sections. In the last section the real time implementation of MLI in control desk
environment using dSPACE 1104 is discussed. One of the key feature of use of
MATLAB/Simulink is that it allows the user to simulate the design over a specified period of
time. This way it is possible to analyze the time response of inverter system. For experimental
verification of pulse generation on CRO, dSPACE 1104 is used as the main controller.
4.2 Five Level Diode Clamped Multilevel Inverter
52

The Figure 4.1 shows the three phase line voltages and line currents generated by five level
diode clamped multilevel inverter. The line voltage consists of the phase-leg voltage of terminal
a and the negative phase-leg voltage of terminal b. each phase leg voltage tracks one half of
sinusoidal wave. The resulting line voltage is a nine level staircase wave. This implies that mlevel converter has m-level output phase-leg voltage and (2 m1) level output line voltage.
In diode clamped inverter each switching device is required to block a voltage level of
V dc
(m1) , the clamping diodes need to have different reverse voltage blocking ratings. If the
blocking voltage rating of each diode is same that of the switching device, the number of diode
required for each phase is
in m. thus for m=5,

N D =( m1 ) ( m2 ) .

N D =12.

This number represents a quadratic increase

When is m is sufficiently high, the number of diode makes the

system impractical to implement, which in effect limits the number of levels.

Figure 4.1 Line to Line Voltage and Current waveform for Five Level Diode Clamed Multilevel Inverter in
MATLAB/Simulink

53

The figure 4.2 clearly shows the output phase voltage is of staircase type and formed by the
series addition of the different voltage levels. As compared to the five level cascaded multilevel
inverter results, this shows higher distortion in the voltage waveform.

Figure 4.2 Phase to Phase Voltage and Current waveform for Five Level Diode Clamed Multilevel Inverter in
MATLAB/Simulink

This is primarily because of the unbalancing in the neutral point clamping. This problem can be
resolved by creating a closed loop system. The comparison analysis between these two
techniques is done in the later part of the thesis. The Figure 4.2 shows the three phase voltages
and phase currents generated by five level diode clamped multilevel inverter.
4.3 Five Level Cascaded Multilevel Inverter
Figure 4.3 shows the output line-line voltages across the load. As discussed earlier the peak value
of each phase reaches to 400V because of the use of 100V DC source in each H-bridge module.
The inrush current in line-line current waveform of Y-phase shows that during switching ON, Yphase output reaches the maximum value first so it drives the major part of load as R and B
phase output are building. After one cycle system stabilizes and draws a balanced current from
the inverter.

54

Figure 4.3 Line to Line Voltage and Current of 5 Level Cascaded Multilevel Inverter in MATLAB/ Simulink

Figure 4.4 shows the output phase-phase voltages and currents across the load. The proposed
cascaded configuration is star connected so that the output line currents and phase current
waveforms are same.

Figure 4.4 Phase Voltage and Current of 5 Level Cascaded Multilevel Inverter in MATLAB/ Simulink

4.4 Five Level Cascaded MLI with POD Switching Technique

55

The phase opposite disposition or POD, uses four carriers, two for the positive voltage levels and
two for the negative voltage levels. The negative voltage levels are shifted by 180 degrees with
respect to the carrier for the positive voltage levels. The carriers are multiplied for their
corresponding voltage level sign in order to fill the entire voltage range.

Figure 4.5 A phase 5-level voltage waveform with POD

Figure 4.5 shows the 5-level output voltage waveform of A phase with POD switching
technique. The total harmonic distortion is found to be 28.7% for the modulation index of 0.8.
4.5 Five Level Cascaded MLI with APOD Switching Technique
The alternative phase opposite disposition, or APOD, is based on four carriers that varies in the
initial starting voltage level and phase. These two carriers are then multiplies consequently over
the entire voltage range. The displacement of carrier does not affect the amplitude or the
frequency of the carriers.

56

Figure 4.6 A phase 5-level voltage waveform with APOD

Figure 4.6 shows the 5-level output voltage waveform of A phase with APOD switching
technique. The total harmonic distortion is found to be 29.17% for the modulation index of 0.8. It
is to be noted that the number of switching per modulation cycle is dependent of the carrier
frequency in the case of PWM based modulations (both POD and APOD). The synthesized
output voltage has a low content of harmonic distortion for all modulations schemes, even at low
frequencies.
4.6 Generalized Switching Function for Five-level Inverter
Based on the above theoretical explanation in chapter 3 switching function model of the 5-level
multilevel inverter is carried out. The phase to phase voltage generated by switching function is
shown in the Figure 4.7

57

Figure 4.7 A Phase voltage

Similarly three line-to-line voltages are also generated as follows.

Figure 4.8 Line-to-line voltages

The figure 4.8 shows that the peak value of phase voltage reaches to 200V with five different
voltage levels (200V, 100V, 0V, -100V and -200V) and the figure 4.6 shows the output line-line
voltages. The results obtained in figure 4.7 and 4.8 by using switching function model are
verified by comparing them with the results obtained from the previous results shown in figure
4.3 and 4.4

58

Figure 4.9 Phase currents in three phase

The following current waveform shown in figure is generated by the switching function analysis
and it is validated by the results obtained by the MATLAB simulation carried out in the earlier
part of the thesis. Both result shows similar kind of behavior.
The following Figure 3.18 in last chapter shows the separation algorithm of switching current as
well as diode current from the phase current waveform.
Figure 4.10 to 4.16 shows the switching function signals for the 5-level multilevel inverter
obtained from SPWM strategy. Based on switching function of a phase, the inverter voltages
parameter such as phase voltages

V an ,V bnV cn

succesfuly derived. Also the balanced load currents

, line-line voltages
I a , I bI c

V ab ,V bc V ca

can be

are obtained as shown in figure

4.9. By multiplying the load currents with the switching function, the switch currents can be
obtained which are shown in Figure 4.10 to 4.14. Then, using the pure current-generating block
as shown in Figure 3.18 in the chapter, the switch currents are divided into the pure switch
current and pure diode currents shown in Figure 4.15 to 4.16. These switch currents can be used
to find the switching losses in the MLI system.

59

Figure 4.10 a)

I a , b) S.F. SF 1 c) Switching current I SF 1 d) S.F. SF 2 e) Switching current

I SF 2

60

Figure 4.11 a)

I a , b) S.F. SF 3 c) Switching current I SF 3 d) S.F. SF 4 e) Switching current

I SF 4

Figure 4.12 a)

I b , b) S.F. SF 5 c) Switching current

I SF 6

61

I SF 5 d) S.F. SF 6 e) Switching current

Figure 4.13 a)

I b , b) S.F. SF 7 c) Switching current

I SF 8

62

I SF 7 d) S.F. SF 8 e) Switching current

Figure 4.14 a)

I c , b) S.F. SF 9 c) Switching current I SF 9 d) S.F. SF 10 e) Switching current

I SF 10

Figure 4.15 a) Switching current

I SF 1 b) pure switch current e) diode current

63

Figure 4.16 a) Switching current

I SF 2 b) pure switch current e) diode current

4.7 dSPACE 1104 Controller

The switching signals generated in MATLAB/Simulink real time environment are given to the
dSPACE 1104 controller (MPC8240processor) which is having inbuilt independent digital I/O
lines. So the switching signals of MATLAB/Simulink can be brought in real time with the 5V
voltage level.

Figure 4.17 dSPACE 1104 controller kit

64

The DS1104 R&D Controller Board is a standard board that can be plugged into a PCI slot of a
PC. The DS1104 is specifically designed for the development of high-speed multivariable digital
controllers and real-time simulations in various fields. It is a complete real-time control system
based on a 603 Power PC floating-point processor running at 250 MHz. For advanced I/O
purposes, the board includes a slave-DSP subsystem based on the TMS320F240 DSP
microcontroller. For purposes of rapid control prototyping (RCP), specific interface connectors
and connector panels (see below) provide easy access to all input and output signals of the board.
Thus, the DS1104 R&D Controller Board is the ideal hardware for the dSPACE Prototype
development system for cost-sensitive RCP applications.
The dSPACE control platform simplifies the programming task using library block set and
interfacing of control algorithm to run on processor and on-chip peripherals. To observe the
variables of a running real-time application, it is necessary to create a Control Desk layout with
instrument such as plotter, and connect the instrument to the variable to be observed.

Figure 4.18 dSPACE 1104 Control Desk

65

As discussed, the control desk offers wide range of instruments. We have used the data
acquisition instrument and the plotter to plot the simulated data. Also slider tool is also used to
vary the modulation index in the range of 0 to 1.
The following Figure 4.19 shows the line-to-line voltage generation on Control Desk. Three
different scope data are combined in the plotter to show the three phase line voltages on the same
screen.

4.19line-to-line voltage generation on control desk

The following Figure 4.20 shows the real time implementation of the multilevel inverter pulses
on CRO. Out of 20 digital I/O available, pin 0, 1, 2 and 4 are used. The pulses from MATLAB
are converted to Boolean data type and then the program is built on dSPACE 1104.

4.20Real time pulse generation on DSO

66

4.8 T.H.D. Analysis of Multilevel Inverter

Table 4.1
Modulaton Index Vs T.H.D. for 5-level Cascaded Multilevel Inverter
Modulation Index
1
0.9
0.8
0.7
0.6

Voltage THD %
25.22
25.37
27.85
28.3
29.3

Current THD %
2.47
2.49
2.5
2.51
2.52

The table 4.1 shows the variation of voltage and current THD for 5-level cascaded multilevel
inverter with variation in modulation index.
Table 4.2
Modulaton Index Vs T.H.D. for 5-level Diode Clamped Multilevel Inverter
Modulation Index
1
0.9
0.8
0.7
0.6

Voltage THD %
36.72
53.08
57.7
62.74
67

Current THD %
3.2
9.08
9.6
10.99
11.19

The table 4.2 shows the variation of voltage and current THD for 5-level diode clamped
multilevel inverter with variation in modulation index.
It is clearly seen from the above analysis that the cascaded multilevel inverter offers a lesser
THD variation with the changes in modulation index.
4.9 Comperison of Multilevel Converters
The multilevel converters can replace the existing systems that use traditional multi-pulse
converters without the need for transformers. For a three-phase system, the relationship between
the number of levels m, and the number of pulses p, can be formulated by p=6 (m1) . The
cascaded and diode clamped, both have the potential for application in high voltage, high power
system. The diode clamped inverter is most suitable for back-to-back intertie system operating as
a unified power flow controller. The other types may also be suitable for the bac-to-back intertie,
but they would require more switching per cycle and more advanced control techniques to
67

balance the voltage. The Cascaded multilevel inverters finds potential applications in adjustable
speed drives where the use of multilevel converters can not only solve harmonics and EMI
problems but also avoid possible high-frequency switching failures.
Table 4.3 compares the component requirements per phase leg among the both multilevel
inverter of m-level. All devises are assumed to have the same rating, but not necessarily same
current rating.
Table 4.3
Comparison of component requirements per leg of multilevel inverter
Converter Type
Main Switching devices

Diode clamped
(m1) 2

Cascaded
(m1) 2

Main Diodes

(m1) 2

(m1) 2

Clamping Diodes

(m1)(m2)

DC bus Capacitors

(m1)

(m1)/2

Balancing Capacitors

The cascaded inverter uses a full bridge in each level as compared with the half bridge version of
diode clamped type. The cascaded inverter requires the least number of components and has the
potential for utility interface applications because of its capabilities for applying modulation and
soft-switching technique.

CONCLUSION

68

The term multilevel begins with the three-level converter. Subsequently, several multilevel
converter topologies have been developed. The advantages of cascade multilevel inverters are
prominent for motor drives and utility applications. The cascade inverter has drawn great interest
due to the great demand of medium-voltage high-power inverters. The cascade inverter is also
used in regenerative-type motor drive applications. Recently, some new topologies of multilevel
inverters have emerged. This includes generalized multilevel inverters, mixed multilevel
inverters, hybrid multilevel inverters and soft-switched multilevel inverters. These multilevel
inverters can extend rated inverter voltage and power by increasing the number of voltage levels.
They can also increase equivalent switching frequency without the increase of actual switching
frequency, thus reducing ripple component of inverter output voltage and electromagnetic
interference effects.
In literature review this dissertation provides a brief summary of multilevel inverter circuit
topologies. Multilevel inverter can be applied to utility interface systems and motor drives. These
inverters offer a low output voltage T.H.D., and high efficiency and power factor. There are
many topologies available for multilevel inverter out of which cascaded and diode clamped
multilevel inverter are discussed briefly in this dissertation work. Multilevel inverter are suitable
for high voltage and high current applications also they offer higher efficiency because of the
devices can be switched at a low frequency.
In system development, it is seen that each MLI has its own mixture of advantages and
disadvantages and for any one particular application. Often, topologies are chosen based on what
has gone before, even if that topology may not be the best choice for the application. Diode
clamped and cascaded MLI are found most common topologies used for medium and high
voltage industrial applications. Multilevel converters can achieve an effective increase in overall
switch frequency through the cancellation of the lowest order switch frequency terms.
In result analysis, we have discussed output waveform of different types MLI and their carrier
based PWM modulation techniques. There are many modulation techniques for multilevel
inverters. But carrier based modulation technique is easy and efficient. Their harmonic analysis
is also discussed. T.H.D. of the five level cascaded and diode clamped multilevel inverters have
been calculated at different modulation index. For the real time implementation, dSPACE 1104 is
used as a main controller. dSPACE 1104 can be easily integrated with MATLAB/Simulink and
69

hence it is shown that the switching signals from MATLAB simulation can be used for the
prototyping actual hardware of MLI.
Following points are concluded from this dissertation.
1. Multilevel Inverter can provide better voltage and current waveform as compared to the
conventional classical inverters (two level).
2. Increase in number of level can give a very fine stepped waveform of voltage close to
sinusoidal voltage waveform.
3. Comparison between Cascaded MLI structure and Diode MLI structure shows better
performance of Cascaded MLI structure in terms of THD.
4. Generalized switching function is derived for 5 level MLI.
5. Increase in the number of level requires fast processor for the computation of switching
times for all the switches for real time application. In this work dSPACE 1104 controller
is used which considerably reduces the computational complexity and generates the
embedded code from the MATLAB/Simulation itself.
To summarize the results from this dissertation, it has been shown with simulations that
multilevel inverters can be used instead of two-level inverters to get lower THD in both output
voltage and current and also to lower the switching power losses. However, a higher number of
components must be used but these can be of a kind with lower voltage ratings, depending on the
number of voltage levels used in the multilevel inverter. It has also been shown that the Cascade
MLI in general, is the best choice of MLI when it comes to component requirements. Since it
was the voltage source MLI with the lowest number of components needed also the Cascade
MLI is among the MLIs that require the lowest voltage ratings of the switches.
Future Work
From the conclusion, the advantages with multilevel inverters over two-level inverters are clear.
If low disturbances or low switching power loss is wanted, multilevel inverters are certainly a
solution. Following are some points for the further future work.
1. Actual laboratory implementation of the cascade as well as diode clamped MLI.
2. Simulations on the Neutral-Point Clamped inverter with a voltage balancing modulation.
3. Multilevel and two-level inverter comparison on the basis of losses in the filter.

REFERENCES

70

[1] Andreas Nordvall, Multilevel Inverter Topology Survey, Thesis For The Degree Of
Master Of Science, Chalmers University of technology Gteborg, Sweden, 2011
[2] Fang Zheng Peng, Senior Member, IEEE, A Generalized Multilevel Inverter Topology
with Self Voltage Balancing, IEEE Transactions on Industry Applications, Vol. 37, NO. 2,
March/April 2001.
[3] Yuttana Kumsuwan, Suttichai Prem rudeep reechacharn, Member, IEEE, and Vijit
Kinnares, Member, IEEE, A Carrier-Based Unbalanced PWM Method for Four-Leg
Voltage Source Inverter Fed Unsymmetrical Two-Phase Induction Motor IEEE
Transactions On Industrial Electronics, Vol. 60, No. 5, May 2013
[4] Jun Mei, Member, IEEE, Bailu Xiao, Student Member, IEEE, Ke Shen, Student Member,
IEEE, Leon M. Tolbert, Fellow, IEEE, and Jian Yong Zheng, Modular Multilevel
Inverter with New Modulation Method and Its Application to Photovoltaic GridConnected Generator, IEEE Transactions On Power Electronics, Vol. 28, No. 11,
November 2013.
[5] Byoung-Kuk Lee, Student Member, IEEE, and Mehrdad Ehsani, Fellow, IEEE, A
Simplified Functional Simulation Model for Three-Phase Voltage-Source Inverter Using
Switching Function Concept, IEEE Transactions on Industrial Electronics, vol. 48, no. 2,
april 2001
[6] M. G. Hosseini Aghdam, S. H. Fathi, Modeling of Conduction and Switching Losses in
Three-Phase Asymmetric Multi-Level Cascaded Inverter, Proceedings of the 5th WSEAS
Int. Conf. on Power Systems and Electromagnetic Compatibility, Corfu, Greece, August
23-25, 2005 (PP 176-181)
[7] V. T. Somasekhar, K. Gopakumar, Senior Member, IEEE, M. R. Baiju, Krishna K.
Mohapatra, Student Member, IEEE, and L. Umanand, A Multilevel Inverter System for
an Induction Motor With Open-End Windings, IEEE Transactions On Industrial
Electronics, Vol. 52, No. 3, June 2005
[8] Leon M. Tolbert, Senior Member, IEEE, Fang Zheng Peng, Senior Member, IEEE, and
Thomas G. Habetler, Senior Member, IEEE, Multilevel Converters for Large Electric
Drives, IEEE Transactions On Industry Applications, Vol. 35, No. 1, January/February
1999
[9] Alessandro Luiz Batschauer, Student Member, IEEE, Samir Ahmad Mussa, Member,
IEEE, and Marcelo Lobo Heldwein, Member, IEEE, Three-Phase Hybrid Multilevel
Inverter Based on Half-Bridge Modules, IEEE Transactions On Industrial Electronics,
Vol. 59, No. 2, February 2012
71

[10] Surin Khomfoi, Nattapat Praisuwanna, Student Member, IEEE, Leon M. Tolbert, Senior
Member, IEEE, A Hybrid Cascaded Multilevel Inverter Application for Renewable
Energy Resources Including a Reconfiguration Technique, IEEE Transactions, 978-14244-5287-3/10
[11] P. Senthilkumar, M. Balachandran, N. P. Subramaniam, Cascaded H-Bridge Multilevel
Inverter Using SPWM International Journal of Advanced Research in Engineering and
Applied Sciences. ISSN: 2278-6252
[12] C.R. Balamurugan, S.P. Natarajan, and R. Revathy, Analysis of Control Strategies for
Diode Clamped Multilevel Inverter, International Journal of Innovation and Applied
Studies, Innovative Space of Scientific Research Journals, ISSN 2028-9324 Vol. 3 No. 1
May 2013, pp. 19-34
[13] Rajesh K. Ahuja, Lalit Agarwal, Pankaj Kumar, Simulation of Single Phase Multilevel
Inverters with Simple Control Strategy Using MATLAB, International Journal of
Advanced Research in Electrical, Electronics and Instrumentation Engineering, (An ISO
3297: 2007 Certified Organization) Vol. 2, Issue 10, October 2013
[14] Janyavula Deepthi , Dr S N Saxena , Study of Variation of THD in a Diode Clamped
Multilevel Inverter with respect to Modulation Index and Control Strategy, 2nd
International Conference and workshop on Emerging Trends in Technology (ICWET)
2011
[15] Dr. Muhammad H. Rashid, Power Electronics: Circuits, Devices, and Applications,
Pearson Education Third Edition, Electrical and Computer Engineering, University of
West Florida.

PAPER PUBLISHED DURING DISSERTATION WORK

72

1) Title: Simulation of Five Level Inverter with Sinusoidal PWM Carrier Technique Using
MATLAB/Simulink.
Journal Name: International Journal of Electrical Engineering (IJEE)
Volume No: 07
Issue No.: 03 (January 2015)
ISSN No: 0974-2150

TRAINING ATTENDED DURING DISSERTATION WORK

1) Title: Short-term Training on Energy Storage
Venue: National Institute of Electronics and Information Technology, Aurangabad,
Maharashtra
Duration: 11th May 2015 to 15th May 2015
2) Title: National level workshop series on Research Perspectives on Solar PV System
(Basics, Design, Simulation and Application)
Venue: PSG College of Technology, Coimbatore, Tamil Nadu.
Duration: 26th March 2015 to 29th March 2015
3) Title: National level workshop on Advances in Power Electronics and Applications
Venue: AISSMS College of Engineering, Pune, Maharshtra
Duration: 27th February 2015 to 28th February 2015
73

4) Title: National level workshop on Signal Processing

Venue: Samrat Ashok Technological Institute, Vidisha, Madhya Pradesh.
Duration: 4th December 2014 to 6th December 2014

ACKNOWLEDGEMENT

Completion of my dissertation work is a task which could not be accomplished

without cooperation and help from my guide. At the outset, I wish to express my deep
sense of gratitude to my guide and Head of the Department Dr. A. G. Thosar for her
guidance and constant encouragement during the dissertation work, without which it
would not have been possible.
I am also very much grateful to Principal, Dr. P. S. Adwani who has been a
constant source of inspiration. I am very much thankful to all my faculty members whose
presence always inspires me to do better.
Furthermore, I thank my friends for their support and friendly environment.
Finally, I would like to thank my whole family, particularly my parents for their
love and patience.

74

Punit L. Ratnani

75