BMFA 3313 - Guidelines to solutions

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Q1. Step 1: Controller to be designed is PI

Step 2: Select a pole at origin and a zero close to origin to complete the PI controller.
Step 3: Compute the steady-state error for the uncompensated system using K = 73.09.
Step 4: Compute the steady-state error for the compensated system using K = 72.23.
Steady-state error here should be zero.
Step 5: With information on uncompensated and compensated , calculate both compensated
and uncompensated settling times and peak times.

Q2. Step 1: Realised that this is a type 0 system.

Step 2: Calculate Kp as the static error constant. Use gain of 7.5
Step 3: Use formula for s.s.e using Kp.
Step 4: Design a PI controller by selecting a pole at the origin and a zero close to the origin.

Q3. Step 1: Controller to be designed is PD compensator.

Step 2: Get the damping ratio for 4.3% overshoot.
Step 3: Find the current settling time using current pole location. Ts 4 / 2.32 .
Step 4: Identify the required settling time by dividing old settling time by 2.
Step 5: Locate the new point (sigma) from result of step 4.
Step 6: Solve for d of the new point using tangent of the angle (cos =zeta).
Step 7: Upon solving the new point, get the summations of all poles and zero to this point.
Whatever the different of this angle with 180 is the angle contributed by the PD
compensator.
Step 8: Construct the necessary triangle to locate zc.

Q4. Step 1: Solve for zeta for 20% OS.

Step 2: Get the phase margin for this zeta.
Step 3: Identify the frequency on the phase plot that would give this phase margin.
Step 4: Read the gain at this frequency.
Step 5: Convert the absolute value of this gain to dB. This is the gain K.

BMFA 3313 - Guidelines to solutions

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Q5. Step 1: This is a lag compensator design.

Step 2: Find the gain K that yields kv = 5.
Step 3: Identify the frequency that gives a PM = 40 + 10
Step 4: Identify the magnitude at this frequency.
Step 5: The magnitude of the lag compensator must be a negative of the magnitude identified in
Step 4.
Step 6: Moves 1 decade lower from this frequency. This is zc.
Step 7: Draw a line with a slope of -20Db/dec from this point and identify the intersection points
frequency with the 0 dB line. The frequency identified is pc.
Step 8: Complete the lag compensator design by adjusting for DC gain value (pc / zc).

Q6. Step 1: Design a lead/lag compensator.

Step 2: Get the required BW of the system from Tp.
Step 3: The designed freq. equals 0.8 of this bandwidth, get max .
Step 4: From % OS value, get the damping ratio.
Step 5: Calculate the desired PM.
Step 6: From Kv, get the gain K values.
Step 7: Identify the current phase margin at max .
Step 8: Identify max that is the difference between desired and actual PM with correction.
Step 9: Calculate for .
Step 10: Then get value of .
Step 11: Construct the lag compensator, zc is 1 dec lower than max . This is 1/T2
Step 12: Get pc that is (1/ ) (1/T2).
Step 13: Correct for DC gain unity.
Step 14: Design Lead, zc equal 1/T1, get this from knowledge of max and .
Step 15: Design for pc. that is ( ) (1/T1).
Step 16: Correct for DC unity gain.
Step 17: Construct the overall TF of lag + lead compensators.

BMFA 3313 - Guidelines to solutions

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Q7. Step 1: This is a lag compensator design.

Step 2: Simplify the block diagram.
Step 3: Get the value of K from information on static error constant. You know which error constant
from step 2.
Step 4: Adjust the magnitude plot in Figure 7 that was plotted for K=1.
Step 5: From %OS get the damping ratio value. Then find the PM requirement with correction.
Step 6: Identify the frequency of this PM.
Step 7: Identify the magnitude at this frequency.
Step 8: The magnitude of the lag compensator must be a negative of the magnitude identified in
Step 9: Moves 1 decade lower from this frequency. This is zc.
Step 10: Draw a line with a slope of -20Db/dec from this point and identify the intersection points
frequency with the 0 dB line. The frequency identified is pc.
Step 11:Complete the lag compensator design by adjusting for DC gain value (pc / zc).

Q8. This is a lead lag compensator design.

Steps are similar to Q6.
(c) Results showed that the magnitude plot at the higher frequencies has been reduced to enhance
stability. The PM obtained is as desired.

Q9.

Step 1: This is a lead compensator design.

Step 2: From Tp, identify the BW desired.
Step 3: From %OS values, get the damping ratio.
Step 4: From the zeta value, get the desired PM.
Step 5: Calculate gain K value from kv. To do this, simplify the block diagram.
Step 6: Identify current PM from Figure 11.
Step 7: Identify the phase required as max .
Step 8: Calculate for .
Step 9: Get the magnitude in dB for the compensator.
Step 10: Identify the frequency where the magnitude of the uncompensated system is negative of
that identified in step 9. This is max .
Step 11: Next, calculate 1/T from max . This is zc.
Step 12: Get pc from (1/ ) (1/T).
Step 13. Adjust for DC unity gain and construct the complete transfer function.