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VLSI Di
Digital
it l Circuits
Ci
it
Spring 2011
Lecture 12: Logical Effort
-11
= (W/Lp)/(W/Ln)
tpLH
4.5
tpHL
of 2.4 (= 31 k/13 k)
gives symmetrical
response
tp
of 1.6
1 6 to 1
1.9
9 gi
gives
es
optimal performance
3
3.5
3
1
= (W/Lp)/(W/Ln)
Out
Cg,1
1
CL = 8 Cg,1
Heads up
This lecture
z
Logical Effort
- Reading assignment textbook pp251-257, and handout
Next lecture
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History
Gain-based synthesis
y
based on Logical
g
effort
z
Inverter Delay
where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the
gate
f: effort delay
p: parasitic delay
f=gh
g: logical effort
h: electrical effort = Cout/ Cin (the ratio of
Cin
Logic
g
Gate
Cout
Logical Effort
z Complexity of logic function (Invert, NAND, NOR, etc)
z Define inverter has logical effort = 1
z Depends only on topology not transistor sizing
Electrical Effort
z Ratio of output capacitance to input capacitance Cout/Cin
Parasitic Delay
z Intrinsic delay
z Independent of transistor sizes and output load
Example
Estimate
E
ti t the
th delay
d l off an inverter
i
t driving
d i i 4 identical
id ti l
inverter: (FO4)
g=
h=
p=
d=
Example
T t l path
Total
th delay
d l th
through
h a combinational
bi ti
l llogic
i bl
block
k
tp = dj = pj + hj gj
the minimum
th
i i
d
delay
l th
through
h th
the path
th d
determines
t
i
th
thatt each
h stage
t
should bear the same gate effort
h1g1 = h2g2 = . . . = hNgN
g1=10/3 g2=1
1 6/3 g2=5/3
2 /3
g1=6/3
g1=4/3 g2=5/3 g3=4/3 g4=1
Isolating fan-in
f
f
from
fan-out
f
using buffer
ff insertion
CL
CL
Questions
d = gh+p
Cp
Cout
g
Sp11 CMPEN 411 L12 S.20
Parasitic Delay
CgateP
RonP
RonN
CgateN
These scale
Th
l with
ith ttransistor
i t width
idth
so it is independent of transistor
sizes
For inverter:
CdrainP
Ch
Characterize
t i process speed
d with
ith single
i l d
delay
l parameter:
t
~= 15 ps for 0.18um
Path
logical effort, G = gi
Path
Parasitic
P
iti
Path
D=
D
d
delay,
l
P = pi
effort, F= fi = gi hi
F+P
C
Consider
paths that branch:
GH
h1
h2
= GH?
15
90
5
15
90
No! Consider
C
paths that branch:
=1
= 90 / 5 = 18
GH
= 18
h1
= (15 +15) / 5 = 6
h2
= 90 / 15 = 6
= g1g2h1h2 = 36 = 2GH
15
90
5
15
90
Multistage Networks
Path electrical effort: H= Cout/Cin
Path logical effort: G = g1g2g
gN
Branching effort: B = b1b2bN
P th effort:
Path
ff t F=
F GBH
Path delay D = F+P=GBH+P
C
Compute
the path effort:
ff
F = GBH
G
Sketch the p
path with this number of stages
g
Cg,1 = 1
16
Cg,1 = 1
1
tp
64
65
18
15
2.8
15.3
CL = 64 Cg,1
4
CL = 64 Cg,1
8
2.8
Cg,1 = 1
CL = 64 Cg,1
8
22.6
CL = 64 Cg,1
Summary
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