eGaN FET DATASHEET

EPC2016C

EPC2016C Enhancement Mode Power Transistor

VDSS , 100 V
RDS(on) , 16 mW
ID , 18 A

NEW PRODUCT

EFFICIENT POWER CONVERSION

HAL

Gallium nitride is grown on silicon wafers and processed using standard CMOS equipment leveraging the infrastructure that has been developed over the last 55 years. GaNs exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure
and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that
can handle tasks where very high switching frequency, and low on-time are beneficial as well as
those where on-state losses dominate.

EPC2016C eGaN FETs are supplied only in

passivated die form with solder bars

Maximum Ratings
VDS
ID
VGS
TJ
TSTG

Drain-to-Source Voltage (Continuous)

100

Drain-to-Source Voltage (up to 10,000 5ms pulses at 150 C)

120

Continuous (TA = 25C, JA = 13.4)

18

Pulsed (25C, Tpulse = 300 s)

75

Gate-to-Source Voltage

Gate-to-Source Voltage

-4

Operating Temperature

-40 to 150

Storage Temperature

-40 to 150

Applications
High Speed DC-DC conversion
Class-D Audio
High Frequency Hard-Switching and
Soft-Switching Circuits

Benefits
Ultra High Efficiency
Ultra Low RDS(on)
Ultra low QG
Ultra small footprint

V
C

Static Characteristics (TJ= 25C unless otherwise stated)

PARAMETER

TEST CONDITIONS

MIN
100

TYP

MAX

UNIT
A

BVDSS

Drain-to-Source Voltage

VGS = 0 V, ID = 300 A

IDSS

Drain Source Leakage

VGS = 0 V, V DS = 80 V

25

150

Gate-Source Forward Leakage

VGS = 5 V

0.5

Gate-Source Reverse Leakage

VGS = -4 V

0.25

0.15

Gate Threshold Voltage

VGS = VGS, ID = 3 mA

1.4

2.5

16

IGSS
VGS(th)

0.8

RDS(on)

Drain-Source On Resistance

VGS = 5 V, ID = 11 A

12

VSD

Source-Drain Forward Voltage

IS = 0.5 A, VGS = 0 V

1.8

mA

All measurements were done with substrate shorted to source.

Thermal Characteristics
TYP
RJC

Thermal Resistance, Junction to Case

C/W

RJB

Thermal Resistance, Junction to Board

C/W

RJA

Thermal Resistance, Junction to Ambient (Note 1)

69

C/W

Note 1: RJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.

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eGaN FET DATASHEET

EPC2016C
Dynamic Characteristics (TJ= 25C unless otherwise stated)

PARAMETER

TEST CONDITIONS

TYP

MAX

360

420

210

310

Reverse Transfer Capacitance

3.2

4.8

RG

Gate Resistance

0.4

QG

Total Gate Charge

3.4

CISS

Input Capacitance

COSS

Output Capacitance

CRSS

MIN

VGS = 0 V, V DS = 50 V

QGS

Gate-to-Source Charge

QGD

Gate-to-Drain Charge

QG(TH)

Gate Charge at Threshold

QOSS

Output Charge

QRR

Source-Drain Recovery Charge

UNIT
pF

4.5

1.1

VDS = 50 V, ID = 11 A

0.55

nC

0.7
VGS = 0 V, V DS = 50 V

16

24

All measurements were done with substrate shorted to source.

Figure 1: Typical Output Characteristics at 25C

Figure 2: Transfer Characteristics

75

75

45

30

VGS = 5 V
VGS = 4 V
VGS = 3 V
VGS = 2 V

15

50

RDS(on) Drain to Source Resistance (m)

ID Drain Current (A)

60

0.5

1.5

VDS Drain-to-Source Voltage (V)

2.5

ID = 8 A
ID = 12 A
ID = 20 A
ID = 40 A

20

10

2.5

3.5

VGS Gate-to-Source Voltage (V)

30

50

30

45

Figure 3: RDS(on) vs. VGS for Various Currents

40

4.5

VDS = 3 V

15

RDS(on) Drain to Source Resistance (m)

ID Drain Current (A)

60

25C
125C

0.5

1.5

2.5

3.5

VGS Gate-to-Source Voltage (V)

4.5

Figure 4: RDS(on) vs. VGS for Various Temperatures

25C
125C

40

ID = 11 A

30

20

10

2.5

EPC EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |

3.5

VGS Gate-to-Source Voltage (V)

4.5

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eGaN FET DATASHEET

EPC2016C

Figure 5a: Capacitance (Linear Scale)

600

Figure 5b: Capacitance (Log Scale)

400

Capacitance (nF)

Capacitance (nF)

1000

COSS = CGD + CSD

CISS = CGD + CGS
CRSS = CGD

500

300
200

100
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD

10

100
0

20

40

60

80

100

20

40

VDS Drain-to-Source Voltage (V)

Figure 6: Gate Charge

36

5
ID = 11 A
VDS = 50 V

4
3.5
3
2.5
2
1.5
1
0.5
0

0.5

1.5

QG Gate Charge (nC)

2.5

24
18
12
6

Figure 8: Normalized On Resistance vs. Temperature

1.5

2.5

3.5

VSD Source-to-Drain Voltage (V)

4.5

Figure 9: Normalized Threshold Voltage vs. Temperature

ID = 11 A
VGS = 5 V

1.3

1.5
1.4
1.3
1.2
1.1
1

ID = 3 mA

1.2
1.1
1
0.9
0.8
0.7

0.9
0.8

1.4

Normalized Threshold Voltage

Normalized On-State Resistance RDS(on)

1.6

100

25C
125C

0.5

3.5

1.8
1.7

80

Figure 7: Reverse Drain-Source Characteristics

30

ISD Source to Drain Current (A)

VGS Gate to Source Voltage (V)

4.5

60

VDS Drain-to-Source Voltage (V)

25

50

75

100

125

TJ Junction Temperature ( C )

150

0.6

25

50

75

100

125

150

TJ Junction Temperature ( C )

All measurements were done with substrate shortened to source.

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eGaN FET DATASHEET

EPC2016C
12

Figure 10: Gate Current

25C
125C

IG Gate Current (mA)

10
8
6
4
2
0

VGS Gate-to-Source Voltage (V)

Figure 11: Transient Thermal Response Curves

Junction-to-Board
ZJB, Normalized Thermal Impedance

Duty Factors:
0.5

0.2
0.1 0.1
0.05

T
PDM

0.02
0.01 0.01

Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZJB x RJB + TB

Single Pulse
0.001
10-5

tp

10-4

10-3
10-2
tp - Rectangular Pulse Duration [s]

10-1

10

Junction-to-Case
ZC, Normalized Thermal Impedance

Duty Factors:
0.5
0.2
0.1 0.1
0.05
0.02
0.01 0.01
0.001

T
PDM

Notes:
Duty Factor = tp/T
Peak TJ = PDM x ZJC x RJC + TC

Single Pulse

0.0001
10-5

tp

10-4

10-3
10-2
tp - Rectangular Pulse Duration [s]

10-1

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10

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eGaN FET DATASHEET

EPC2016C

Figure 12: Safe Operating Area

100

I D- Drain Current (A)

10
limited by RDS(on)
Pulse Width
100 ms
10 ms
1 ms
100 us

0.1

0.1

10

100

VDS - Drain-Source Voltage (V)

TJ = Max Rated, TC = +25C, Single Pulse

TAPE AND REEL CONFIGURATION

4mm pitch, 8mm wide tape on 7 reel

Loaded Tape Feed Direction

Die
orientation
dot

7 reel

Gate
solder bar is
under this
corner

Die is placed into pocket

solder bar side down
(face side down)

EPC2016C (note 1)

Dimension (mm) target min

a
b
c (see note)
d
e
f (see note)
g

8.00
1.75
3.50
4.00
4.00
2.00
1.5

7.90
1.65
3.45
3.90
3.90
1.95
1.5

max

8.30
1.85
3.55
4.10
4.10
2.05
1.6

Note 1: MSL1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.

DIE MARKINGS

2016C
YYYY
Die orientation dot
Gate Pad solder bar
is under this corner

ZZZZ

Part
Number
EPC2016C

Laser Markings
Part #
Marking Line 1

Lot_Date Code
Marking line 2

Lot_Date Code
Marking Line 3

2016

YYYY

ZZZZ

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eGaN FET DATASHEET

EPC2016C

DIE OUTLINE

Solder Bar View

f
X4

d
X2

DIM
3

A
B
c
d
e
f
g

MIN

MICROMETERS
Nominal

MAX

2076
1602
1379
577
235
195
400

2106
1632
1382
580
250
200
400

2136
1662
1385
583
265
205
400

g
X3

SEATING PLANE

RECOMMENDED
LAND PATTERN

815 Max

100 +/- 20

(685)

Side View

The land pattern is solder mask defined.

Pad no. 1 is Gate;

(units in m)

Pads no. 3, 5 are Drain;

Pads no. 4, 6 are Source;
Pad no. 2 is Substrate.

X3

1362

560
X2

2106

180

X4
180

Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to
improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit
described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN is a registered trademark of Efficient Power Conversion Corporation.
U.S. Patents 8,350,294; 8,404,508; 8,431,960; 8,436,398; 8,785,974; 8,890,168; 8,969,918; 8,853,749; 8,823,012

EPC EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2015 |

Information subject to
change without notice.
Revised September, 2015

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