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Study of Non-Conventional Instrument

Transformer and IEC61850 impact on Current

Differential Protection
K. L., Shenxing

s., X. Dong, Senior Member, IEEE, and Z. Bo

Abstract--Non Conventional Instrument Transformer (NCIT)

and IEC 61850 are crucial technologies in digital substations. But
they bring some new uncertainties to protection IEDs, especially
the time synchronization issue in current differential protection.
The paper analyzes the time delay of transferring sampled values
from NCIT to current differential relay in NCIT and IEC61850
based digital substation, then finds out the delay-nondeterministic problem, at last presents a novel current
differential protection scheme by using Phase-Locked Loops
(PLL ) technology.
Index Terms-- IEC 61850, MU, NCIT, PLL, time

URRENTLY, digital substation is a headline to utilities

and vendors. Digital substation covered all aspects, such
as CT/VT, breaker, transformer, protection, control,
communication, software development and application [1-3].
Substation automation system (SAS), implemented using
intelligent electronic devices (IEDs)
and network
communication technologies, could facilitate the effective
substation monitoring, local & remote control, protection,
primary equipment condition monitoring and many other
functions that couldn't be easily realized with conventional
protection and control devices. IEC 61850 -'''Communication
networks and systems in substations" is the latest international
standard on substation automation communication series. The
standard consists of the protocol of digital interface between
IEDs, the adoption of which will increase the technical merit
of substation automation system. It can not only improve the
safety stability operation level of substation automation
system, reduce drain on manpower and material resources in
inspection and maintenance, but also achieve the
interoperability in the whole system.
Non Conventional Instrument Transformer (NCIT) offers
This work was supported by the National Natural Science Foundation of
China (Grant Nos.50077011 and 50377019) and the National Basic Research
Program of China ("973" Project) (Grant No.2004CB217906).
Kun Liu, Shenxing Shi and Xinzhou Dong are with the State Key Lab of
Control and Simulation of Power System and Generation Equipments,
Department of Electrical Engineering, Tsinghua University, Beijing 100084
ssx99(~)mails tsinghua. edu. cn,
Zhiqian Bo is with AREVA T&D Automation, Stafford ST 17 4LX UK (email:

978-1-4244-2218-0108/$25.00 2008 IEEE.

many advantages over the conventional instrumental

transformers, such as immune to electromagnetic noise,
rationalization of electrical insulation, and extension of
dynamic ranges and frequency bands of the measured signals,
therefore to achieve higher performance, higher compactness
and higher reliability of instrument transformers. The NCIT is
also developed with digital interface to IEDs, which is
supported by IEC 61850 [4].
MU (Merging Unit) will be placed between NCIT and
protection IEDs [5]. This equipment can receive the sampled
value from NCIT, and output data to protection IEDs in
accordance with IEC 61850 with a high speed data processing.
A simple example of linked MU and protection lED is shown
as Fig. 1.

Un. Protection

............. ,


.. :~

Fig.!. NCIT, MU and Protection lED

The introduction of NCIT and IEC 61850 accelerates the

digitalization process in substation, but brings some new
uncertainties to protection IEDs, such as current differential
protection. As well known, IEC 61850 is the standard focusing
on the communication in local substation, the communication
end-to-end (ETE) time delay requirements are applicable to
the correct performances of native IEDs. Current differential
protection adopts Kirchhoff s Law based on the fault current
information at both terminals of a protected device, such as
transmission lines. The two current differential relays (CDR)
are installed in different substations.

1- _


- ' .AI"




Fig. 2. Current differential protection between two different kinds of


It is well known that time synchronization is one of the

most important issues in current differential protection, the
fault current information at both terminals must be accurately
synchronized to enable differential algorithm to perform. But
the presence of local area network (LAN) between MU and
protection lED results variable time delay that brings
considerable difficulties to synchronization between two
current differential relays in both ends of the protected line
section. Especially in the process of popularization of digital
substations, it is possible to implement the current differential
protection between two different kinds of substation, one is
digital substation and the other is conventional one as shown
in Fig. 2.
Currently, accurate GPS timing information has been
employed to implement synchronous sampling in CDR to
synchronize the sampled values [6]. MU has realized the
synchronization of native current and voltage information, but
time synchronization between MU and protection lED has not
been considered because relative low requirements of time
effectiveness. The output message from MU has not been
precisely time tagged by GPS timing information [7].
Time synchronization is urgent to be solved in current
differential protection based on NCIT and IEC 61850. The
paper analyzes the time delay of transferring sampled values
from NCIT to current differential relay in accordance with
IEC 61850. Due to delay-non-deterministic problem existing
in LAN, the paper puts fonvard a novel method based on
Phase-Locked Loops (PLL) technology to implement the time
synchronization between MU and protection lED.
There are breaker lED, merging unit (MU), and combined
protection and control (P&C) lED. In the SAS, those IEDs
provide the following general functions. The MU first
processes and combines the signals from field CT and VT.
Then it transmits the digital voltage and current output to the
process bus (a high speed field Ethernet bus). The breaker
lED, which not only controls the breaker's open/close but also
monitors the state and condition of the circuit breaker,
receives the trip/close command from the P&C IEDs and
sends state change event to corresponding protection IEDs

through the process bus. The P&C lED, a universal device,

integrates the protection & control functionalities for the bay
unit it serves in the substation.
The IEDs shall follow the communication stack specified in
IEC 61850. According to IEC 61850-5 and IEC 61850-8,
messages are classified into 7 categories. The 7 types of
messages are mapped into different communication stacks
because of different performance requirements as shown in
Fig. 3.

=: J


OSI rive Lay~r \todd















thcmeI (ISOIIEe 8802-3)



Fig. 3. OSI five layer model

According to the IEC 61850-5, the message transmission

time requirements for SAS network must be ensured under
any operating conditions and contingencies inside the
substation. The raw data messages (Sampled Values, SAV,
type 4) and GOOSE messages (type 1) are time critical and
therefore directly mapped to low-level Ethernet layer. This
gives the advantage of improved performance for real time
messages by shortening the Ethernet frame (no upper layer
protocol overhead) and reducing the processing time. In
addition, the quality of service in link layer is provided by
priority tagging according to IEEE 802.1 Q. This is to
distinguish the time critical messages (type 1 and type 4) from
the other low time requirement messages and make sure that
tinle critical messages have the priority to be transmitted
firstly inside the substation network.

Re uirements/ms
<3 or <10

However, the message transmission time between two

IEDs in different substations is not specified, which is a
critical issue to be considered in current differential protection.

A. Scheme ofCurrent Differential Protection

One scheme is indicated as Fig. 4 and SAV messages (type
4) are chosen to be discussed. Two current differential relays
(CDR) are placed in two different digital substations. The

target is to implement the advanced line differential protection

scheme based on NCIT. The scheme mainly consists ofNCIT,
MU and protection IEDs in each digital substation. As shown
in Fig. 4, SAV messages according to IEC 61850 from
merging unit can be transmitted to CDR through Ethernet.
As well known, time synchronization is one of the most
important issues in current differential protection which adopts
Kirchhoff's Law. The fault current information at both
terminals must be accurately synchronized to enable
differential algorithm to perform. But in the process of data
transmission, time delay is hard to avoid and time
compensation is essential. But delay-non-deterministic
problem brings inconvenience to fixed time compensation,
which is discussed as follows.

B) Definition of data transmission time

The complete transmission of a message includes necessary
handling in both ends. The time counts from the moment the
sender puts the data content on top of its transmission stack up
to the moment the receiver extracts the data from its
transmission stack. The time requirement is applicable for the
complete transmission chain as indicated in Fig. 5 [5]. In the
proposed scheme, PD 1 represents MU and PD2 represents
Transfer time,

'a + 'b + 'e;




. processor

Fig. 5. Data Transmission Time Definition

Fig. 4. Constitution of data transmission time delay

As shown in Fig. 4, the time delay during the process of

data transmission in the proposed scheme can be generally
divided into the following parts:
t1: data processing time in NCIT, which is determined by
the speed of obtaining current information in NCIT;
t2: data processing time in MU, which lies on the
processing speed of MU. The sampled values will be
converted into another form followed by IEC 61850;
t3: data transmission time between MU and CDR;
t4: data transmission time between CDRs placed in both
line ends; and it includes the data processing time in CDR.

B. Analysis ofData Transmission Time and Delay-nondeterministic

In these parts mentioned above, we will put emphasis on
the data transmission time between MU and CDR (t3) in which
delay-non-detelministic problem mainly occurs.
A) Delay-non-deterministic in Ethernet
In communication network of digital substation, delay-nondeterministic problem refers to that the message could not be
transmitted reliably in a divinable time range. The time delay
discussed in this paper refers to end-to-end (ETE) time delay,
which is the time from a fixed message sent by the sending
point to it received by the receiving point. Message-lost is
considered as infinite time delay, so it is defined as a
particular delay-non-detenninistic problem.
The Ethernet in substation must satisfy the requirement for
the confinnation of the time delay in the most rigorous
application such as GOOSE and SAV messages.

t a refers to sending process delay of communication

processor in sending point. It means the time of the message
from the application layer to the physical layer. t c refers to
receiving process delay of communication processor in
receiving point. It means the time of the message from the
physical layer to the application layer. They generally include
protocol packaging of sending point, the process of CPU
pointer execution, data copy, queue delay of sending buffer,
accordingly, queue delay of receiving point, the time of
protocol package resolution, pointer process and data copy.
tb is the network transfer time including waiting time and
time used by routers and other devices that are parts of the
complete network. It is constituted with three delay parts.
(1) Sending time delay
Sending time delay ~t1 refers to the time from that the
sending point begins to send message with the first bit in the
communication link to that it sends the message with the last
bit, which is determined by the length of message and the rate
of data transmission. It is ~t1=Lf/R, in which Lf nleans the
length of the message (the unit is bit) and R means the
bandwidth (the unit is bit/s).
(2) Spread time delay
Spread time delay ~ t2 refers to the time from that the
sending point begins to send message with the first bit in the
communication link to that this bit arrives the receiving point,
which is determined by the transmission distance and spread
velocity. It is ~t2=DslV, in which D s indicates the transmission
distance of the link (m) and V indicates the spread velocity

(3) Queue time delay

Queue delay time ~ t3 refers to the process time that the data
store and transmit in the exchange point, which is determined
by traffic in network at that moment.
In Ethernet ring with switches, the formula of queue time
delay (without the overflow of the queue) is:



= L(96 + Lk)t


N q is the frame number in the switch buffer, '"96" refers to

the bit number of fioame interval regulated by Ethernet. L k is
the length of K frame message (bit), t is the transmission time
of one bit. N q is a variable number that can not be determined
at an appointed time. If too many frames have entered into the
~t3 determines that the whole data transmission time
becomes a variable value which can not be compensated as a
constant one.
For data transmission of SAV messages, IEC 61850-9-2
LE version provides two different control blocks MSVCBO 1
and MSVCB02, which are chosen based on different sampling
rates. If the transmission of 80 samples per nominal line cycle
is available, the MSVCBO 1 applies, else if the transmission
with 256 samples, the MSVCB02 will be used. Based on the
concept above, the refreshing frequency and the sampling rate
must be the same to implement real time transmission.
Different sampling rates will determine the number of
Application-Service Data Unit (ASDU) in one Application
Protocol Data Unit (APDU). MSVCBOI block will control the
transmission of 80 samples per cycle, in which the frame is
composed of one ASDU; MSVCB02 block will control the
transmission of 256 samples per cycle, in which the frame is
composed of 8 ASDU.
We take the frame with one ASDU controlled by
MSVCBOI block as an example; consider the Ethernet frame
gap as 96 bits, size of Ethernet stuff as 38 Bytes including the
header, source address, destination address, CRC information,
size of ASN.l fix header as 7 Bytes and size of 1 ASDU &
ASN.l tag as 114 Bytes, sum up these information, the size of
the frame can be calculated as 171 Bytes. If the Ethernet
adopts optical fiber transmission system IEEE 802.3 100BaseFX and 100Mbit/s Ethernet switch, considering the
transmission distance as a constant (100m), we can get the
value of ~tland ~t2
tlt 1 =L f / R =- - -6 =13.6811('
100x 10

If the number of MU linked with the Ethernet switch is
four, N q=3, if only SAY messages exist in the flow of the
Ethernet and the length of each SAV message is Fixed as 171
Bytes, so L k= 1368. The capacity of the network is 100Mbit/s,
so t=O.O 1J.lS.
I1t 3 =3x(96+ 1368)xO.Olxl0-6 =43.92,us
tlt 2


2 /

V =- -8 = 0.5f.1S

In this condition, If we select MSVCB02 for

control block, the size of one frame can be calculated as 988
Bytes and The calculation above is just based on
an ideal condition which is not considering other
configurations of network.
C) Summary of Delay-non-deterministic in Ethernet
Reasons of delay-non-deterministic problem are exhibited
as follows:

(1) There are many categories of information sources in the

digital substation communication system, the collision of the
information and message resending are not avoided. That
directly leads to the delay-non-deterministic problem.
(2) All the switches and hubs in the network have their own
sending and receiving buffer, if the rate of message arriving is
close to the rate of message processing and retransmitting, the
message will be accumulated in the buffer, that leads to the
queuing phenomenon. So the message transmission will be
badly delayed, even there will be message-lost when the
buffer is overflo\ved.
(3) Delay-non-deterministic problem is not only related to
the bandwidth and buffer size of switches, but also to the
processing capacity of the linked IEDs.
(4) At the present stage, the net is high-speed oriented and
message-lost grows more common in the case of deficiency of
processing capacity and the inadequate buffer size.
C. Impact on Synchronization ofcurrent differential protection
In current differential protection, synchronous sampling
which is based on GPS timing information has been used to
implement the time compensation. The current differential
communication is carried out over a high-level data link
control channel, using dedicated serial communications
controller hardware to handle the task [6].
However, end-to-end (ETE) time delay between MU and
CDR has the characteristic of delay-non-deterministic; many
simulations have shown that the data transmission time
between MU and CDR is a floating value in the case of
different Ethernet settings [8]. In addition, if we consider the
time delay derived from Anti-Aliasing analog filter, ADC
processing and Digital output filter in MU, h (data processing
time in MU) solely will exceed Ims [7].
The fixed time compensation is deficient to solve delaynon-deterministic problem, the most efficient method is that
MU provides accurate GPS timing information to each SAV
message. In addition, the resolution of CDR time tag must be
improved. So operating criterion must take adjustment of
accurate time in consideration. Those will take enormous
changes in hardware.
The PLL method mentioned below is a simple way to
implement the time synchronization between MU and CDR.

A PLL is a device which causes one signal to track another

one. It keeps an output signal synchronizing with a reference
input signal in frequency as well as in phase. More precisely,
the PLL is simply a servo system, which controls the phase of
its output signal in such a way that the phase error between
output phase and reference phase reduces to a minimum [9].





gain first-order loop. The lock-in limit of a first-order loop is

equal to the loop gain. We argue here that a higher order loop
has nearly the same lock limit. The lock-in range t:.roL can be
approximately estimated as

Fig. 6. Linear model of the phase-locked loop

~OJL ~ KdKvF(oo)



Fig. 7. Active filter

The functional block diagram of a PLL is shown as Fig. 6,

which consists of a phase detector (PD), a loop filter (LPF),
and a voltage-controlled oscillator (VCO).
LPF is the key component whose order and parameters
determine the performance and stability of the whole function.
If LPF is an active filter shown as Fig. 7, the closed-loop
transfer function of the PLL is given by

H(s) =

KdKv(S'l"2+ 1)/



For convenience in description, (5) can be rewritten into the

H(s) = 2 2s mn + m~ 2




Fig. 8. Ranges of the dynamic limits of a PLL

Acquisition of frequency in PLL is more difficult and

slower, and requires more design attention than phase
acquisition. The self-acquisition of frequency is known as
frequency pull-in, or simply pull-in, and the self-acquisition of
phase is known as phase lock-in, or lock-in.
Because of synchronous sampling between both CDRs, this
PLL technology can be solely used between CDR and MU at
the NCIT side.

+ OJn


In which ron is the natural frequency of the loop and Sis the
damping ratio. The relevant parameters for active filter are

mn=( K~~d
S= ~(K~~d



'l"2 =

R2 C

Define the DC gain of the loop as



A large value of K o is usually required for achieving a good

performance of the loop. Define the hold-in range of a loop as
~roH=Ko. If the input frequency is sufficiently close to the
VCO frequency, a PLL locks up with just a phase transient;
there is no cycle slipping prior to lock. The frequency range
over which the loop acquires phase to lock without slips is
called the lock-in range of the PLL. In a first-order loop, the
lock-in range is equal to the hold-in range, but for the second
higher order loops, the lock-in range is always less than the
hold-in range. Besides, there is a frequency interval, smaller
than the hold-in interval and larger than the lock-in interval,
over which the loop will acquire lock after slipping cycles for
a while. This interval is called the pull-in range. Their
relations are indicated in Fig. 8. To ensure stable tracking, it is
common practice to build loop filters with equal numbers of
poles and zeros. At high frequencies the loop is
indistinguishable from a first-order loop with gain
K=KdKyF(00). As a fair approximation, we can say that the
higher order loop has the same lock-in range as the equivalent-

Fig. 9. Synchronization between MU and CDR

MU sends frames according to IEC61850 at a fixed

frequency; CDR can capture the clock source derived fronl
MU through decoding the frames. CDR receives the frames at
the frequency that follows the sending frequency of the
sending side precisely. The receiving signal is lagged a fix
time delay which is determined by the maximum network
transfer time (tb).
One big enough sending stack is essential in MU and
another big enough receiving one is contained in CDR. In
MU, SAY messages firstly enter into the sending stack. With
the trigger of sending signal, messages leave stack for network
one after another; Accordingly, Messages coming from MU
firstly enter into the stack of CDR. With the trigger of
receiving signal, messages leave stack for physical layer of
CDR one after another. Through this designing, the network
transfer time (tb) is modified as constant value.


Ii : :

Sending frequency

L . - -_ _----l


i::ReceiVing frequency

m~imUjje ~elaY . ~

Sjitl~k ~

Receiving stack
Fig. 10. Explanation for PLL application

Using this PLL technology, we can simply implement the

relative time synchronization between CDR and MU. But
message-lost must be avoided through increasing the size of
buffer and enhancing the reliability of communication, or
messages at different time will reduce maloperation of the
current differential protection. Message-lost can be detected
by subscriber (CDR) using sampling count parameter which is
contained in SAV messages coming from publisher (MU)

Delay-non-deterministic in network data transmission is the

most serious threat to correct performance of current
differential protection based on NCIT and IEC 61850. PLL
technology can implement relative time synchronization
between CDR and MU, so the proposed scheme can simply
function based on the existing equipments.
Several improvements must be considered in future:
(1) PLL is a hardware connecting MU and CDR, that
requires MU and CDR be installed in the same cabinet or
place not far away from each other.
(2) The sacrifice of operating time of protection is the most
serious drawback in the PLL scheme.
(3) Message-lost must be avoided to implement the basic
function of current differential protection.
With the development of communication technology and
capacity of the lEOs, Delay-non-deterministic problem will be
gradually solved in the foreseeing future.

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Kun Liu received the B.E. degree in electrical engineering from Tianjin
University, China, in 2006.
Currently, he is a Ph.D. student in Tsinghua University, China. His research
interests include protective relaying and substation automation system.
Xinzhou Dong (M'99-SM'01) received the B.Sc., M.Sc. and Ph.D. degree in
electrical engineering from Xi'an Jiaotong University, China, in 1983, 1991 and
1996 respectively.
He furthered his post-doctoral research at the Electrical Engineering Station
of Tianjin University, China, from 1997 to 1998. Since February 1999, he has
been working at Tsinghua University, China, where he currently serves as a
Professor and the Director of Research Center of Protection and Control
between Tsinghua Univ. and AREVA Co. His research interests include
protective relaying, fault location, and application of wavelet transforms in
power systems.
Zhiqian Bo (M'87-SM'95) received the B.Sc. degree from the Northeastern
University, China in 1982 and Ph.D. degree from the Queen's University of
Belfast, UK in 1988 respectively.
From 1989 to 1997, he worked at the Power Systems Group in the
University of Bath. Currently, he is with AREVA T&D UK and responsible for
new technology developments. His main research interests are power system
protection and control.