Sie sind auf Seite 1von 32

COURSE TITLE: DIGITAL ELECTRONICS AND DIGITAL INSTRUMENTS

(Code: 3340904)
TEACHING AND EXAMINATION SCHEME
Teaching Scheme
(In Hours)

Total
Credits
(L+T+P)

Examination Scheme
Theory Marks
Practical
Marks

ESE

PA

ESE

PA

70

30

20

30

Total
Marks
150

SYLLABUS
Unit

Major Learning Outcomes

Topics and Sub-topics

(in cognitive domain)

Unit I
Number
Systems

1a. Convert numbers from


one to another system
1b. Perform binary
arithmetical operations.
1c. Explain various types of
binary codes and its
applications.

1.1Types of number system, inter conversion


1.2 Basic mathematical operations 1s
complement,2s complement, 9s
complement and 10s complement
1.3 Binary addition, subtraction,
multiplication and division.
1.4 Introductions to codes Binary, weighted
,non weighted codes, Excess code, Grey
code, BCD code, Hamming code (only
introduction)

Unit II
Logic Gates
And Wave
Shaping
Circuits

2a. Use of Diode as Wave


shaping circuit with the
output waveforms of the
clipper circuit.
2b. Differentiate different
logic levels
2c.Prepare the truth table of
various logic gates.
2d. Develop basic gates
using Universal gates
2e. State the features of
various logic families

2.1 Diode and transistor as a switch.


2.2 Diode as a clipper circuit

3a.Apply laws of Boolean


algebra
3b.State the need for
Demorgans theorems.

3.1 Laws of Boolean algebra.

3c.Build logic circuit for a


given Boolean expression
3d.Build various
combinational circuits.
3e.Describe the working of 3
to 8 decoder and BCD to
Seven segment decoder

3.3 Boolean expression and logic diagram


and vice versa
3.4 Simplification of given Boolean equation.
3.5 Combinational circuits: Half and Full
Adder, half and full Subtractor,
Multiplexer and Demultiplexer Encoder
and Decoder

Unit III
Boolean
Algebra and
Combinational
Circuits

2.3 Positive logic and negative logic levels


2.4 Different types of logic gates, symbol and
truth table
2.5 Universal gates - NAND and NOR

2.6 Logic family RTL, DTL


2.7 NMOS, PMOS and CMOS

3.2 Demorgans theorems.

Unit- IV
Sequential
Circuits

Unit-V

4a.Explain the working of


various Flip Flops with
the help of truth table.
4b.Describe the working of
various types of shift
generator.
4c.Draw the waveform of
Asynchronous and
Synchronous counter
counters

4.1Flip-Flop (FF) circuits: R-S, D, J-K and


master slave J-K.

4.3Asynchronous and Synchronous


using 7493 and 7490

counter

4d. Select various

4.4 Introduction of Semiconductor

memory

semiconductor memories

RAM, ROM, PROM, EPROM and EEPROM

5a.Describe the working of

5.1

A to D And D
various types of A to D
to A
convertors.
Convertors and 5b.Describe the working of
Display Devices
various types of and D to
A convertors.

Unit-VI
Digital
Instruments

4.2Shift register: series, parallel left and


right

5.2

5c.Explain working of
various display devices
used with digital circuits.

5.3

6a. State the features of


digital over analog
instruments.
6b.Draw the block diagram
of digital instruments and
explain each block.

6.1

6c. Explain the working of


various Digital

6.3

instruments

6.2

6.4

Digital to Analog conversion.


Weighted Resistor Network type
Binary Ladder Network type
Analog to Digital conversion
Parallel Comparator type
Successive approximation type
Counter OR Staircase type
Display devices
Mechanical Drum or Disc type
Light Emitting Diode type
Liquid Crystal Display
Comparison of digital instrument
with
analog instrument.
Basic building blocks of -digital
instruments.
Digital volt-meter - Ramp and
Staircase
type
Digital frequency meter, multi
meter,
Digital watt meter, Digital energy
meter

SUGGESTED SPECIFICATION TABLE WITH HOURS AND MARKS (THEORY)


Unit
No.
I
II
III
IV
V
VI

Unit Title

Number Systems
Logic Gates and Wave shaping
Circuits
Boolean Algebra And
Combinational Circuits
Sequential Circuits
A to D and D to A Convertors
and Display Devices
Digital Instruments
Total

Teaching
Hours
8

Distribution of Theory Marks


R
U
A
Total
Level
Level
Level Marks
2
4
4
10

11

14

12

15

11

14
10

6
56

3
20

3
25

1
25

7
70

UNIT I
NUMBER SYSTEMS
Types of number system, inter conversion

Basic mathematical operations


1s complement
2s complement
9s complement and
10s complement

Binary addition, subtraction, multiplication and division.

Introductions to codes
Binary weighted & non weighted codes
Excess code
Grey code,
BCD code
Hamming code (only introduction)

Binary to gray code conversion


Binary to gray code conversion is a very simple process. There are several steps to do this
types of conversions. Steps given below elaborate on the idea on this type of conversion.
1.
The M.S.B. of the gray code will be exactly equal to the first bit of the given binary
number.
2.
Now the second bit of the code will be exclusive-or of the first and second bit of the
given binary number, i.e if both the bits are same the result will be 0 and if they are
different the result will be 1.
3.
The third bit of gray code will be equal to the exclusive-or of the second and third bit
of the given binary number. Thus the Binary to gray code conversion goes on. One
example given below can make your idea clear on this type of conversion.

Thus the equivalent gray code is 01101. Now concentrate on the example where the M.S.B. of
the binary is 0 so for it will be 0 for the most significant gray bit. Next, the XOR of the first
and the second bit is done. The bits are different so the resultant gray bit will be 1. Again
move to the next step, XOR of second and third bit is again 1 as they are different. Next, XOR
of third and fourth bit is 0 as both the bits are same. Lastly the XOR of fourth and fifth bit is 1
as they are different. That is how the result of binary to gray code conversion of 01001 is done
whose equivalent gray code is 01101.

Gray code to binary conversion


Gray code to binary conversion is again very simple and easy process. Following steps can
make your idea clear on this type of conversions.
1.
The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
2.
Now if the second gray bit is 0 the second binary bit will be same as the previous or
the first bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it
was 0 it will be 1.
3.
This step is continued for all the bits to do Gray code to binary conversion.
One example given below will make your idea clear.

The M.S.B of the binary will be 0 as the M.S.B of gray is 0. Now move to the next gray bit. As it is 1 the
previous binary bit will alter i.e it will be 1, thus the second binary bit will be 1. Next look at the third bit of the
gray code. It is again 1 thus the previous bit i.e the second binary bit will again alter and the third bit of the
binary number will be 0. Now, 4th bit of the given gray is 0 so the previous binary bit will be unchanged, i.e 4th

binary bit will be 0. Now again the 5th grey bit is 1 thus the previous binary bit will alter, it will be 1 from 0.
Therefore the equivalent Binary number in case of gray code to binary conversion will be (01001).

Objective Question & Answers


1. The digital systems usually operate on ........system.
(a) binary
(b) decimal
(c) octal
(d) hexadecimal.
2. The binary system uses powers of ........for positional values.
(a) 2
(b) 10
(c) 8
(d) 16
3. After counting 0, 1, 10, 11, the next binary number is
(a) 12
(b) 100
(c) 101
(d) 110.
4. The number 10002 is equivalent to decimal number
(a) one thousand
(b) eight
(c) four
(d) sixteen.
5. In binary numbers, shifting the binary point one place to the right.
(a) multiplies by 2
(b) divides by 2
(c) decreases by 10
(d) increases by 10.
6. The binary addition 1 + 1 + 1 gives
(a) 111
(b) 10
(c) 110
(d) 11
7. The cumulative addition of the four binary bits ( 1 + 1 + 1 + 1) gives
(a) 1111
(b) 111
(c) 100
(d) 1001
8. The result of binary subtraction (100 011) is
(a) 111
(b) 111
(c) 011
(d) 001.
9. The 2's complement of 10002 is
(a) 0111
(b) 0101
(c) 1000
(d) 0001
10. The chief reason why digital computers use complemental subtraction is that it
(a) simplifies their circuitry
(b) is a very simple process
(c) can handle negative numbers easily
(d) avoids direct subtraction.
11. The result of binary multiplication 1111 102 is

(a) 1101
(b) 0110
(c) 1001
(d) 1110
12. The binary division 110002 1002 gives
(a) 110
(b) 1100
(c) 11
(d) 101
13. The number 128 is equivalent to decimal
(a) 12
(b) 20
(c) 10
(d) 4
14. The number 1001012 is equivalent to octal
(a) 54
(b) 45
(c) 37
(d) 25.
15. The number 178 is equivalent to binary
(a) 111
(b) 1110
(c) 10000
(d) 1111.
16. Which of the following is NOT an octal number?
(a) 19
(b) 77
(c) 15
(d) 101
17. Hexadecimal number system is used as a shorthand language for representing .......numbers.
(a) decimal
(b) binary
(c) octal
(d) large
18. The binary equivalent of A16 is
(a) 1010
(b) 1011
(c) 1000
(d) 1110.
19. BCD code is
(a) non-weighted
(b) the same thing as binary numbers
(c) a binary code
(d) an alphanumeric code.
20. Which of the following 4-bit combinations is/are invalid in the BCD code ?
(a) 1010
(b) 0010
(c) 0101
(d) 1000.
21. Octal coding involves grouping the bits in
(a) 5's
(b) 7's
(c) 4's
(d) 3's.
22. In Excess-3 code each coded number is .......than in BCD code.
(a) four larger
(b) three smaller
(c) three larger
(d) much larger.
23. Which numbering system uses numbers and letters as symbols ?

(a) decimal
(b) binary
(c) octal
(d) hexadecimal
24. To convert a whole decimal number into a hexadecimal equivalent, one should divide the
decimal value by.......
(a) 2
(b) 8
(c) 10
(d) 16.
Answers
1. (a) 2. (a) 3. (b) 4. (b) 5. (a) 6. (d) 7. (b) 8. (d) 9. (c) 10. (a) 11. (d) 12. (a) 13. (c) 14. (b) 15. (d) 16. (a) 17. (a) 18. (a) 19. (c)
20. (a) 21. (d) 22. (c) 23. (d) 24. (a)

Unit II
Logic Gates and Wave Shaping Circuits
2.1 Diode and transistor as a switch.
2.2 Diode as a clipper circuit
2.3 Positive logic and negative logic levels
2.4 Different types of logic gates, symbol and truth table
2.5 Universal gates - NAND and NOR
2.6 Logic family RTL, DTL
2.7 NMOS, PMOS and CMOS

2.1 Diode and transistor as a switch.


Diode as a Switch
A diode is said to be an Ideal Diode when it is forward biased and acts like a perfect
conductor, with zero voltage across it. Similarly, when the diode is reversed biased, it acts as a
perfect insulator with zero current through it.
The V-I characteristics of an Ideal diode are shown in the figure below.

An Ideal diode also acts like a switch. When the diode is forward biased it acts like a closed
switch as shown in the figure below.

Whereas, if the diode is reversed biased, it acts like an open switch as shown in the figure
below.

Transistor as a Switch
We all know that a transistor has 4 regions of operation, in which Active, Cut-off and Saturation are
commonly used. A transistor works in active region when worked as an Amplifier. When a transistor
works as a Switch it works in Cut-off and Saturation Regions. In the Cut-off State both Emitter Base
Junction and Collector Base junctions are reverse biased. But in saturation region both junctions are
forward biased. Switch is a very useful and important application of transistors. In most digital ICs
transistors will work as a switch to make power consumption very low. It is also a very useful circuit
for an electronics hobbyist as it can be used as a driver, inverter etc.

Circuit Diagram Transistor as a Switch


From the above circuit we can see that the
control input Vin is given to base through a
current limiting resistor Rb and Rc is the
collector resistor which limits the current
through the transistor. In most cases output is
taken from collector but in some cases load is
connected in the place of Rc.

ON = Saturation

OFF = Cutof

Transistor as a Switch ON
Transistor will become ON
(saturation) when a sufficient
voltage V is given to input. During
this condition the Collector Emitter
voltage
Vce
will
be approximately equal to zero, ie
the transistor acts as a short circuit.
For a silicon transistor it is equal to
0.3v. Thus collector current Ic =
Vcc/Rc will flows.

Transistor as a Switch
OFF
Transistor will be in OFF (cut-of) when the
input Vin equal to zero. During this state
transistor acts as an open circuit and thus
the entire voltage Vcc will be available at
collector.

Positive logic and negative logic levels


Positive Logic: With reference to positive logic, logical 1 state is the most positive logic or
voltage level and logic 0 state is the most negative logic or voltage level. In other words,
active high level is 1 and active low level is 0.
For instance, V(0) = 0V and V(1) = 5V, V(0) = 5V and V(1) = 15V.

Negative Logic: With reference to negative logic, logic 0 state is the most positive logic or
voltage level and logic 1 state is the most negative logic or voltage level. In other words,
active high level is 0 and active low level is 1.
For instance, V(0) = 5V and V(1) = 0V, V(0) = 15V and V(1) = 5V.

Thus a positive logic AND gate acts as a negative logic OR gate and vice versa.
Hope you find the information presented here useful. Please leave your footprints in the
comments section below for any feedback or queries.

Different types of logic gates, symbol and truth table

SUMMARY

GTU
QUESTION

PAPERS

DIGITAL LOGIC FAMILIES


In Digital Designs, our primary aim is to create an
Integrated Circuit (IC). A Circuit configuration or arrangement of
the circuit elements in a special manner will result in a
particular Logic Family. Electrical Characteristics of the IC will be
identical. In other words, the different parameters like Noise
Margin, Fan In, Fan Out etc. will be identical. Different ICs
belonging to the same logic families will be compatible with
each other.
The basic Classification of the Logic Families are as follows:
A) Bipolar Families:
1. Diode Logic (DL)
2. Resistor Transistor Logic (RTL)
3. Diode Transistor Logic (DTL)
4. Transistor- Transistor Logic (TTL)
5. Emitter Coupled Logic (ECL) or Current Mode Logic
(CML)
6. Integrated Injection Logic (IIL)

B) MOS Families:
1. P-MOS Family
2. N-MOS Family
3. Complementary-MOS Family

Diode Logic
In DL (diode logic), only Diode and Resistors are used for
implementing a particular Logic. Remember that the Diode
conducts only when it is Forward Biased.

Disadvantages of Diode Logic


Diode Logic suffers from voltage degradation from one stage to the
next.
Diode Logic only permits OR and AND functions.

Resistor Transistor Logic


In RTL (resistor transistor logic), all the logic are implemented using resistors
and transistors. One basic thing about the transistor (NPN), is that HIGH at input
causes output to be LOW (i.e. like a inverter). In the case of PNP transistor, the
LOW at input causes output to be HIGH.

Advantage:

Less number of Transistors


Disadvantage:

High Power Dissipation

Low Fan In

Diode Transistor Logic


In DTL (Diode transistor logic), all the logic is implemented using
diodes and transistors.

Disadvantage:
Propagation Delay is Larger

Unit-VI
Digital Instruments

Signal

Waves
Representation
Example
Technology

Analog
Analog signal is a continuous
signal which represents physical
measurements.
Denoted by sine waves
Uses continuous range of values to
represent information
Human voice in air, analog
electronic devices.
Analog technology records
waveforms as they are.

Data transmissions Subjected to deterioration by noise


during transmission and write/read
cycle.

Digital
Digital signals are discrete time
signals generated by digital
modulation.
Denoted by square waves
Uses discrete or discontinuous values
to represent information
Computers, CDs, DVDs, and other
digital electronic devices.
Samples analog waveforms into a
limited set of numbers and records
them.
Can be noise-immune without
deterioration during transmission and
write/read cycle.

Response to Noise More likely to get affected


reducing accuracy
Flexibility Analog hardware is not flexible.
Uses Can be used in analog devices
only. Best suited for audio and
video transmission.
Applications Thermometer
Bandwidth Analog signal processing can be
done in real time and consumes
less bandwidth.
Memory Stored in the form of wave signal
Power Analog instrument draws large
power
Cost Low cost and portable
Impedance Low
Errors Analog instruments usually have a
scale which is cramped at lower
end and give considerable
observational errors.

Less affected since noise response


are analog in nature
Digital hardware is flexible in
implementation.
Best suited for Computing and
digital electronics.
PCs, PDAs
There is no guarantee that digital
signal processing can be done in real
time and consumes more bandwidth
to carry out the same information.
Stored in the form of binary bit
Digital instrument drawS only
negligible power
Cost is high and not easily portable
High order of 100 megaohm
Digital instruments are free from
observational errors like parallax and
approximation errors.

Instrumentation System
INSTRUMENTATION SYSTEMS CAN BE CLASSIFIED INTO TWO.

1. Analog Instrumentation System


The block diagram is shown below.
An analog instrumentation system includes three functional units. They are

Analog Instrumentation System


The Primary Element/Transducer
The input receives the quantity whose value is to be measured and is converted into its
proportional incremental electrical signal such as voltage, current, resistance change,
inductance or even capacitance. Thus, the changed variable contains the information of the
measured variable. Such a functional element or device is called a transducer.

The Secondary Element/Signal Processing Unit


The output of the transducer is provided to the input of the signal processing unit. This unit
amplifies the weak transducer output and is filtered and modified to a form that is acceptable
by the output unit. Thus this unit may have devices like: amplifiers, filters, analog to digital
converters, and so on.

The Final Element/Output Unit


The output from the signal processing unit is fed to the input of the output unit. The output
unit measures the signal and indicates the value to the reader. The indication may be either
through: an indicating instrument, a CRO, digital computer, and so on.

2. Digital Instrumentation System


All the functional units that were used in an analog system will also be used here. He basic
operation in a digital system includes the handling of analog signals, making the
measurements, converting and handling digital data, programming and also control. The block
diagram and functional units are given below.

Digital Instrumentation System

Transducer
All the physical input parameters like temperature, pressure, displacement, velocity,
acceleration and so on will be converted into its proportionate electrical signal.

Signal Conditioning Unit


This working of this unit is exactly the same as that of a signal processing unit in an analog
instrumentation system. It includes all the balancing circuits ad calibrating elements along
with it.

Scanner/Multiplexer
Multiple analog signals are received by this device and are sequentially provided on to a
measuring instrument.

Signal Converter
It is used to convert an analog signal to a form that is acceptable by the analog to digital
converter.

Analog to (A-D) Digital Converter


The analog signal is converted into its proportional digital signal. The output of an A-D
converter is given to a digital display.

Auxiliary Equipment

All the system programming and digital data processing functions are carried out by this unit.
The auxiliary equipment may be a single computer or may be a collection of individual
instruments. Some of its basic functions include linearizing and limit comparison.

Digital Recorder
It is mostly a CRO or a computer.

Unit III
Boolean Algebra and Combinational Circuits

3.1 Laws of Boolean algebra.


3.2 Demorgans theorems.
3.3 Boolean expression and logic diagram and vice versa
3.4 Simplification of given Boolean equation.
3.5 Combinational circuits:
Half and Full Adder
half and full Subtractor
Multiplexer and DE multiplexer
Encoder and Decoder

Unit- IV
Sequential Circuits
Flip-Flop (FF) circuits: R-S, D, J-K and master slave J-K.
Shift register: series, parallel left and right
Asynchronous and Synchronous counter using 7493 and 7490
Introduction of Semiconductor memory RAM, ROM, PROM,
EPROM and EEPROM

A digital computer needs devices which can store information. A flip flop is a binary
storage device. It can store binary bit either 0 or 1. It has two stable states HIGH and LOW i.e.
1 and 0. It has the property to remain in one state indefinitely until it is directed by an input
signal to switch over to the other state. It is also called bistable multivibrator.
The basic formation of flip flop is to store data. They can be used to keep a record or
what value of variable (input, output or intermediate). Flip flop are also used to exercise
control over the functionality of a digital circuit i.e. change the operation of a circuit
depending on the state of one or more flip flops.
These devices are mainly used in situations which require one or more of these three.
Operations, storage and sequencing.

Latch Flip Flop


The RS (Reset Set) flip flop is the simplest flip flop of all and easiest to understand. It
is basically a device which has two outputs one output being the inverse or complement of the
other, and two inputs.
A pulse on one of the inputs to take on a particular logical state. The outputs will then
remain in this state until a similar pulse is applied to the other input. The two inputs are called
the Set and Reset input (sometimes called the preset and clear inputs).
Such flip flop can be made simply by cross coupling two inverting gates either NAND
or NOR gate could be used Figure 1(a) shows on RS flip flop using NAND gate and Figure
1(b) shows the same circuit using NOR gate.

To describe the circuit of Figure 1(a), assume that initially both R and S are at
the logic 1 state and that output is at the logic 0 state.
Now, if Q = 0 and R = 1, then these are the states of inputs of gate B, therefore
the outputs of gate B is at 1 (making it the inverse of Q i.e. 0). The output of gate B is
connected to an input of gate A so if S =1, both inputs of gate A are at the logic 1 state. This
means that the output of gate A must be 0 (as was originally specified). In other words, the 0
state at Q is continuously disabling gate B so that any change in R has no effect. Also the 1
state at is continuously enabling gate A so that any change S will be transmitted through to Q.

The above conditions constitute one of the stable states of the device referred to as the Reset
state since Q = 0.
Now suppose that the RS flip flop in the Reset state, the S input goes to 0. The
output of gate A i.e. Q will go to 1 and with Q = 1 and R = 1, the output of gates B ( ) will go
to 0 with now 0 gate A is disabled keeping Q at 1. Consequently, when S returns to the 1 state
it has no effect on the flip flop whereas a change in R will cause a change in the output of gate
B. The above conditions constitute the other stable state of the device, called the Set state
since Q = 1. Note that the change of the state of S from 1 to 0 has caused the flip flop to
change from the Reset state to the Set state.
There is another input condition which has not yet been considered. That is when
both the R and S inputs are taken to the logic state 0. When this happens both Q and will be
forced to 1 and will remain so far as long as R and S are kept at 0. However when both inputs
return to 1 there is no way of knowing whether the flip flop will latch in the Reset state or the
Set state. The condition is said to be indeterminate because of this indeterminate state great
care must be taken when using RS flip flop to ensure that both inputs are not instructed
simultaneously

When NOR gate are used the R and S inputs are transposed compared with the NAND
version. Also the stable state when R and S are both 0. A change of state is effected by pulsing
the appropriate input to the 1 state. The indeterminate state is now when both R and S are
simultaneously at logic 1.
Table 3 shows this operation

Clocked RS Flip Flop


The RS latch flip flop required the direct input but no clock. It is very use full to add clock to
control precisely the time at which the flip flop changes the state of its output.
In the clocked RS flip flop the appropriate levels applied to their inputs are blocked till the
receipt of a pulse from another source called clock. The flip flop changes state only when clock pulse
is applied depending upon the inputs. The basic circuit is shown in Figure 2. This circuit is formed by
adding two AND gates at inputs to the RS flip flop. In addition to control inputs Set (S) and Reset (R),
there is a clock input (C) also.

The excitation table for RS flip flop is very simply derived as given below

D Flip Flop

A D type (Data or delay flip flop) has a single data input in addition to the clock input as
shown in Figure 3.

Basically, such type of flip flop is a modification of clocked RS flip flop gates
from a basic Latch flip flop and NOR gates modify it in to a clock RS flip flop. The D input
goes directly to S input and its complement through NOT gate, is applied to the R input.
This kind of flip flop prevents the value of D from reaching the output until a clock pulse
occurs. The action of circuit is straight forward as follows.
When the clock is low, both AND gates are disabled, therefore D can change
values without affecting the value of Q. On the other hand, when the clock is high, both AND
gates are enabled. In this case, Q is forced equal to D when the clock again goes low, Q
retains or stores the last value of D. The truth table for such a flip flop is as given below in
table 6.

JK Flip Flop
One of the most useful and versatile flip flop is the JK flip flop the unique features of a JK flip
flop are:

1. If the J and K input are both at 1 and the clock pulse is applied, then the output will change state,
regardless of its previous condition.
2. If both J and K inputs are at 0 and the clock pulse is applied there will be no change in the output.
There is no indeterminate condition, in the operation of JK flip flop i.e. it has no ambiguous state. The
circuit diagram for a JK flip flop is shown in Figure 4.

When J = 0 and K = 0
These J and K inputs disable the NAND gates, therefore clock pulse have no effect on the flip
flop. In other words, Q returns it last value.
When J = 0 and K = 1,
The upper NAND gate is disabled the lower NAND gate is enabled if Q is 1 therefore, flip
flop will be reset (Q = 0, =1) if not already in that state.
When J = 1 and K = 0
The lower NAND gate is disabled and the upper NAND gate is enabled if is at 1, As a result
we will be able to set the flip flop (Q = 1, = 0) if not already set
When J = 1 and K = 1
If Q = 0 the lower NAND gate is disabled the upper NAND gate is enabled. This will set the
flip flop and hence Q will be 1. On the other hand if Q = 1, the lower NAND gate is enabled and flip
flop will be reset and hence Q will be 0. In other words, when J and K are both high, the clock pulses
cause the JK flip flop to toggle. Truth table for JK flip flop is shown in table 8.

T Flip Flop

A method of avoiding the indeterminate state found in the working of RS flip flop is to
provide only one input (the T input) such, flip flop acts as a toggle switch. Toggle means to

change in the previous stage i.e. switch to opposite state. It can be constructed from clocked
RS flip flop be incorporating feedback from output to input as shown in Figure 5.

Such a flip flop is also called toggle flip flop. In such a flip flop a train of extremely
narrow triggers drives the T input each time one of these triggers, the output of the flip flop
changes stage. For instance Q equals 0 just before the trigger. Then the upper AND gate is
enable and the lower AND gate is disabled. When the trigger arrives, it results in a high S
input.
This sets the Q output to 1. When the next trigger appears at the point T, the lower
AND gate is enabled and the trigger passes through to the R input this forces the flip flop to
reset.
Since each incoming trigger is alternately changed into the set and reset inputs the flip
flop toggles. It takes two triggers to produce one cycle of the output waveform. This means
the output has half the frequency of the input stated another way, a T flip flop divides the input
frequency by two. Thus such a circuit is also called a divide by two circuit

Master Slave JK Flip Flop

Figure 8 shows the schematic diagram of master slave JK flip flop

A master slave flip flop contains two clocked flip flops. The first is called master and the
second slave.
When the clock is high the master is active. The output of the master is set or reset according
to the state of the input. As the slave is inactive during this period its output remains in the
previous state.
When clock becomes low the output of the slave flip flop changes because it become active
during low clock period. The final output of master slave flip flop is the output of the slave
flip flop. So the output of master slave flip flop is available at the end of a clock pulse.

Introduction of Semiconductor memory


Classification of Memory:

This section provides classification of memories. There are two main types of memories i.e.
RAM and ROM. Following tree diagram shows the classification of Memory:

ROM (Read Only Memory):


First classification of memory is ROM. The data in this memory can only be read, no writing
is allowed. It is used to store permanent programs. It is non-volatile type of memory. The
classification of ROM memory is as follows:

Masked ROM
PROM
EPROM
EEPROM

a)
Masked ROM: the program or data are permanently installed at the time of
manufacturing as per requirement. The data cannot be altered.
The process of permanent recording is expensive but economic for large quantities.
b)
PROM (Programmable Read Only Memory): The basic function is same as that of
masked ROM. but in PROM, we have fuse links. Depending upon the bit pattern, fuse can be
burnt or kept intact. This job is performed by PROM programmer.
To do this, it uses high current pulse between two lines. Because of high current, the fuse will
get burnt; effectively making two lines open. Once a PROM is programmed we cannot change
connections, only a facility provided over masked ROM is, user can load his program in it.
The disadvantage is a chance of regrowing of fuse and changes the programmed data because
of aging.
c)
EPROM (Erasable Programmable Read Only Memory): the EPROM is
programmable by the user. It uses MOS circuitry to store data. They store 1s and 0s in form
of charge. The information stored can be erased by exposing the memory to ultraviolet light
which erases the data stored in all memory locations. For ultraviolet light a quartz window is
provided which is covered during normal operation. Upon erasing it can be reprogrammed by
using EPROM programmer. This type of memory is used in project developed and for
experiment use. The advantage is it can be programmed erased and reprogrammed. The
disadvantage is all the data get erased even if you want to change single data bit.
d)
EEPROM: EEPROM stands for electrically erasable programmable read only memory.
This is similar to EPROM except that the erasing is done by electrical signals instead of
ultraviolet light. The main advantage is the memory location can be selectively erased and

reprogrammed. But the manufacturing process is complex and expensive so do not commonly
used.
RAM (Random Access Memory):
Second classification of memory is RAM. The RAM is also called as read/write memory. The
RAM is a volatile type of memory. It allows programmer to read or write data. If the user
wants to check execution of any program, user feeds the program in RAM memory and
executes it. The result of execution is then checked by either reading memory location
contents or by register contents.
Following is the classification of RAM memory. It is available in two types:
a)
SRAM (Static RAM): SRAM consists of flip-flop; using either transistor or MOS. for
each bit we require one flip-flop. Bit status will remain as it is; unless and until you perform
next write operation or power supply is switched off.

Advantages of SRAM:

1) Fast memory (less access time)


2) Refreshing circuit is not required.

Disadvantages of SRAM:

1)

Low package density

2)

Costly

b)
DRAM (Dynamic RAM): In this type of memory a data is stored in form of charge in
capacitors. When data is 1, the capacitor will be charged and if data is 0, the capacitor will not
be charged. Because of capacitor leakage currents the data will not be hold by these cells. So
the DRAMs require refreshing of memory cells. It is a process in which same data is read and
written after a fixed interval.

Advantages of DRAM:

1)

High package density

2)

Low cost

Disadvantages of DRAM:

1)
Required refreshing circuit to maintain or refresh charge on capacitor, every after few
milliseconds.