Vlsi Manual

Mahatma Gandhi Mission's
COLLEGE OF ENGINEERING
&TECHNOLOGY
Kamothe, Navi Mumbai 410 209.
DEPARTMENT OF BIOMEDICAL ENGINEERING
Laboratory Journal
for the subject
Very Large Scale Integration
B.E. Semester-VII
Name of the student:

Batch:.......................................................................................
Roll no.:Exam Seat No
MGMS COLLEGE OF ENGINEERING AND

Academic Year:
TECHNOLOGY
KAMOTHE, NAVI-MUMBAI
DEPARTMENT OF BIOMEDICAL ENGINEERING
B.E. SEM VII (BIOMEDICAL ENGG) VLSI

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Subject- Very Large Scale Integration
INDEX
Sr
DATE
No.
NAME OF THE EXPERIMENT
PAGE
No.
REMARK
SIGN
Basic Logic gates ( using VHDL)
Binary to gray and Gray to Binary code

conversion( using VHDL)
Binary to Excess-3 code conversion( using
VHDL)
Implementation of Multiplexer( using VHDL)
Implementation of Demultiplexer( using
VHDL)
Implementation of Adder(using VHDL)
Implementation of 4 bit full adder using half
adder as component( using VHDL)
Study of Inverter characteristics(using wspice)
2
3
4
5
6
7
8
Assignment 1
Assignment 2
10
Assignment 3
11
Assignment 4
12
Date:
Grade:
Faculty Incharge

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CERTIFICATE
THIS IS TO CERTIFY THAT
MISS/MR.
..
Has
Satisfactorily Completed the Practicals of the Subject

VLSI (Very Large Scale Integrated Circuits)
PRESCRIBED BY MUMBAI UNIVERSITY IN
Faculty Incharge
Head Of Dept.

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Experiment No: 01
DATE:
AIM: To study AND, NAND, OR, NOT, NOR, XOR gate using Xilinx Simulator..
THEORY:
OR Gate:
Its gate with 2 or more i/ps and single o/p.
The o/p is high only when the i/p is high.
The logical expression is y=A+B.
AND Gate: It is equivalent to no. of switches connected in serious.
An o/p is high only if all switches are closed.
The logical expression is Y=A .B.

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NOT Gate : It is single i/p and single o/p gate.
O/p is inverted version of i/p.
The logical expression is
NAND Gate: Operation of NAND gate is similar to AND gate in series with NOT gate.
O/p is low when i/p is high.
It is universal gate.

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NOR Gate: Its operation is similar to OR gate in series with NOT gate.
It is universal gate.

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EX-OR Gate: The o/p is high only if odd no. of i/ps are high.
EX-NOR: The operation is similar to EX-OR gate connected in series with NOT gate.

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Write VHDL codes for the following:

1. Write features of VHDL.
2. Write information about library functions.
3. Write stucture of VHDL programs
4. Write VHDL codes for AND gate
5. Write VHDL codes for OR gate
6. Write VHDL codes for NAND gate using basic gates
7. Write VHDL codes for NOR gate using basic gates
8. Write VHDL codes for Ex-OR gate using basic gates
9. Write VHDL codes for Ex-NOR gate using basic gates
10. Write VHDL codes for for the following boolean expression.
F= ABC+ABC
Attach Print outs of Programs and Screenshots.
Observations:
Conclusions:
Date:
Grade:
Faculty Incharge

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Experiment No: 02
DATE:
AIM: Binary to gray and Gray to Binary code conversion (using VHDL)
THEORY:
The logical circuit which converts binary code to equivalent gray code is known as
binary to gray code converter. The gray code is a non weighted code. The successive
gray code differs in one bit position only that means it is a unit distance code. It is also
referred as cyclic code. It is not suitable for arithmetic operations. It is the most popular
of the unit distance codes. It is also a reflective code.
Binary to gray code conversion:
Steps given below elaborate on the idea on this type of conversion:
The M.S.B. of the gray code will be exactly equal to the first bit of the given binary
number.
Now the second bit of the code will be exclusive-or of the first and second bit of the
given binary number, i.e if both the bits are same the result will be 0 and if they are
different the result will be 1.
The third bit of gray code will be equal to the exclusive or of the second and third bit of
the given binary number.
One example given below can make your idea clear on this type of conversion.
Thus the equivalent gray code is 01101.

Now concentrate on the example where the M.S.B. of the binary is 0 so for it will be 0 for
the most significant gray bit.
1. The XOR of the first and the second bit is done. The bits are different so the resultant gray
bit will be 1.

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2. Again move to the next step, XOR of second and third bit is again 1 as they are different.
3. Next, XOR of third and fourth bit is 0 as both the bits are same.
4. Lastly the XOR of fourth and fifth bit is 1 as they are different.
The result of binary to gray code conversion of 01001 is done whose equivalent gray code is
01101.
That means, in a 4 bit gray code, (4-1) or a 3 bit code is reflected against the axis drawn after
(24-1)th or 8th row. The bits of 4 bit gray code are considered as G 4G3G2G1. Now from
conversion table,

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Fro
m above SOPs, let us draw K -maps for G4, G3, G2 and G1.

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Grey to Binary Code Converter

In gray to binary code converter, input is a multiplies gray code and output is its equivalent
binary code.
Let us consider a 4 bit gray to binary code converter. To design a 4 bit gray to binary code
converter, we first have to draw a conversion table.

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From above gray code we get,

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Exercise:
1. Explain reflective property of Gray code.
2. Write application of Gray code.
3. Find Gray code for the following binary numbers.
a. 11001100
b. 01011110
4. What is the advantage of gray code over binary number?
5. Write VHDL codes for 2 bits comparator.
6.
7.
8.
Observations:
Conclusions:
Date:
Grade:
Faculty Incharge

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Experiment No: 03
DATE:
AIM: Binary to Excess 3 code conversion (using VHDL)
THEORY:
The term BCD refers to representing the ten decimal digits in binary forms; which simply
means to count in binary; see Table 1 below. The Excess-3 system simply adds 3 to each
number to make the codes look different. System because the discussion would serve too
great a distraction from our present purpose and the cost would outweigh the benefit. Suffice
it to say that the Excess-3 BCD system has some properties that made it use`ful in early
computers.
Decimal Numerals
Binary Numerals
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Table 1: BCD
The Excess-3 BCD system is formed by adding 0011 to each BCD value as in Table 2. For
example, the decimal number 7, which is coded as 0111 in BCD, is coded as
0111+0011=1010 in Excess-3 BCD.

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Decimal Numerals
Binary Numerals
Excess-3
0000
0011
0001
0100
0010
0101
0011
0110
0100
0111
0101
1000
0110
1001
0111
1010
1000
1011
1001
1100
Table 2: BCD Excess-3
Code converters, more specifically encoders and decoders, have been used to protect
private information.
Indeed, code converters have proven to be so effective that the National Security
Agency (NSA) has made a career out of creating and breaking codes.
To convert fro binary to excess 3 code the input lines must supply the bit combination
of elements as specified by the code.
Binary Coded Decimal

The term BCD refers to representing the ten decimal digits in binary forms; which
simply means to count in binary.
In computing and electronic systems, binary coded decimal is a class of binary
encodings of decimal numbers where each decimal digit is represented by a fixed
number of bits, usually four or eight, although other sizes (such as six bits) have been
used historically. Special bit patterns are sometimes used for a sine or for other
indications ( e.g. error or overflow).

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Date:
Grade:
Faculty Incharge

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Experiment No: 04
DATE:
AIM: To implement of multiplexer with the help of Xilinx Simulator.
THEORY:
In electronics, a multiplexer (or mux) is a device that selects one of several analog or digital
input signals and forwards the selected input into a single line. A multiplexer of 2n inputs has
n select lines, which are used to select which input line to send to the output
Multiplexers: In electronics, a multiplexer (or mux) is a device that selects one of several
analog or digital input signals and forwards the selected input into a single line. A multiplexer
of 2 n inputs has n select lines, which are used to select which input line to send to the output.
A 2n -to-1 multiplexer sends one of 2n input lines to a single output line. A multiplexer has
two sets of inputs: 2n data input lines n select lines, to pick one of the 2n data inputs The
mux output is a single bit, which is one of the 2n data inputs.
The simplest multiplexer is a 2-to-1 mux
Q = S D0 + S D1 The select bit S controls which of the data bits D0-D1 is chosen: If S=0,
then D0 is the output (Q=D0). If S=1, then D1 is the output (Q=D1). Here is a full truth
table for this 2-to-1 mux, based on the equation:

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Q = S D0 + S D1
Here is another kind of abbreviated truth table.
4-to-1 Mux
Here is a block diagram and abbreviated truth table for a 4-to-1 mux.
Be careful! In Logic Works the multiplexer has an active-low EN input signal.
When EN = 1, the mux always outputs 1.
Q = S1 S0 D0 + S1 S0 D1 + S1 S0 D2 + S1 S0 D3

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Implementing functions with multiplexers:
Muxes can be used to implement arbitrary functions. For a function of n variables follow
these steps:
1. Select the type of Mux [2n-1 -to-1].
2. Select (n-1) as selection line.
3. The other input connects as input.
Implement following function with multiplexer:
Solution:
1. The type of Mux [23 -to-1] == 8-to-1 mux
2. Select (3) as selection line. == For example (B, C, and D)
3. The other input connects as input. == (A)

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1 What is multiplexer?
2 What is the significance of enable?
3 Design 8x1 multiplexer using full adder?
4 Design 16x1 multiplexer using 8x1 mux.
Write VHDL codes for 4:1 multiplexer the following :
5 By using data flow method.
6 By using behavioral modeling.
7 By using structural modeling.
8 Use case statement.
9 Use select statement.
10 Use with statement
Observations:
Conclusions:
Date:
Grade:
Faculty Incharge

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Experiment No: 05
DATE:
AIM: To implement Demultiplexer with the help of Xilinx Simulator.

THEORY:
The Demultiplexer is combinational logic circuit that performs the reverse operation of
Multiplexer. It has only one input, n selectors and 2n outputs.
Depending on the combination of the select lines, one of the outputs will be selected to take
the state of the input.
The following figure shows the block diagram and the truth table for 1x4 De-multiplexer.
By applying logic '1' to the input, the circuit will do the same function of the typical
2-to-4 Decoder.

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1.
2.
3.
4.
5.
What is the difference between decoder and demultiplexer?

How many decoders are needed for constructing 4x16 decoders
Write syntax for exit statement.
Write syntax for next statement.
How delay is specified in VHDL programming?
Write VHDL codes for the following:

1
2
3
2
5
By using data flow method.

Use case statement.
Use select statement
2:4 decoder using structural style of modeling
3:8 decoder

Observations:
Conclusions:
Date:
Grade:
Faculty Incharge

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Experiment No: 06
DATE:
AIM: To study Half adder and Full adder using Xilinx Simulator.
THEORY:
HALF ADDER
It is logic circuit that adds two binary digit.
It consist of an EX-OR and an AND gate .
It has two o/ps sum and carry.

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FULL ADDER
It is a logic circuit that adds three digits bit at a time.
It has two o/ps sum and carry.

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Truth table

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FULL SUBTRACTOR
It is needed for multibit subtractor where borrow is from previous bit position.
It has three i/ps
It has 2 o/ps

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Write VHDL code for the following :

1. Half adder
2 Full Adder
3 Half subtractor
2. Full subtractor

Observations:
Conclusions:
Date:
Grade:
Faculty Incharge

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Experiment No: 07
DATE:
Aim: Implementation of full adder using half adder as component (using VHDL)
Full adder using half adder as a component
c) 4 bit adder using full adder as a component
B

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Experiment No: 08
DATE:
Aim: Study Dynamic Characteristics of :
1. NMOS Inverter with Resistive Load.
2. CMOS inverter.
3. Software required: W-spice.
Theory:
Figure of merit to describe logic gates is the response in the time domain
The rise and fall times, tf and tr, are measured at the 10% and 90% points on the transitions
between the two states as shown by the following expressions:
V 10% = V L + 0.1V
V 90% = V L + 0.9V = V H 0.1V
where V is the logic swing given by V = V H - V L

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The resistor R is used to pull the output high

MS is the switching transistor used to pull the output low
The size of R and the W/L ratio of MS are the design factors that need to be chosen.
Study Dynamic Characteristics of CMOS Inverter.

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The switching characteristics of digital ICs essentially determine the overall operating Speed
of digital systems. The closed form delay expression will be derived under the assumption
of pulse excitation for lumped load capacitances. While exact circuit (Spice) simulation
provides the most accurate estimation of the time domain behavior of complex circuits.

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For the inverter with resistive load
Derive relations of VIL
Derive relations of VIH
Derive relations of VOL
Derive relations of VOH
Derive relation of NML
Derive relation of NMH
For CMOS inverter :

Derive relations of VIL
Derive relations of VIH
Derive relations of VOL
Derive relations of VOH
Derive relations of NML
Derive relations of NMH

Observations:
Conclusions:
Date:
Grade:
Faculty Incharge

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Mahatma Gandhi Mission's

DEPARTMENT OF BIOMEDICAL ENGINEERING

Name of the student:

MGMS COLLEGE OF ENGINEERING AND

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

NAME OF THE EXPERIMENT

Basic Logic gates ( using VHDL)

Binary to gray and Gray to Binary code

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

Satisfactorily Completed the Practicals of the Subject

PRESCRIBED BY MUMBAI UNIVERSITY IN

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

Its gate with 2 or more i/ps and single o/p.

The o/p is high only when the i/p is high.

The logical expression is y=A+B.

AND Gate: It is equivalent to no. of switches connected in serious.

An o/p is high only if all switches are closed.

The logical expression is Y=A .B.

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

NOT Gate : It is single i/p and single o/p gate.

O/p is inverted version of i/p.

The logical expression is

O/p is low when i/p is high.

The logical expression is

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

The logical expression is

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

The logical expression is

The logical expression is

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

Write VHDL codes for the following:

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

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Thus the equivalent gray code is 01101.

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B.E. SEM VII (BIOMEDICAL ENGG) VLSI

Mahatma Gandhi Mission's

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

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B.E. SEM VII (BIOMEDICAL ENGG) VLSI

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Grey to Binary Code Converter

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From above gray code we get,

B.E. SEM VII (BIOMEDICAL ENGG) VLSI

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B.E. SEM VII (BIOMEDICAL ENGG) VLSI

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B.E. SEM VII (BIOMEDICAL ENGG) VLSI