Beruflich Dokumente
Kultur Dokumente
US
Troubleshooting Tools
System
System Troubleshooting
10032747
10032746
08653771
05936518
Siemens AG
Siemens Medical
Ultrasound
ejt
DivisionSolutions
2003
English
Doc. Gen. Date: 10.05
n.a.
Revision / Disclaimer
1Revision / Disclaimer
Copyright
Copyright 2004 by Siemens Corporation. All rights reserved. No part of this publication
may be reproduced, transmitted, transcribed, stored in retrieval systems, or translated into
any language or computer language, in any form or by any means, electronic, mechanical,
magnetic, optical, chemical, manual, or otherwise, without the prior written permission of
Siemens Corporation. Siemens Corporation reserves the right to change its products and
services at any time. In addition, this manual is subject to change without notice. Siemens
Corporation welcomes customer input on corrections and suggestions for improvements
to this manual.Although Siemens Corporation has attempted to ensure accuracy throughout this manual, Siemens Corporation assumes no liability for any errors or omissions, nor
for any damages resulting from the application or use of this information.
Trademarks
ACUSON, Sequoia, Cypress, AEGIS, Aspen, 128XP, XP, AcuNav, CV70, SONOLINE,
Adara, Antares, G20, G40, G50, G60S, Omnia and KinetDx are trademarks of Siemens
Corporation registered in the U.S. Patent and Trademark Office. CWS3000, DS3000,
WS3000, and WebPro are trademarks of Siemens Corporation.
Windows XP, 2000 and NT are registered trademarks of Microsoft Corporation. Internet
Explorer is a trademark of Microsoft Corporation. Netscape and Netscape Navigator are
registered trademarks of Netscape Communications Corporation. Java and the JavaScript
name are registered trademarks of Sun Microsystems, Inc. Adobe Acrobat is a registered
trademark of Adobe Systems, Inc.
Other products and brand names are trademarks of their respective owners.
Disclaimer
The service of equipment described herein is to be performed by qualified personnel who
are employed by Siemens or one of its affiliates or who are otherwise authorized by Siemens or one of its affiliates to provide such services.
Assemblers and other persons who are not employed by or otherwise directly affiliated
with or authorized by Siemens or one of its affiliates are directed to contact one of the
local offices of Siemens or one of its affiliates before attempting installation or service procedures.
License Agreement
All computer programs copyright 1990-2004 by Siemens Corporation or its suppliers. Programs are licensed under the following agreement:
Siemens or its suppliers retain(s) ownership of and title to any computer program supplied
with the equipment and to the trade secrets embodied in such computer programs. Subject to the Buyers acceptance and fulfillment of the obligations in this paragraph, Siemens
grants the Buyer a personal, non-transferable, perpetual, non-exclusive license to use any
computer program supplied with the Equipment that is necessary to operate the Equipment solely on the medium in which such program is delivered for the purpose of operating the equipment in accordance with the instructions set forth in the operators manuals
supplied with the Equipment and for no other purpose whatsoever. Buyer may not
reverse-assemble, reverse-compile or otherwise reverse-engineer such computer programs nor may Buyer make a copy of such program or apply any techniques to derive the
trade secrets embodied therein. In the event of a failure by Buyer to comply with the terms
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Revision / Disclaimer
of this license, the license granted by this paragraph shall terminate. Further, because
unauthorized use of such computer programs will leave Siemens without an adequate
remedy at law, Buyer agrees that injunctive or other equitable relief will be appropriate to
restrain such use, threatened or actual. Buyer further agrees that (i) any of Siemens"s
suppliers of software is a direct and intended beneficiary of this end-user sublicense and
may enforce it directly against Buyer with respect to software supplied by such supplier,
and (ii) No supplier of Siemens shall be liable to buyer for any general, special, direct, indirect, consequential, incidental or other damages arising out of the sublicense of the computer programs supplied with the equipment.
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1-
Table of Contents
0Table of Contents
11
11
23
28
36
36
36
38
43
51
61
61
72
75
83
84
85
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Table of Contents
VI memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Control DAC test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A2D Diag Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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Troubleshooting Guide
2-
Purpose
1Troubleshooting Guide
The purpose of this section is to identify the root cause of the error with the Antares system.
Begin with the (Troubleshooting Flowchart / p. 11). It guides the user through a series of
functional tests and diagnostic suggestions.
If the answer is Troubleshoot E Module, refer to the (E Module Troubleshooting
Process / p. 36). Use this section and the service manual to further troubleshoot other
system faults.
NOTICE
Antares
Acronym/Term
Definition
AC
aperture
apodization
beamformer
electronics responsible for combining signals (receive or transmit) from each transducer element into a single acoustic vector
axial direction
B-mode
BC-mode
BE
BP
Backplane
BP-mode
CB
CW Beamformer Board
CLA transducer
CP
Control Panel
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Acronym/Term
Definition
CW or CW Doppler
DGC
ECG
electrocardiogram
EM
E Module
ensemble
FE
frontend
FOV
field-of-view
FP
Front Panel
HDD
HW
hardware
HW/HW IDD
IO
Input/Output Board
IP
LA transducer
M-mode
Motion Mode
PA transducer
PY
Physio Module
PS
power supply
PSAC
PW or PW Doppler
RC
RM
ROI
region-of-interest
TEE
transesophageal transducer
TGC
THI
TI
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Troubleshooting Guide
Acronym/Term
Definition
TR
Transmit/Receive Board
RTC
VI
Video Input/Output
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Troubleshooting Guide
1. Power up the system and ensure that the system boots to imaging mode with a functional ultrasound image.
2. If the system does not boot to imaging, refer to the (Boot Sequence / p. 38) to determine possible defective EM boards.
3. If the service test tools are available, execute EM, PS and TI diagnostics.
4. If diagnostics fail, refer to (Appendix E: Test Descriptions / p. 61) and (Tab. 16 / p. 44) to
identify probable E Module board failures.
- If the diagnostic failure and the probable E Module board failure are related, then determine which board needs to be replaced.
- If the two are not related, two boards may need to replaced; one to fix the diagnostic
problem and the other to fix the boot problem. Refer to the (Tab. 17 / p. 47) to resolve
the failure.
To prevent the loss of system license information, replace only one board or one FRU at a
time and reboot after each task.
The applications license.dat file is maintained in four locations in the system:
RM board
TI board
Control Panel
Hard Drive
On each reboot, the license.dat file is pulled from each location and the stored licenses
are compared.
If there is any disagreement within the individual license file locations, the software will
use the license.dat information that receives the most matches from within these locations. If no two license.dat files match, the license.dat file becomes corrupted and must be
reloaded.
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Troubleshooting Guide
NOTE
TR0
TR1
TR2
RC
BE
VI
RM
CB (for future use)
The system serial number is determined by comparing the files stored on each reboot. A
serial number will be assigned if a majority of the compared files match.
If there is no majority from the files contained on the E Module boards, a secondary comparison will be performed from files stored on the TI Module, the Control Panel and the
Hard Drive.
If there is still no majority, the system will force the serial number to 99999 and will create
a license file for each board using the 99999 number.
If the system serial number is forced to 99999, escalate the problem to the Headquarters
Support Center (HSC) as soon as possible.
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11
Troubleshooting Flowchart
The system troubleshooting flowchart is designed as a closed loop. The main flowchart
branches to secondary flowcharts, each of which returns to the main flowchart for continued troubleshooting. With this method, fault conditions involving more than one error may
be resolved. The flowchart is not intended to resolve all possible fault conditions; it is
designed to resolve 80 percent of typical field situations.
Always start at the top and check each item in the CHECK column, which provides details
for each CHECK item. Any place on the flowchart which has an active link will be noted
with bold green text.As an example, a system does not boot correctly.Do not go directly to
the BOOTUP flowchart. First confirm power by checking the LEDs on the PSAC and I/O
modules. If these are all OK, and the monitor LED is on, proceed to the BOOTUP flowchart by clicking on the E, which will link to the section of the flowchart which deals specifically with BOOTUP troubleshooting. Follow the BOOTUP flowchart, then clicking the
F, which will follow the flowchart pattern back to the main flowchart. Confirm the remaining items in the flowchart to complete use of the troubleshooting flowchart.
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Troubleshooting Guide
Fig. 1:
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Fig. 2:
Fig. 3:
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Troubleshooting Guide
Fig. 4:
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Fig. 5:
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Troubleshooting Guide
Fig. 6:
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Fig. 7:
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Troubleshooting Guide
Fig. 8:
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Fig. 9:
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Troubleshooting Guide
Fig. 10:
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Fig. 11:
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Fig. 12:
Fig. 13:
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FRU
TP
Description
Comment
PSAC
48V output
See
(Fig. 14
/ p. 23)
Fan voltage (TP6 is only on PSAC units before M/N Tolerance: 45V +/- 1V
74 78 212.)
48V return
Signal ground
Test Point 1
Pos. 2
Test Point 2
Pos. 3
Test Point 3
Pos. 4
Test Point 4
Pos. 5
Test Point 5
Pos. 6
Transformeer Fuse F1
Pos. 7
Transformer Fuse F2
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Troubleshooting Guide
Tab. 2
FRU
TP
Description
Comment
PSA1
See
(Fig. 15
/ p. 25)
P14AQ
+14.2V +/- 5%
P5AQ
+5.0V +/- 5%
EBN
-3V +/- 5%
M9.6A
-9.6V +/- 5%
M2.0AQ
-2.2V +/- 5%
M100HV
+7.5V +/- 5%
M14AQ
-14.2V +/- 5%
VTX1
10
P7A
7.0V +/- 5%
11
P3.3A
+3.3V +/- 5%
12
P5A
+5.0V +/- 5%
13
P3.3AQ
+3.45V +/- 5%
14
P100HV
+3.87V +/- 5%
15
1. PSA test points are not labeled. Test point Number 1 is at the top.
Tab. 3
FRU
TP
Description
Comment
PSD1
See
(Fig. 15
/ p. 25)
M12D
-12V +/-5%
P12D
+12V +/-5%
P5D
+5.1 +/-5%
P3.3D
+3.4V +/-5%
+2.575 +/-5%
1. PSD test points are not labeled. Test point Number 1 is at the top.
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Troubleshooting Guide
Tab. 4
FRU
TP
Description
I/O
Module
Ground
I/O LED 7
I/O LED 8
I/O LED 9
+12V DP (HDD)
I/O LED 4
+5V DP (HDD)
I/O LED 3
+5V RDD
I/O LED 5
+12V RDD
I/O LED 6
+5V MIC
12
P2-5D
Not used
16
-12V
See
(Fig. 16
/ p. 26)
Comment
NOTE
Antares
The I/O Board test points are located behind the hard disk drive assembly.
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Tab. 5
27
FRU
LEDs
Description
I/O Module
LEDs
RM boot status
+5V HDD
+12V HDD
+5V RDD
+12V RDD
See
(Fig. 17 / p. 27)
When attempting to use the I/O Module LEDs to diagnose a problem, note that LED 1 will
be yellow during BIOS load and initialization of the system. It will change to solid green
when Windows starts loading.
LED 2 will flash yellow when any activity occurs on the hard drive.
LEDs 3-9 should be solid green, indicating voltages are present in the associated test
points.
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Troubleshooting Guide
Tab. 6
FRU
LED
Description
Control Panel
See
(Fig. 18 / p. 28)
Not Used
Not Used
FRU
Connector
Pin
Signal
AC transformer
primary
J50/P50
115/230 VAC
100 VAC
0 VAC
115/230 VAC
0 VAC
0 VAC
48V PS AC MAIN N
48V PS AC MAIN H
AC transformer
secondary
Antares
J49/P49
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29
FRU
Connector
Pin
Isolation transformer
PSA Power
PSD Power
PS Fans
J36/P36
J37/P37
J32/P32, J92/P92
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Signal
A1
48V_PSA
A2
48V_PSA_RET
A1
48V_PSD
A2
48V_PSD_RET
PFANS1
PFANS1 TACH
PFANS1 RET
PFANS2
PFANS2 TACH
PFANS2 RET
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Troubleshooting Guide
FRU
Connector
Pin
Signal
Main Fans
J31/P31, J91/P91
FANS1
FANS1 TACH
FANS1 RET
FANS2
FANS2 TACH
FANS3 RET
FANS3
FANS2 TACH
FANS3 RET
+4.8V (Red)
Hot (Brown)
Neutral (Blue)
Shield ground
+5V
+5V RET
+12V
+12V RET
1-5
+12V RDD
6-10
+5V RDD
13-15
+5V Fused
33, 34
Mic Power
35-39
40-44
Battery
Monitor AC
CP
P39
J41/P41, J63/P63
J52/P52
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FRU
Connector
Pin
Signal
HDD
J13/P13, J130/P130
+12V
+12V RET
+5V RET
+5V
+12V
+5V
+12V RET
+5V RET
+12V
+12V RET
+5V RET
+5V
+12V RET
+12V DC
RDD
P72
J133/P133, J135/P135
Physio module
J12A/P12A, J76/P76
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Troubleshooting Guide
Many system faults can be detected by viewing the AC Tray LED array located near the
circuit breaker on the rear of the Antares system. See (Fig. 19 / p. 32). The group of tables
located in (AC Tray LED Fault Indication tables / p. 32)will explain the AC Tray LED array
and what each fault indication pattern means.
LED Array
LED Meaning
LED Legend
1. PSA status
2. PSD status
3. 48V status
4. Main fans status
5. Power Supply fans status
6. AC Tray fans status
Battery Status
AC power status
In each of the next four sections, the Dont Care LED indicator means that the LED is not
relevant for the condition being described. The relevant error section should be used to
determine the meaning of the other LEDs. LED 1, 2 and 3 are described in the (Power
Supply Status / p. 34) section. LED 4, 5, and 6 are described in the (AC Tray Fan LED
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Status / p. 35) section. The (Battery Status / p. 33) and (AC LED Status / p. 33) are
described in individual sections. Any condition that causes a yellow LED to illuminate will
cause the system to shutdown.
AC LED Status
Tab. 9
AC LED Status
LED Pattern
Condition
Description
No AC Power
AC power available
Battery Status
Tab. 10
Battery Status
LED Pattern
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Medical Solutions USA, Inc.
Condition
Description
No Battery, or battery
malfunction
If the battery is present and correctly connected, this condition indicates that a fault
has been detected in the battery pack by the
charger. Otherwise this a normal condition.
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Troubleshooting Guide
Power Supply Status
Tab. 11
LED Pattern
Antares
Condition
Description
Standby
PSD started
AC Tray running
The PSD is overloading the 48V power supply. If condition continues, replace the PSD
The PSA is overloading the 48V power supply. If condition continues, replace the PSA
PSD Overload
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LED Pattern
35
Condition
Description
PSA Overload
LED Pattern
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Medical Solutions USA, Inc.
Condition
Description
Fans Running
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Troubleshooting Guide
Using this section assumes that troubleshooting has already been completed at the module level and the problem has been isolated to the E Module.
Stage Description
1
The CSE collects and analyzes imaging and other performance symptoms. These
will generally be reported by the customer, and later verified by the CSE at the site.
The E Module service test tools are used to provide additional information about E
Module performance. Using the combination of performance symptoms and test
data, the CSE assesses board defect possibilities, and determines a cost effective
strategy for ordering replacement boards.
The CSE accesses the E Module and makes one or more board replacements. Performance symptoms and diagnostic tests are rechecked to confirm effectiveness of
the changes.
The CSE conducts a comprehensive set of imaging tests to verify that the system is
operating correctly.
Troubleshooting Flowcharts
NOTE
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Troubleshooting Guide
Boot Sequence
(Tab. 14 / p. 38) shows the boot sequence for the Antares system software Rev 2.1 and
3.0 and potential problems that may occur during the sequence.
The table has four columns. The first column, Boot sequence progress, indicates the
approximate stage of the boot sequence.
The second column, Corresponding Expected Behavior/Indications, indicates what
should be happening in each stage of the sequence.
In the event that a condition described in the second column does not happen, refer to the
third column, Possible Causes of Unexpected Behavior, to determine a potential explanation for why the behavior did not occur.
The fourth column, Further evaluation, provides suggestions to follow which may help
identify the defective E Module board.
Tab. 14
Boot
sequence
progress
Corresponding
Expected Behavior/Indications
Standby Mode
AC PS supply (see
(Tab. 9 / p. 33))
Further evaluation
AC PS cooling fan
turns on (Note: Only
for ACPS without
Handles around the
breaker)
Powering Up
(user initiated)
Control Panel
Executing Self
test
Antares
LEDs on AC PS
turn on
EM cooling fans
turn on
To distinguish between BE
and VI; disconnect VI from
RM in reset condition (BIOS backplane and power on syserr LED on RM on; all others tem; if RM reset condition
off. See (Fig. 21 / p. 39)) due goes away VI is likely cause.
to BE, VI or RM board prob- Note: The BE cannot be disconnected in a similar manlem
ner, since removing the BE
will indicate to the AC PS that
a overtemp fault occurred
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Boot
sequence
progress
Corresponding
Expected Behavior/Indications
Further evaluation
Video initializing
LED on monitor
turns green
System emits
beep
RM Boot OK
RM or VI if screen is blank
LED is on
LED #1 on IO
changes from
amber to green
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Power LED
Pos. 2
Boot OK LED
Pos. 3
Pos. 4
Pos. 5
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Troubleshooting Guide
Boot
sequence
progress
Corresponding
Expected Behavior/Indications
Windows loading
Further evaluation
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Boot
sequence
progress
Corresponding
Expected Behavior/Indications
41
Further evaluation
Defective:
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Boot
sequence
progress
Corresponding
Expected Behavior/Indications
Further evaluation
System Ready
for Imaging
(Tab. 15 / p. 42) will show many of the common problems that occur during boot up and
the potential causes.
Tab. 15
Boot Problems
Symptom
Cause
VI board problem
blank screen
RM problem
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Symptom
43
Cause
The following troubleshooting table will show a number of potential problems and the test
that may help determine the problem. Always use the test tools for further troubleshooting.
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Troubleshooting Guide
Tab. 16
Board
Image Problem
TR
Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.
Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.
A single channel receive failure typically creates an artifact that is shaped like an arc
in normal or THI imaging
mode
Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.
Antares
Test
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Troubleshooting Suggestion
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Board
Image Problem
Test
Troubleshooting Suggestion
RC
RC memory
Receive test
B mode
BC mode
RC memory
Receive test
B mode
BC mode
RC memory
Receive test
B mode
BC mode
A2D Diag
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Board
Image Problem
Test
BE
B mode
Troubleshooting Suggestion
BC mode
Image problems that seem to BE memory
be digital - hard horizontal or B mode
vertical boundaries; blocks of
BC mode
colors; etc.
Radial line color noise
B mode
BC mode
Doppler problems
BE memory
M-mode problems
BE memory
Cine problems
BE memory
BE/VI
Audio problem
VI
no image
Color noise
Incorrect color (I.e, red
image)
Vertical lines in image
Doppler Auto stats overlay
problem
RM
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U78
Pos. 2
U79
Tab. 17
Image Problem
Board
Troubleshooting Suggestion
Problems in 8-channel
segments
TR
3D problems
RM
4D problems
RM
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Image Problem
Troubleshooting Guide
Board
Troubleshooting Suggestion
Problems in 64-channel
segments
TR
Arc-shaped artifact in
normal or THI imaging
mode
TR
Audio problem
BE, VI
Bands in image
RC
Cine problems
Test
BE memory
Color noise
Color noise on skinline
VI
A2D Diag
Color/Power outside
vessels or on bright
areas of B image, can
be intermittent due significant tendency on
temperature
Transmit test
Antares
BE
RC
RC
TR
Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Refer to
Antares (Channel Map / p. 51)and then
interchange TR boards. A TR-related
imaging fault will move with the associated TR as indicated by the channel
map.
VI
BE memory
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Image Problem
Test
Board
B mode, BC mode
tests
BE
Error message
TR, RC,
BE, VI
RC
Image break up
RM
RM
Incorrect color
VI
RC memory,
receive test, B
mode, BC mode
RC
RC
TR
M-mode problems
BE memory
Troubleshooting Suggestion
Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Refer to
Antares (Channel Map / p. 51)and then
interchange TR boards. A TR-related
imaging fault will move with the associated TR as indicated by the channel
map.
BE
No image
VI
RC
BE memory, b
mode, BC mode
tests
BE
B mode, BC mode
tests
BE
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Image Problem
Test
Board
Troubleshooting Suggestion
TR
System locks up
RM
RC memory,
receive test, B
mode, BC mode
RC, VI
Firmware failures
Firmware failures are logged in the fwlog.txt file located in the C:/syngo/log directory.
Always start at the end of the file to review the most current firmware information.
For firmware failures, the board where the failing device is located is the probable cause.
The board controlling the programming operation is the next probable - but less likely cause.
A firmware load/upgrade normally takes place if a new board, module or 4D transducer is
recognized. Firmware may also be upgraded as part of a software patch or combine code
load. For details on how to access a FW log, see (Appendix C: Examples of ImagingBE
and Firmware Logs / p. 56) and (Appendix D: How to Boot in Safe Mode / p. 59).
Tab. 18
Firmware Failures
Board
Device
BE
SIP DSP
RM and BE
SIP
BE
FPA
BE
FPB
BE
PCI
BE
DEC
BE
VI
ENC
ACLK
VCLK
Antares
RC
RTC
BE
TR
TR
BE
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Board
Device
TI
TI
BE
RM
Program BIOS
RM
Channel Map
The following figures show the Antares Channel map, from left to right. The map is broken
down into segments for ease of use.
Image channels from left to right refers to the channels displayed on the system monitor, from left to right. Channel 0 is the left-most channel while channel 191 is the
right-most for a 192-element transducer. Channel 32 is the left-most and channel 159 is
the right-most channel for a 128-element transducer.
Diagnostic channel references refers to the numbering system used in diagnostic test
results.
Transmit receive PWA (TR) identifies which TR board - TR0, TR1 or TR2 - corresponds
to a particular channel or set of channels.
TXPG ASIC identifies which TXPG ASIC corresponds to a particular channel or set of
channels.
Receive Beanformer (RXBF) ASIC identifies which RXBF ASIC corresponds to a particular channel or set of channels.
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An example of a test results and a test summary can be found in: (US03-101.840.71 /
System Logs.exe).
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The ImagingBE log will display test results. Any problems or faults will be noted in the log
and will be preceded by the word ERROR!
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Imaging Log
At each reboot, a new BE log is generated. ImagingBE.log is the log from last reboot. The
system saves up to 3 BE logs at a time. Scroll through the log and look for error indications.
An example of a BE log can be found in: (US03-101.840.71 / System Logs.exe).
The FW log gets updated every time a firmware load is executed. Typically, a firmware
load takes place if a new module or board is installed. The system checks the firmware
revision and loads new firmware if necessary.
A firmware load can take place if a 4D transducer is connected or a software patch or
combine code is installed.
If firmware is loaded or if an attempt is made to load firmware, information will be
appended to the fw log. The most recent information will be at the end of the log.
What to look for in a FW log
Firmware tests check to see if the correct firmware has been/is installed on the system. If
the test discovers that the fw is not current, it will search for the proper fw revision and
attempt to load the correct version. It will then attempt to verify that the correct firmware
was properly loaded. The firmware log will alert the CSE to the status of the firmware.
Firmware Log Example
The following information is an example of a firmware log pulled from an Antares system.
The log itself can also be found in: (US03-101.840.71 / System Logs.exe).
Firmware log
Mon Oct 04 15:33:57 2004
Zm System : Software Installed
Mon Oct 04 15:57:18 2004
Back End : Configuration mismatch Back End PCI FW rev expected 29.29, actual 29.22
Mon Oct 04 15:57:19 2004
Video Interface : Configuration mismatch Video Interface VCLK FW rev expected 5.0,
actual 4.0
Mon Oct 04 15:57:19 2004
Back End : Loading c:\zdt\program_PCI_29.29_0.sbs to Back End
Mon Oct 04 15:58:33 2004
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Wed Oct 06 10:37:12 2004
Back End : Verify c:\zdt\verify_FPA_4.5_1.sbs on Back End
Wed Oct 06 10:37:15 2004
Back End : Loading c:\zdt\program_PCI_29.29_0.sbs to Back End
Wed Oct 06 10:38:28 2004
Back End : Loading c:\zdt\program_PCI_29.29_1.sbs to Back End
Wed Oct 06 10:39:41 2004
Back End : Verify c:\zdt\verify_PCI_29.29_0.sbs on Back End
Wed Oct 06 10:39:44 2004
Back End : Verify c:\zdt\verify_PCI_29.29_1.sbs on Back End
Wed Oct 06 10:39:48 2004
Transducer Interface : Loading c:\zdt\program_TI_5.53_0.sbs to Transducer Interface
Wed Oct 06 10:41:01 2004
Transducer Interface : Verify c:\zdt\verify_TI_5.53_0.sbs on Transducer Interface
Wed Oct 06 10:41:04 2004
Realtime Manager : Loading c:\zdt\program_BIOS_1.0.7.bin to Realtime Manager
Wed Oct 06 10:41:27 2004
Realtime Manager : Verify c:\zdt\program_BIOS_1.0.7.bin on Realtime Manager
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NOTE
If this does not work, power down system and retry. Instead of
holding down the Ctl and Browser keys, hold down the Ctl key and
then quickly and continuously tap the Browser key.
NOTE
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3. Continue holding the key until the system starts beeping, then release the key.
4. A screen will come up asking how the system should be booted. Select Safe Mode
with a Command Prompt.
5. Press Enter on the keyboard
6. The system will ask which OS should be loaded. Choose MS Windows Professional and press Enter on the keyboard.
7. The system will boot to Safe Mode with a Command Prompt.
NOTE
Antares
After leaving Safe Mode and rebooting the system, the Antares will
not restore the BIOS defaults. Please re-enter the BIOS and change
the Clean Screen setting to Enable and the USB Legacy setting to
Disable.
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Back-end Board
Transmit Receive Board
Receive Control
The individually executable test functions and the FRUs they address are described in the
following outline.
Unless otherwise specified these tests require no external test equipment.
Front-end Segment
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Fig. 33: Test Coverage, Transmit Pulse Generator ASIC Memory Test
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This test will exercise the TXPG by generating only one 4.5 mhz pulse sequence per
channel after a maximum length channel delay.
Test Coverage - Transmit Pulse Generator ASIC Built-in Self-test
This test covers the TXPG internal logic and SRAM plus the TCBus interface to the TR
and the local uP bus.
Fig. 34: Test Coverage, Transmit Pulse Generator ASIC Built-in Self-test
Receive Test
A signal source on the RC is routed through the TI to all receive channels and sampled by
each RXBF ADC. Signal analysis on samples in each RXBF SRAM are used to verify
each receive channel.
Test Coverage - Receive Test
Coverage includes the RC boards FEBus interface, RTC, RXBFs, gain controls and
TCBus interface; the TR boards TCBus interface, receive amplifiers and signal paths and
gain controls; TI boards BIT test signal routing and internal power divider.
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Transmit Tests
The test will be done by transmitting on each channel in turn or multiple channels delayed
with increasing delay per channel and examining the signal received in the RXBF SRAM
of channel 16. This TRRCS channel can be connected to the TIRCMSR inputs which permit an independent signal path. The resistive power combiner on the TI board can be
directed to this measurement path. Signal analysis on these samples will verify that each
of the transmitters fire.
The transmit test must be executed twice, once for each of the 2 transmit voltage supplies.
Test Coverage - Transmit Tests
Coverage includes the RC boards FEBus interface, RTC, RXBF channel 16, and TCBus
interface; the TR boards TCBus interface, transmit pulsers and signal paths and transmit
voltage controls; TI boards BIT test signal routing and internal power combiner or the
external PCD.
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Continuous Wave IQ Phase and Gain Calibration Test
This test injects a signal from an external source into the CB boards Pencil Probe CW
input. The external source delivers a signal whos frequency is the current operating frequency plus two kilo Hertz. The CB board is properly set up for this mode of operation.
The signal is processed as a PPCW signal and IQ data is gathered at the SIP. The Baseband IQ data is analyzed for Phase difference and amplitude ratio. The phase difference
from exactly 90 deg of the Q data and the amplitude ratio of I/Q are saved and stored in
the CB boards IDProm. A calibration value for each operating frequency, each high pass
filter setting and each baseband gain setting is stored. The total number of values is 162
(9X2X9).
The Data that is stored in the CB board ID prom is made available to OPSW via a text file.
The text file is generated by the test and any time Zdt starts up and detects that the CB
Serial number has changed from the last time the file was generated. (The CB board
Serial number is imbedded in the file).
Test Coverage - Continuous Wave IQ Phase and Gain Calibration Test
The test covers the Pencil probe CW input amplifier, Frequency specific band pass filter
section, RF mixer section, base band gain section, the selectable high pass filter section,
the low pass anti-aliasing section and the Analog to Digital converter section.
Pencil Probe CW Receive Test
The Pencil probe CW receive test sets up the CB board from the test selectable operating
frequency, base band gain and high pass filter settings. The pseudo random signal generator resident on the RC board is used to inject a test signal into the Pencil Probe CW input
via the TI board diagnostic test circuit. IQ data is gathered at the SIP and Analyzed for signal level at a particular frequency. The raw time domain data is processed by a
Cooley-Tukey radix-2, DIF fft function. It provides a frequency resolution of 9.5367 Hz.
The pseudo random generated will provide frequency content that will span more than
one bin but will be consistent from machine to machine.
Steerable CW Receive Test
The Steerable CW receive test sets up the CB board from the test selectable operating
frequency, base band gain and high pass filter settings. The pseudo random signal generator resident on the RC board is used to inject a test signal into all of the TR RF signal
paths via the TI board diagnostic test circuit and power divider. IQ data is gathered at the
SIP and Analyzed for signal level at a particular frequency. The raw time domain data is
processed by a Cooley-Tukey radix-2, DIF fft function. It provides a frequency resolution of
9.5367 Hz. The pseudo random generated will provide frequency content that will span
more than one bin but will be consistent from machine to machine.
Pencil Probe CW Transmit Test
The Pencil Probe CW transmit test sets up the CB board from the test selectable operating frequency and transmits its CW signal to the TI board which as been configured to
direct the PPCW transmit to the TIRCMSR circuit. The data is gathered via TRRCS channel 16. The data is analyzed for power and compared to and expected absolute value.
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The Control Dac test exercises the TGC, AAC, TXV0, TXV1, PSMON0 and PSMON1 control dacs. Each dac output, or a derivative of it is available at the mux of each TR board.
For general tests related to the RC board the mux on the first TR board is used. For TR
board specific tests the mux on the Board under test is used.
The mux output drives the Diagnostic A2D converter on the RC board. Each dac is incremented over its entire range. The acquired values from the ADC are processed for Slope,
Offset and RMS deviation. Limits are applied to each of these values.
The PSMON0 and 1 dacs are not directly tested. These dacs are tested by setting the
PSMON dac then incrementing the TXV dac until the corresponding interrupt occurs. The
TXV value is acquired and when all PSMON values have been exercised then the same
Slope, Offset and RMS calculations and limits are applied. The Slope and Offset values
from the TXV test, which is always executed first, are used to minimize errors in this calculation.
Test Coverage - Control Dac Test
These tests exercise the RC board Dacs and ADC the TXV power supplies and Various
analog buffers on the RC and TR boards.
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Back-end Segment
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VPDM ASIC Memory Test - VI
Standard memory test performed on all testable registers and memory spaces in the VI
VPDM ASIC except for the external SDRAMs.
Test Coverage -VPDM ASIC Memory Test
The internal and external memory spaces in the VPDM ASIC and the VI local bus.
VPDM SDRAM Test - VI
Four memory tests are available for the external SDRAM associated with the VPDM. Two,
the Address Data Test and the Bank Address Test, are enabled by default but may be
optionally disabled for troubleshooting support. Two other tests, the Checkerboard Test 0
and Checkerboard Test 1, may be enabled for troubleshooting support.
Test Coverage -VPDM ASIC Memory Test
The Address Data Test accesses all memory locations the external SDRAM. The test
checks the operation of all address and data lines, and identifies row and column addressing errors. The test cannot identify bank addressing errors.
The Bank Address Test identifies bank addressing errors.
The two checkerboard tests may be used to write alternating ones and zeros to every bit
in SDRAM.
Each test returns up to 30 error messages identifying the SDRAM LUT index, the device,
bank, row, and column of the failing location, and the expected and actual data read from
the location.
Executes the CP power-on self test on the CP sub-processor and reads the result back.
The POST tests executed are:
CPU Check
RAM Check
Boot Block CkSum
App Code CkSum
Stuck Key
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The approach for each of the mode functional tests is to load a static test pattern into the
RXBF delay SRAMs and to program the entire system (excepting transmit channels) to
beamform and image this data in each of the specified modalities.
After a fixed number of frames the sequencer is stopped. Register data and CRC values
for memory data are examined to verify system operation in the specified imaging mode.
For each mode of operation a meaningful visual pattern is displayed on the system.
Register data and CRC values isolate the section of the EM that is responsible for a test
failure.
Tests are defined for the imaging modes listed below.
B-Mode
The test emulates B-Mode imaging operation for a C5-2 transducer set for maximum
depth and 4 parallel beams.
The test stimulus is a 2.2 Mhz sine wave pattern loaded into all RXBF Delay SRAMs.
Imaging is enabled for a fixed number of frames then halted. Register values are tested for
the RC board, for the VPSC ASIC on the BE board, and for the VPDM ASIC on the VI
board. When register values indicate successful operation, CRC values are calculated
from the following: Synthetic Aperture memories associated with all 4 DR ASICs on the
BE board, RP Raster memory associated with the VPSC ASIC on the BE board, and raster memory associated with the VPDM ASIC on the VI board. If register values indicate
that data were not processed as expected at any point, subsequent CRC values are not
calculated.
B-Mode System Test Coverage
The entire digital B-Mode data path is tested, from the RXBF ASICs on the RC board
through to the raster video area of SDRAM and the VPDM ASIC on the VI board.
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BC-Mode
The test emulates BC-Mode imaging operation for a C5-2 transducer with a color ROI set
for minimum width and maximum height.
The test stimulus is a 2.2 Mhz sine wave pattern loaded into all RXBF Delay SRAMs.
Imaging is enabled for a fixed number of frames then halted. Register values are tested for
the RC board, for the VPSC ASIC on the BE board, and for the VPDM ASIC on the VI
board. When register values indicate successful operation, CRC values are calculated
from the following: Synthetic Aperture memories associated with two DR ASICs on the BE
board, RP Raster memory associated with the VPSC ASIC on the BE board, and raster
memory associated with the VPDM ASIC on the VI board. If register values indicate that
data were not processed as expected at any point, subsequent CRC values are not calculated.
BC-Mode System Test Coverage
The entire digital BC-Mode data path is tested from the RXBF ASICs on the RC board
through to the raster video area of SDRAM and the VPDM ASIC on the VI board. Both the
echo path through the DR and EP ASICs and the flow path through the FP ASIC and FP
FPGA are evaluated.
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In this Stage, the higher level FRU diagnostic test suites can be run.
To access the diagnostic tests, a site-specific service access key Level 7 is needed. Service access keys for the Antares are based on the system serial number. The CSE or user
who requires a Service key obtains it through Service.
1. Select Presets from the imaging toolbar or from the keyboard.
2. Select Service
Fig. 51:
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Fig. 52:
4. The Service Authentication page appears. Enter the service access key and click OK.
The Service access key is a 20-digit alphanumeric password. The first 14 digits are
placed in the first field and the last six are placed in the second field. Clicking the Set as
Default box will save only the first 14 digits upon reboot. The final six must me entered
manually after each entrance to the local service page. if the Set as Default box is not
checked, the entire access key must be re-entered on reboot.
Fig. 53:
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5. The Service Home page appears. Click TestTools to go to the TestTools screen. A
message will appear saying: Please insure [sic] that all probes are disconnected and REMOVED from the three connectors of the system.
This is REQUIRED for tests to operate properly. Ensure that all transducers are disconnected from the transducer interface, then click OK.
6. The TestTools screen allows access to all of the higher level FRU tests, including the E
Module test, E Module board level tests, transducer interface test, Power Supply test,
Physio Module test, transducer tests and CD-ROM tests.
Fig. 54:
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7. Select Board Test, a sub-menu for E Module test. A new menu will appear which will
show all the available board tests.
8. Select the appropriate test and click Start to run the tests. An Estimated Time counter
shows approximately how much time is needed to complete the diagnostic tests. The
counter will count down during the tests, which is indicated by the letters dn next to the
timer. When the estimated time has been exceeded, the counter will start counting up,
indicated by the letters up.
Fig. 56:
9. After the tests are completed, scroll to the bottom of the scroll box and check the status
of the tests. If the test fails, a detailed report of the failure can be found on the Reports
page.
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Test target areas
The next section will show a series of tables which explain the tests performed in each
section of the system, which board is targeted in each section of the test and the primary
focus of that test. The tests will be executed as part of the board tests.
Tab. 19
TR Board
Test
RC Board
Test
E Module
Test
RC Memory
FE Memory
RC Cntrl Seq
RTC
RC Memory
FE Memory
RC Memory
FE Memory
TR Cntrl Seq
RTC
TR memory
FE Memory
TR memory
FE Memory
Receive Test
TR receive
Receiver
TI Module
Test
Receiver
TR transmit
TR Transmit
TR Diags
RC Diags
Refs
Refs
TI Memory
Probe Relay
Thermistor
Overcurrent Test
Overcurrent
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Tab. 20
93
Test Backend
BE
EM
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
BE Memory
Tab. 21
VI
EM
VI Memory
VI Memory
VI Memory
VI Memory
VI Memory
VI Memory
VI Memory
VI Memory
Tab. 22
Test
RC
BE
VI
EM
B Mode
B Mode
B Mode
B Mode
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Test
RC
BC-Mode
BE
VI
EM
BC Mode
BC Mode
BC Mode
Audio
Fig. 57:
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3. Find and click Test Results.htm in the Hierarchal listing to show a detailed report of
the test, which may be used for further troubleshooting.
Fig. 58:
4. If multiple TestResults.htm items appear in the log, use the date and time to determine which summary is the most recent.
NOTE
If the E Module test or any of the board tests fails, scroll through
the test results to identify which module/board is the root cause.
Use the information in (Appendix A: Test Results and Test
Summary / p. 54)
Transmit test
The transmit test exercises all 192 transmit circuits (EM level test) or all 64 transmit circuits (TR0, TR1, TR2 level tests). Antares has two transmit voltage sources (TXV0 and
TXV1). The transmit test uses TXV0 and then TXV1; the resulting sets of data (192 or 64
rows) are analyzed independently. The outputs of the transmit circuits on the TR board
are routed to the TI board where a resistor combiner combines the 192 or 64 channels
onto one signal line. This signal line is routed from the TI to the RC board. On the RC
board the signal is routed to the RXBF ASIC corresponding to channel 16 and the waveforms are stored in the SRAM of this ASIC. The stored SRAM data is then analyzed.
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Tab. 23
Failing EM
board type
Corresponding Image
indication
Troubleshooting Suggestion
TR
Refer to (Channel
Map / p. 51) to link failing
channel to TR board.
Refer to (Channel
Map / p. 51) to link failing
channel to TR board.
Typically 1 or 2 channels
out of range, or 8 consecutive channels corresponding to TXPG
groupings (refer to (Channel Map / p. 51))
All 192 channels failing
Absolute Median and
Mean Power Limits
RC
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Failing EM
board type
Corresponding Image
indication
TI
RM, BE, VI
Troubleshooting Suggestion
Receive Test
The receive test exercises all 192 receive circuits (EM/RC level test) or all 64 receive circuits (TR0, TR1, TR2 level tests). The receive test uses two gain settings (26 and 14); the
resulting two sets of data are analyzed independently. The RC board has a stimulus
source that is used for the receive test. This stimulus source is routed to the TI board
where a resistor divider distributes this stimulus to the 192 or 64 channels. From the TI,
these signals are routed to the TR where filtering and gain is applied. From the TR these
signals are routed to the RC board and then the waveforms are stored in the SRAM of
respective RXBF ASICs. The stored SRAM data is then analyzed.
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Tab. 24
Failing EM
board type
Corresponding
Image indication
Troubleshooting
Suggestion
TR
RC
RM, BE, VI
This test inputs a known set of data into the RC board and the system processes this data
from the RC through the DR, EP, and SC sections of the BE and then to the VI board. A
CRC is a method of detecting a 1 bit mismatch. Once a CRC fails, this failure will propagate through the remaining CRC checks. Thus the true failure information is contained in
the first failing CRC read from top to bottom.
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Tab. 25
99
Failing EM
board type
RC
BE
VI
False Failure
Corresponding
Image indication
Troubleshooting
Suggestion
This test inputs a known set of data into the RC board and the system processes this data
from the RC through the DR, EP, FP, and SC sections of the BE and then to the VI board.
A CRC is a method of detecting a 1 bit mismatch. Once a CRC fails, this failure will continue through the remaining CRC checks. Thus the true failure information is contained in
the first failing CRC.
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Tab. 26
Corresponding
Image indication
Troubleshooting
Suggestion
BE
VI
RTC Sequence Test (RC sequence, TR0 sequence, TR1 sequence, TR2
sequence)
RTC FPGA programs the TR boards and RXBF ASICs at high speed. The target registers and tables are first cleared. Patterns are stored in the RC index state machines
tables. A sequence is loaded that is expected to move the patterns out to the TXPG and
RXBF ASICs. The sequence is executed and the results verified.
Tab. 27
Corresponding
Image indication
Troubleshooting
Suggestion
RC
TR0
TR1
TR interchange; if
failure follows TR
with interchange then
TR board is source of
problem; if failure
does not move then
RC is source of problem
TR2
TI
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Failing EM Failing EM board data presentation
board type
RC
101
Corresponding
Image indication
Troubleshooting
Suggestion
Standard memory test performed on all testable registers and memory spaces in the frontend. Buses used are PCI bus between RM and BE; Febus between BE and RC, and
TCbus between RC and TR.
Tab. 28
Troubleshooting
Suggestion
RC
TR0
TR1
TR2
RM/BE
Damaged
connector
pin
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Troubleshooting Guide
Adjusts a system parameter, measures DC offset of all 192 channels and verifies that all
are within a set of test limits. The initial parameter adjustment is executed in the tune up
menu. The EM and individual board tests execute the a subsequent verification of limits.
Tab. 29
Failing EM
board type
Troubleshooting
Suggestion
TR
RC
TI
The probe relay test uses a test method similar to the receive test. Both use a stimulus
generated on the RC board and both route the signals for analysis through the TR to the
RC where the data is stored in the RXBF SRAM for analysis. The main difference is in the
routing of the stimulus on the TI board. For this test the stimulus is routed through the
relays on the TI board before being output to the TR boards.
Tab. 30
TR
TI
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Corresponding
Image indication
Troubleshooting
Suggestion
TR Swap
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BE memory
Standard memory test performed on all testable registers and memory spaces in the frontend. Buses used are PCI bus between RM and BE and local BE buses
Tab. 31
BE memory
Failing
Failing EM board data
EM board presentation
type
BE
VI memory
Standard memory test performed on all testable registers and memory spaces in the frontend. Buses used are PCI bus between RM and VI and local VI buses
Tab. 32
VI memory
Failing
Failing EM board data presentation
EM board
type
Corresponding
Image indication
VI
no image, incorrect
colors
Troubleshooting
Suggestion
The RC board contains the Digital to Analog Converters (DAC) used to control five variable voltages on the Antares system. The five voltages are VTGC, VFC, VMID, TXV0, and
TXV1. This test uses all possible digital inputs to the DACs in ascending order to produce
a ramp analog output. The test then analyzes the Slope (m), Offset (b), and RMS (standard error) for the resulting output (y=mx + b). For VTGC, VFC, and VMID these voltages
are routed from the RC to the TRs. From the TRs, these are routed to a separate measurement signal path that returns to the RC, where a serial Analog to Digital converter
(ADC) is used to measure voltages. For TXV0 and TXV1, the output of the DACs are
routed to the PSA and the resulting TXV0 and TXV1 voltages are routed from the PSA
back to the TRs. The same measurement path to the ADC is used for these voltages as
for the other three voltages. Pass/Fail criteria is based on the calculated Slope, Offset,
and RMS values. A TXV0 and TXV1 trip point test is also part of this test group. Plots of
the data are also displayed as part of the test.
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Tab. 33
Failing
Failing EM board data presentation
EM board
type
RC
Since the actual DACs and associated circuitry is contained on the RC board, the RC
board is a primary cause of failure for these
tests. Especially slope, offset and gross
RMS failures. The plots that deviate significantly from a straight line are usually indicative of a RC fault.
Corresponding
Image indication
Troubleshooting
Suggestion
Always use either
the EM test group
or TR0 test group
to execute the
Control DAC test.
The control DAC
test in the RC test
group does not
test all of the Control DAC circuitry.
PSA
TI
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The RC board has an ADC that is used to measure DC voltages in the system. For A2D
Diag test various system DC voltages on the RC board, the TR board, and the TI board
are routed via multiplexers to this ADC on the RC board. Some of these voltages are created on the PSA and PSD directly, while others are created using regulators on individual
boards.
Tab. 34
Failing
Failing EM board data presentation
EM board
type
RC
Corresponding
Image indication
Troubleshooting
Suggestion
TR
TI
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