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Antares

US

Troubleshooting Tools
System
System Troubleshooting

10032747
10032746
08653771
05936518

Siemens AG

Siemens Medical
Ultrasound
ejt
DivisionSolutions

Print No.: US03-101.840.01.02.02


Replaces: US03-101.840.01.01.02
Part No.:
sd

2003

The reproduction, transmission or use


of this document or its contents is not
permitted without express written
authority. Offenders will be liable for
damages. All rights, including rights
created by patent grant or registration
of a utility model or design, are
reserved.

English
Doc. Gen. Date: 10.05
n.a.

Revision / Disclaimer

1Revision / Disclaimer

Copyright
Copyright 2004 by Siemens Corporation. All rights reserved. No part of this publication
may be reproduced, transmitted, transcribed, stored in retrieval systems, or translated into
any language or computer language, in any form or by any means, electronic, mechanical,
magnetic, optical, chemical, manual, or otherwise, without the prior written permission of
Siemens Corporation. Siemens Corporation reserves the right to change its products and
services at any time. In addition, this manual is subject to change without notice. Siemens
Corporation welcomes customer input on corrections and suggestions for improvements
to this manual.Although Siemens Corporation has attempted to ensure accuracy throughout this manual, Siemens Corporation assumes no liability for any errors or omissions, nor
for any damages resulting from the application or use of this information.
Trademarks
ACUSON, Sequoia, Cypress, AEGIS, Aspen, 128XP, XP, AcuNav, CV70, SONOLINE,
Adara, Antares, G20, G40, G50, G60S, Omnia and KinetDx are trademarks of Siemens
Corporation registered in the U.S. Patent and Trademark Office. CWS3000, DS3000,
WS3000, and WebPro are trademarks of Siemens Corporation.
Windows XP, 2000 and NT are registered trademarks of Microsoft Corporation. Internet
Explorer is a trademark of Microsoft Corporation. Netscape and Netscape Navigator are
registered trademarks of Netscape Communications Corporation. Java and the JavaScript
name are registered trademarks of Sun Microsystems, Inc. Adobe Acrobat is a registered
trademark of Adobe Systems, Inc.
Other products and brand names are trademarks of their respective owners.
Disclaimer
The service of equipment described herein is to be performed by qualified personnel who
are employed by Siemens or one of its affiliates or who are otherwise authorized by Siemens or one of its affiliates to provide such services.
Assemblers and other persons who are not employed by or otherwise directly affiliated
with or authorized by Siemens or one of its affiliates are directed to contact one of the
local offices of Siemens or one of its affiliates before attempting installation or service procedures.
License Agreement
All computer programs copyright 1990-2004 by Siemens Corporation or its suppliers. Programs are licensed under the following agreement:
Siemens or its suppliers retain(s) ownership of and title to any computer program supplied
with the equipment and to the trade secrets embodied in such computer programs. Subject to the Buyers acceptance and fulfillment of the obligations in this paragraph, Siemens
grants the Buyer a personal, non-transferable, perpetual, non-exclusive license to use any
computer program supplied with the Equipment that is necessary to operate the Equipment solely on the medium in which such program is delivered for the purpose of operating the equipment in accordance with the instructions set forth in the operators manuals
supplied with the Equipment and for no other purpose whatsoever. Buyer may not
reverse-assemble, reverse-compile or otherwise reverse-engineer such computer programs nor may Buyer make a copy of such program or apply any techniques to derive the
trade secrets embodied therein. In the event of a failure by Buyer to comply with the terms

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Revision / Disclaimer

of this license, the license granted by this paragraph shall terminate. Further, because
unauthorized use of such computer programs will leave Siemens without an adequate
remedy at law, Buyer agrees that injunctive or other equitable relief will be appropriate to
restrain such use, threatened or actual. Buyer further agrees that (i) any of Siemens"s
suppliers of software is a direct and intended beneficiary of this end-user sublicense and
may enforce it directly against Buyer with respect to software supplied by such supplier,
and (ii) No supplier of Siemens shall be liable to buyer for any general, special, direct, indirect, consequential, incidental or other damages arising out of the sublicense of the computer programs supplied with the equipment.

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4
1-

Table of Contents
0Table of Contents

1 _______ Troubleshooting Guide ___________________________________________ 6


Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Acronyms and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Basic Troubleshooting steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Rules for Interchanging Boards/Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Troubleshooting Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC/DC Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11
11
23
28

AC Tray LED Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32


AC Tray LED Fault Indication tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Troubleshooting the E Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
E Module Troubleshooting Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Troubleshooting Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Troubleshooting basic imaging problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36
36
36
38
43
51

Appendix A: Test Results and Test Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54


Appendix B: How to Access ImagingBE and Firmware Logs . . . . . . . . . . . . . . . . . . . . . 55
What to look for in a ImagingBElog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Appendix C: Examples of ImagingBE and Firmware Logs . . . . . . . . . . . . . . . . . . . . . . . 56
Imaging Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Firmware (FW) Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Appendix D: How to Boot in Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Appendix E: Test Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Front-end Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Dac Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Back-end Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Video Interface Segment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Panel Tests - CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Level Tests - RC, BE, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

61
61
72
75
83
84
85

Appendix F: Board Tests and Related Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88


Diagnostic Test Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Transmit test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Receive Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Zm System B-Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Zm System BC-Mode Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
RTC Sequence Test (RC sequence, TR0 sequence, TR1 sequence, TR2 sequence)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
FE memory (includes RC memory, TR0 memory, TR1 memory, TR2 memory). . . 101
DC cal/DC cal check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Probe Relay test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
BE memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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VI memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Control DAC test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
A2D Diag Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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Troubleshooting Guide

2-

Purpose
1Troubleshooting Guide

The purpose of this section is to identify the root cause of the error with the Antares system.
Begin with the (Troubleshooting Flowchart / p. 11). It guides the user through a series of
functional tests and diagnostic suggestions.
If the answer is Troubleshoot E Module, refer to the (E Module Troubleshooting
Process / p. 36). Use this section and the service manual to further troubleshoot other
system faults.

NOTICE

When an E Module board is replaced, an E Module test must be


performed.
When the troubleshooting is finished, the system will
prompt the user to execute a module test on every reboot
until the E Module test has been executed.

Acronyms and Terms

Antares

Acronym/Term

Definition

AC

AC tray; also referred to as PSAC Tray

aperture

number of active transducer elements, or transducer width, during transmit or receive

apodization

amplitude weighting function applied across the active transducer aperture

beamformer

electronics responsible for combining signals (receive or transmit) from each transducer element into a single acoustic vector

axial direction

along the acoustic vector

B-mode

two dimensional brightness mode display

BC-mode

B-mode with a color flow ROI

BE

backend or Backend Board

BP

Backplane

BP-mode

B-mode with power mode ROI

CB

CW Beamformer Board

CLA transducer

curved linear array transducer

CP

Control Panel

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Acronym/Term

Definition

CW or CW Doppler

continuous wave Doppler

DGC

depth gain compensation (same as TGC)

ECG

electrocardiogram

EM

E Module

ensemble

set of color flow vectors from a single direction used to estimate


flow

FE

frontend

FOV

field-of-view

FP

Front Panel

HDD

Hard Disk Drive

HW

hardware

HW/HW IDD

specifies signal characteristics of hardware-to-hardware interfaces

IO

Input/Output Board

IP

Image Processor Board

LA transducer

linear array transducer

M-mode

Motion Mode

PA transducer

phased array transducer: element spacing is no greater than


half-wavelength

PY

Physio Module

PS

power supply

PSAC

Power Supply AC tray; also referred to as AC Tray

PW or PW Doppler

pulsed wave Doppler

RC

Receive Beamformer and Controller Board

RM

CPU Real-time Manager

ROI

region-of-interest

TEE

transesophageal transducer

TGC

time gain compensation

THI

Tissue harmonic Imaging

TI

transducer interface, Transducer Interface Board

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Troubleshooting Guide
Acronym/Term

Definition

TR

Transmit/Receive Board

RTC

Real Time Controller

VI

Video Input/Output

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Troubleshooting Guide

Basic Troubleshooting steps

1. Power up the system and ensure that the system boots to imaging mode with a functional ultrasound image.
2. If the system does not boot to imaging, refer to the (Boot Sequence / p. 38) to determine possible defective EM boards.
3. If the service test tools are available, execute EM, PS and TI diagnostics.
4. If diagnostics fail, refer to (Appendix E: Test Descriptions / p. 61) and (Tab. 16 / p. 44) to
identify probable E Module board failures.
- If the diagnostic failure and the probable E Module board failure are related, then determine which board needs to be replaced.
- If the two are not related, two boards may need to replaced; one to fix the diagnostic
problem and the other to fix the boot problem. Refer to the (Tab. 17 / p. 47) to resolve
the failure.

Rules for Interchanging Boards/Modules


NOTICE

The system license information will be corrupted if multiple


boards/modules are replaced/interchanged at the same time.
A corrupt license file will result in the loss of optional features and
system imaging functionality.
To minimize this risk, only replace one board or module
at a time and perform a system reboot each time.

To prevent the loss of system license information, replace only one board or one FRU at a
time and reboot after each task.
The applications license.dat file is maintained in four locations in the system:

RM board
TI board
Control Panel
Hard Drive

On each reboot, the license.dat file is pulled from each location and the stored licenses
are compared.
If there is any disagreement within the individual license file locations, the software will
use the license.dat information that receives the most matches from within these locations. If no two license.dat files match, the license.dat file becomes corrupted and must be
reloaded.

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Troubleshooting Guide
NOTE

Interchanging two TR boards in the E Module for image testing or


other purposes will not corrupt the license.dat file or the system
serial number.

System Serial Number


The system serial number of the Antares system is stored and maintained on a series of
boards within the E Module.

TR0
TR1
TR2
RC
BE
VI
RM
CB (for future use)

The system serial number is determined by comparing the files stored on each reboot. A
serial number will be assigned if a majority of the compared files match.
If there is no majority from the files contained on the E Module boards, a secondary comparison will be performed from files stored on the TI Module, the Control Panel and the
Hard Drive.
If there is still no majority, the system will force the serial number to 99999 and will create
a license file for each board using the 99999 number.
If the system serial number is forced to 99999, escalate the problem to the Headquarters
Support Center (HSC) as soon as possible.

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Troubleshooting Guide

11

Troubleshooting Flowchart

The system troubleshooting flowchart is designed as a closed loop. The main flowchart
branches to secondary flowcharts, each of which returns to the main flowchart for continued troubleshooting. With this method, fault conditions involving more than one error may
be resolved. The flowchart is not intended to resolve all possible fault conditions; it is
designed to resolve 80 percent of typical field situations.

Using the Flowchart

Always start at the top and check each item in the CHECK column, which provides details
for each CHECK item. Any place on the flowchart which has an active link will be noted
with bold green text.As an example, a system does not boot correctly.Do not go directly to
the BOOTUP flowchart. First confirm power by checking the LEDs on the PSAC and I/O
modules. If these are all OK, and the monitor LED is on, proceed to the BOOTUP flowchart by clicking on the E, which will link to the section of the flowchart which deals specifically with BOOTUP troubleshooting. Follow the BOOTUP flowchart, then clicking the
F, which will follow the flowchart pattern back to the main flowchart. Confirm the remaining items in the flowchart to complete use of the troubleshooting flowchart.

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Troubleshooting Guide

Fig. 1:

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Fig. 2:

Fig. 3:

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Troubleshooting Guide

Fig. 4:

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Fig. 5:

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Troubleshooting Guide

Fig. 6:

Antares

P10 Connector into J10 Connection

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Fig. 7:

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Troubleshooting Guide

Fig. 8:

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Fig. 9:

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Troubleshooting Guide

Fig. 10:

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Fig. 11:

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Troubleshooting Guide

Fig. 12:

Fig. 13:

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Troubleshooting Guide

23

Power Test Points


Tab. 1

PSAC Power Test Points

FRU

TP

Description

Comment

PSAC

48V output

Tolerance: 47V +/- 1V

See
(Fig. 14
/ p. 23)

Fan voltage (TP6 is only on PSAC units before M/N Tolerance: 45V +/- 1V
74 78 212.)

48V return

Signal ground

ACRMVRS (Power for LAN and start-up circuitry.)

Tolerance: 5.0V +/- 0.2V

ACRMMSV (Standby power to keep DRAM alive.)

Tolerance: 5.0V +/- 0.2V

Fig. 14: AC Tray (PSAC) Test Points and Transformer Fuses


Pos. 1

Test Point 1

Pos. 2

Test Point 2

Pos. 3

Test Point 3

Pos. 4

Test Point 4

Pos. 5

Test Point 5

Pos. 6

Transformeer Fuse F1

Pos. 7

Transformer Fuse F2

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Troubleshooting Guide
Tab. 2

PSA Power Test Points

FRU

TP

Description

Comment

PSA1

VTX0 (TP at top)

0 - 18.5V (C-, P-, D-mode)

See
(Fig. 15
/ p. 25)

P14AQ

+14.2V +/- 5%

P5AQ

+5.0V +/- 5%

EBN

-3V +/- 5%

M9.6A

-9.6V +/- 5%

M2.0AQ

-2.2V +/- 5%

M100HV

+7.5V +/- 5%

M14AQ

-14.2V +/- 5%

VTX1

0 - 18.5V (B-, M-mode)

10

P7A

7.0V +/- 5%

11

P3.3A

+3.3V +/- 5%

12

P5A

+5.0V +/- 5%

13

P3.3AQ

+3.45V +/- 5%

14

P100HV

+3.87V +/- 5%

15

Ground (TP at bottom)

1. PSA test points are not labeled. Test point Number 1 is at the top.
Tab. 3

PSD Power Test Points

FRU

TP

Description

Comment

PSD1

Ground (TP at top)

See
(Fig. 15
/ p. 25)

M12D

-12V +/-5%

P12D

+12V +/-5%

P5D

+5.1 +/-5%

P3.3D

+3.4V +/-5%

P2.5D (TP at bottom)

+2.575 +/-5%

1. PSD test points are not labeled. Test point Number 1 is at the top.

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Fig. 15: PSA and PSD test points


Pos. PSD 1 PSD Test Point 1 (top)
Pos. PSD 6 PSD TEst Point 6 (bottom)
Pos. PSA 1 PSA Test Point 1 (top)
Pos. PSA 14PSA Test Point 14
Pos. PSA 15PSA Test Point 15 - ground (bottom)

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Troubleshooting Guide
Tab. 4

I/O Board Test Points

FRU

TP

Description

I/O
Module

Ground

+3.3VF (Control Panel)

I/O LED 7

+5VF (Control Panel & Front Connector Panel)

I/O LED 8

+12VF (Control Panel)

I/O LED 9

+12V DP (HDD)

I/O LED 4

+5V DP (HDD)

I/O LED 3

+5V RDD

I/O LED 5

+12V RDD

I/O LED 6

+5V MIC

12

P2-5D

Not used

16

-12V

I/O Module only

See
(Fig. 16
/ p. 26)

Comment

Fig. 16: I/O Board Test Points

NOTE

Antares

The I/O Board test points are located behind the hard disk drive assembly.

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Tab. 5

27

I/O Module LEDs

FRU

LEDs

Description

I/O Module
LEDs

RM boot status

HDD disk access

+5V HDD

+12V HDD

+5V RDD

+12V RDD

+3.3VF Control Panel

+5VF Control Panel & Front Connector Panel

+12VF Control Panel

See
(Fig. 17 / p. 27)

When attempting to use the I/O Module LEDs to diagnose a problem, note that LED 1 will
be yellow during BIOS load and initialization of the system. It will change to solid green
when Windows starts loading.
LED 2 will flash yellow when any activity occurs on the hard drive.
LEDs 3-9 should be solid green, indicating voltages are present in the associated test
points.

Fig. 17: I/O Module LEDs

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Troubleshooting Guide
Tab. 6

Control Panel LEDs

FRU

LED

Description

Control Panel

Keyboard USB connection

See
(Fig. 18 / p. 28)

Control Panel USB connection

Not Used

Not Used

LEDs 1 and 2 will be flashing under normal operation.

Fig. 18: Control Panel LEDs

AC/DC Power Connections


Tab. 7

AC/DC Power Connections

FRU

Connector

Pin

Signal

AC transformer
primary

J50/P50

115/230 VAC

100 VAC

0 VAC

115/230 VAC

0 VAC

0 VAC

48V PS AC MAIN N

48V PS AC MAIN H

AC transformer
secondary

Antares

J49/P49

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29

FRU

Connector

Pin

Isolation transformer

J41 Monitor AC fused at F1 1

216 VAC, not switched

216 VAC, not switched

Safety ground to monitor and system chassis

Shelled drain to chassis

J35 OEM AC fused at F2

PSA Power

PSD Power

PS Fans

J36/P36

J37/P37

J32/P32, J92/P92

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Medical Solutions USA, Inc.

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Signal

115/230V selectable AC outlet

A1

48V_PSA

A2

48V_PSA_RET

A1

48V_PSD

A2

48V_PSD_RET

PFANS1

PFANS1 TACH

PFANS1 RET

PFANS2

PFANS2 TACH

PFANS2 RET

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Troubleshooting Guide

FRU

Connector

Pin

Signal

Main Fans

J31/P31, J91/P91

FANS1

FANS1 TACH

FANS1 RET

FANS2

FANS2 TACH

FANS3 RET

FANS3

FANS2 TACH

FANS3 RET

+4.8V (Red)

+4.8V RET (Black)

Hot (Brown)

Neutral (Blue)

Safety ground (Grn/Yel)

Shield ground

+5V

+5V RET

+12V

+12V RET

1-5

+12V RDD

6-10

+5V RDD

13-15

+5V Fused

33, 34

Mic Power

35-39

+12V RDD RET

40-44

+5V RDD RET

Battery

Monitor AC

CP

P39

J41/P41, J63/P63

J52/P52

Front Connector J11A/P11A, J67/P67


Panel

Antares

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31

FRU

Connector

Pin

Signal

HDD

J13/P13, J130/P130

+12V

+12V RET

+5V RET

+5V

+12V

+5V

+12V RET

+5V RET

+12V

+12V RET

+5V RET

+5V

+12V RET

+12V DC

RDD

P72

J133/P133, J135/P135

Physio module

J12A/P12A, J76/P76

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32

Troubleshooting Guide

AC Tray LED Faults

Many system faults can be detected by viewing the AC Tray LED array located near the
circuit breaker on the rear of the Antares system. See (Fig. 19 / p. 32). The group of tables
located in (AC Tray LED Fault Indication tables / p. 32)will explain the AC Tray LED array
and what each fault indication pattern means.

Fig. 19: LED Fault indication panel

AC Tray LED Fault Indication tables


Tab. 8

AC Tray LED Description

LED Array

LED Meaning

LED Legend

1. PSA status
2. PSD status
3. 48V status
4. Main fans status
5. Power Supply fans status
6. AC Tray fans status
Battery Status
AC power status
In each of the next four sections, the Dont Care LED indicator means that the LED is not
relevant for the condition being described. The relevant error section should be used to
determine the meaning of the other LEDs. LED 1, 2 and 3 are described in the (Power
Supply Status / p. 34) section. LED 4, 5, and 6 are described in the (AC Tray Fan LED

Antares

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Status / p. 35) section. The (Battery Status / p. 33) and (AC LED Status / p. 33) are
described in individual sections. Any condition that causes a yellow LED to illuminate will
cause the system to shutdown.
AC LED Status
Tab. 9

AC LED Status

LED Pattern

Condition

Description

No AC Power

AC Power is not available. This could be


caused by the absence of wall power, the
cord, the AC tray circuit breaker being open,
the AC tray or the isolation transformer.

AC power available

AC Power is available. This is a normal condition

Battery Status
Tab. 10

Battery Status

LED Pattern

Siemens
Medical Solutions USA, Inc.

Condition

Description

No Battery, or battery
malfunction

If the battery is present and correctly connected, this condition indicates that a fault
has been detected in the battery pack by the
charger. Otherwise this a normal condition.

The battery is charging

This condition indicates the battery is in a


discharge/charge cycle.

The battery is charged

A full or partially charged battery is installed


in the system.

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34

Troubleshooting Guide
Power Supply Status
Tab. 11

Power Supply Status

LED Pattern

Antares

Condition

Description

Standby

The power supply is in standby mode, waiting for a power up command.

48V supply started

This condition lasts for 1.2 seconds during


power up. It indicates the 48V power supply
successfully started. If this condition is not
exited in 5 seconds a fault condition will be
displayed

PSD started

This condition lasts for less than 1 second


during power up. It follows It indicates the
48V power supply successfully started. If
this condition is not exited in 5 seconds a
fault condition will be displayed

AC Tray running

This is the normal state of the AC Tray when


the system is running

48V Internal Fault

The AC Tray 48V power supply has


reported an error. This includes undervoltage, overvoltage or over temperature. If
condition continues replace the AC Tray

PSD Internal Fault

The PSD has reported an internal error.


This includes undervoltage, overvoltage or
over temperature. If condition continues
replace the PSD

PSA Internal Fault

The PSA has reported an internal error. This


includes undervoltage, overvoltage or over
temperature. If condition continues replace
the PSA

PSD 48V Overload

The PSD is overloading the 48V power supply. If condition continues, replace the PSD

PSA 48V Overload

The PSA is overloading the 48V power supply. If condition continues, replace the PSA

PSD Overload

One of the PSD outputs is overloaded. This


can be caused by the EM, IO, TI, CP, UFP,
RMM, or HDD.

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LED Pattern

35

Condition

Description

PSA Overload

One of the PSA outputs is overloaded. This


can be caused by the EM, IO, TI, CP, UFP,
RMM, or HDD.

BE board not installed


An EM overheat sensor has not been implein EM (Formerly System mented. The Active high line is currently
Overheat)
grounded on the BE board. If the BE board
is removed from the EM card cage, the AC
tray will not allow the system to power on
and will display this LED pattern.
AC Tray Fan LED Status
Tab. 12

Fan LED Status

LED Pattern

Siemens
Medical Solutions USA, Inc.

Condition

Description

Fans Running

All fans are running normally

AC Tray Fans Stopped

The fan in the AC Tray has stopped. If this


condition continues replace the AC Tray

Power Supply fans


stopped

One or more of the power supply fans is


slow or stopped. If this condition continues
replace the power supply fan assembly

Main fans stopped

One or more of the main fans is slow or


stopped. If this condition continues replace
the main fan assembly

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Troubleshooting Guide

Troubleshooting the E Module

Using this section assumes that troubleshooting has already been completed at the module level and the problem has been isolated to the E Module.

E Module Troubleshooting Process

Troubleshooting the Antares Ultrasound E Module consists of observing symptoms and


test data, identifying the likely cause, replacing potentially defective boards, and verifying
that the module and system have been repaired.
Tab. 13

Stages of E Module Troubleshooting

Stage Description
1

The CSE collects and analyzes imaging and other performance symptoms. These
will generally be reported by the customer, and later verified by the CSE at the site.

The E Module service test tools are used to provide additional information about E
Module performance. Using the combination of performance symptoms and test
data, the CSE assesses board defect possibilities, and determines a cost effective
strategy for ordering replacement boards.

The CSE accesses the E Module and makes one or more board replacements. Performance symptoms and diagnostic tests are rechecked to confirm effectiveness of
the changes.

The CSE conducts a comprehensive set of imaging tests to verify that the system is
operating correctly.

Troubleshooting Flowcharts
NOTE

Antares

Always disconnect the quickstart backup battery, if installed, before troubleshooting.

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Medical Solutions USA, Inc.

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37

Antares

Fig. 20: Troubleshooting Process Flowchart

38

Troubleshooting Guide

Boot Sequence

(Tab. 14 / p. 38) shows the boot sequence for the Antares system software Rev 2.1 and
3.0 and potential problems that may occur during the sequence.
The table has four columns. The first column, Boot sequence progress, indicates the
approximate stage of the boot sequence.
The second column, Corresponding Expected Behavior/Indications, indicates what
should be happening in each stage of the sequence.
In the event that a condition described in the second column does not happen, refer to the
third column, Possible Causes of Unexpected Behavior, to determine a potential explanation for why the behavior did not occur.
The fourth column, Further evaluation, provides suggestions to follow which may help
identify the defective E Module board.
Tab. 14

Boot Sequence troubleshooting chart

Boot
sequence
progress

Corresponding
Expected Behavior/Indications

Possible Causes of Unexpected Behavior

Standby Mode

LEDs on UFP and


monitor turn amber

AC PS supply (see
(Tab. 9 / p. 33))

Further evaluation

AC PS cooling fan
turns on (Note: Only
for ACPS without
Handles around the
breaker)
Powering Up
(user initiated)

Control Panel
Executing Self
test

Antares

LEDs on AC PS
turn on

Fault condition detected by


AC PS (see (Tab. 9 / p. 33))

LED on UFP turns


green

BE board in EM is disconnected from backplane

EM cooling fans
turn on

System stops after 2 to 3


seconds.

To distinguish between BE
and VI; disconnect VI from
RM in reset condition (BIOS backplane and power on syserr LED on RM on; all others tem; if RM reset condition
off. See (Fig. 21 / p. 39)) due goes away VI is likely cause.
to BE, VI or RM board prob- Note: The BE cannot be disconnected in a similar manlem
ner, since removing the BE
will indicate to the AC PS that
a overtemp fault occurred

Control Panel emits Control Panel fault


beep

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39

Boot
sequence
progress

Corresponding
Expected Behavior/Indications

Possible Causes of Unexpected Behavior

Further evaluation

Video initializing

LED on monitor
turns green

Incorrect video signal or


missing sync

If it is the VI, the RM may


continue with the boot process as indicated by RM
POST LED #1 on IO and
accesses to Hard Drive LED
#2 on IO

RM BIOS starts Antares splash


executing
screen is displayed
POST
RM BIOS finished executing POST

System emits
beep

RM Boot OK

RM or VI if screen is blank

RM if splash screen remains Reseat RM


on screen and LEDs do not
change appropriately

LED is on

LED #1 on IO
changes from
amber to green

Fig. 21: RM Board LEDs


Pos. 1

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Power LED

Pos. 2

Boot OK LED

Pos. 3

BIOS ERR LED

Pos. 4

IDE ACT LED

Pos. 5

SCSI ACT LED

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Troubleshooting Guide

Boot
sequence
progress

Corresponding
Expected Behavior/Indications

Possible Causes of Unexpected Behavior

Windows loading

For 2.1.032 stanRM or HDD


dard windows
screen sequence
prior to Syngo count

Further evaluation

For 3.0.094A splash


screen remains on
screen after RM
POST is completed
until Syngo count
starts
Antares Syngo
test tools available

System emits three


clicks

The three clicks indicate a


system reset initiated by the
system after the RM was
able to communicate with all
EM boards and the TI module. The absence of three
clicks could be indicative of
problem with any of these
boards:
RM, VI, BE, RC, TR0, TR1,
TR2, TI

Antares

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Check error messages and


ImagingBE.log, ImagingBE.1.log and ImagingBE.2.log in C:/Syngo/log
directory. See (Appendix B:
How to Access ImagingBE
and Firmware Logs / p. 55)
and (Appendix C: Examples
of ImagingBE and Firmware
Logs / p. 56) for help on how
to access the logs. Use
Escape to OS and
Explorer.exe; Windows safe
mode; or log extract utility to
access these log files

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Boot
sequence
progress

Corresponding
Expected Behavior/Indications

Syngo loading, Syngo count and


Hardware and imaging screens
Firmware con- appear.
figuration check
and Imaging
application
loading. If a
firmware mismatch is
detected, then
a firmware load
will occur followed by a
shutdown.

41

Possible Causes of Unexpected Behavior

Further evaluation

Defective:

Check error messages and


ImagingBE.log, ImagingBE.1.log and ImagingBE.2.log in C:/Syngo/log
directory and call UPTIME
service center (USC). Use
Escape to OS and
Explorer.exe; Windows safe
mode; or log extract utility to
access these log files

RM, VI, BE, RC, TR0, TR1,


TR2, TI

Firmware load problems.


Firmware load failures usually can be traced to the
board where the firmware
load is failing. (Refer to
(Tab. 18 / p. 50))

If LED on RC board is off,


then RTC device has firmware problems.

Check error messages and


fwlog.txt C:/Syngo/log directory to identify failing compoThe circuit that controls data nent and board location. See
transfer for firmware loading (Appendix C: Examples of
ImagingBE and Firmware
is on the BE board, so the
BE board is capable of caus- Logs / p. 56) and (Appendix
D: How to Boot in Safe
ing firmware load problems
Mode / p. 59)
on other boards.
Run a board test to identify
defective boards if the tests
are available.

Fig. 22: RC Board LED


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Troubleshooting Guide

Boot
sequence
progress

Corresponding
Expected Behavior/Indications

Possible Causes of Unexpected Behavior

Further evaluation

System Ready
for Imaging
(Tab. 15 / p. 42) will show many of the common problems that occur during boot up and
the potential causes.
Tab. 15

Boot Problems

Symptom

Cause

Press Power On and system exhibits no response

AC tray is responding to a fault by not allowing system to boot

Press Power On and system starts to respond but


RM is in reset
stops after 2 to 3 seconds; RM BIOS error indicator is
VI is keeping RM in reset by not releasing
on; monitor led is green
ACRM-PSS line
BE is keeping RM in reset by not releasing
ACRM-PSS line
Blank screen, monitor led is amber, RM proceeds
through the standard POST process

VI board problem

System proceeds through boot up process, syngo


counts from 1 through 99, standard overlay information from RM is present on the screen; but no ultrasound information is displayed. ImagingBE.log file
indicates BE driver install failure. Only shutdown or
cancel options are displayed when turning off system, instead of the normal standby, shutdown, or
cancel

BE PCI bridge is not functional

blank screen

RM problem

LED #1 on I/O Board does not change from amber to


green
Hangs on a Windows Bar (Rev 2.1.032)
Hangs after I/O Board LED #1 transition to green but
before Syngo count starts (Rev 3.0)
Monitor LED does not change to green
Video problem early in the boot or with the overlay
information

Antares

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Symptom

43
Cause

Error message on screen or ImagingBE.log indicates RM is cause of error message


error
BE is cause of error message
See (Appendix C: Examples of ImagingBE and FirmTR is cause of error message
ware Logs / p. 56)and (Appendix D: How to Boot in
Safe Mode / p. 59) for more details.
RC is cause of error message
TI is cause of error message
System shuts down during boot up

PSA or PSD Fault is detected by AC tray.


See (Tab. 9 / p. 33)

No operating system found error message

IO module/EM connection problem


HDD problem

Troubleshooting basic imaging problems

The following troubleshooting table will show a number of potential problems and the test
that may help determine the problem. Always use the test tools for further troubleshooting.

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Troubleshooting Guide
Tab. 16

Board vs. Image problem

Board

Image Problem

TR

In general TR board image


problems will be related to a
single channel, a group of 8
channels, or a group of 64
channels. Refer to the
(Channel Map / p. 51) for how
TR channels map to the
image.

Refer to Antares (Channel


Map / p. 51)and then interchange TR
boards. A TR-related imaging fault will
move with the associated TR as indicated
by the channel map.

A single channel or multiple


Transmit Test
channel transmit failure will
create a dead/dark area
associated with the channels.

Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.

A THI transmit failure can cre- Transmit Test


ate lighter or dark lines in the
image

Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.

A single channel receive failure typically creates an artifact that is shaped like an arc
in normal or THI imaging
mode

Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Interchange TR
boards.

Antares

Test

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45

Board

Image Problem

Test

Troubleshooting Suggestion

RC

Large dropouts in image


associated with an defective
RXBF (16-channel grouping)

RC memory

Interchange TR boards. If the dropout/artifact stays in the same position, the


RC board is most likely the problem.

Receive test
B mode
BC mode

Large areas of color noise in


image associated with an
defective RXBF (16 channel
grouping)

If the dropout/artifact changes position,


the TR board is most likely the problem.

RC memory
Receive test
B mode
BC mode

Vertical lines in image

RC memory
Receive test
B mode
BC mode

Color/Power outside vessels


or on bright areas of B image,
can be intermittent due significant tendency on temperature

Check top marking on U78 and U79 (near


connector P508- See (Fig. 23 / p. 47)), if
marked with KLT23 then this failure mode
is possible and RC board should be
replaced, if marked with XEL23 then this
failure mode is not possible. Note: Not all
KLT23 parts are defective, so only
replace RC boards that have these parts
and a history of the problem.

Poor image resolution due to


defective main clock oscillator
Bands in image
Color noise on skinline

A2D Diag

RCFEREF voltage bad

Grid artifact in far field

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Troubleshooting Guide

Board

Image Problem

Test

BE

Entire image has problems

B mode

Troubleshooting Suggestion

BC mode
Image problems that seem to BE memory
be digital - hard horizontal or B mode
vertical boundaries; blocks of
BC mode
colors; etc.
Radial line color noise

B mode
BC mode

Doppler problems

BE memory

M-mode problems

BE memory

Cine problems

BE memory

BE/VI

Audio problem

VI

no image

UFP can also cause no audio

Color noise
Incorrect color (I.e, red
image)
Vertical lines in image
Doppler Auto stats overlay
problem
RM

Image overlay problems


System locks up
Image break up- Large sections of image shifted or out
of place
3D problems
4D problems

Run the TI test and all 4D transducer


tests to ensure the TI board and all the
transducers are OK.

VI/BE/R Error Message


C/TR

Antares

Refer to log files in C:/Syngo/log directory. Files such as ImagingBE.log and


ImagingCrashDataWdyMthDDHHMMSS
Year0.txt

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Fig. 23: Drawing of RC Board Area


Pos. 1

U78

Pos. 2

U79

Tab. 17

Image Problems and associated board fault

Image Problem

Board

Troubleshooting Suggestion

Problems in 8-channel
segments

TR

Refer to Antares (Channel


Map / p. 51)and then interchange TR
boards. A TR-related imaging fault will
move with the associated TR as indicated by the channel map.

3D problems

RM

4D problems

RM

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Medical Solutions USA, Inc.

Test

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This assumes the transducer and TI


module are functioning properly

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48
Image Problem

Troubleshooting Guide
Board

Troubleshooting Suggestion

Problems in 64-channel
segments

TR

Refer to Antares (Channel


Map / p. 51)and then interchange TR
boards. A TR-related imaging fault will
move with the associated TR as indicated by the channel map.

Arc-shaped artifact in
normal or THI imaging
mode

TR

Refer to Antares (Channel


Map / p. 51)and then interchange TR
boards. A TR-related imaging fault will
move with the associated TR as indicated by the channel map.

Audio problem

BE, VI

UFP can also cause no audio

Bands in image

RC

Cine problems

Test

BE memory

Color noise
Color noise on skinline

VI
A2D Diag

Color/Power outside
vessels or on bright
areas of B image, can
be intermittent due significant tendency on
temperature

Dead/dark area associated with the channels

Transmit test

Doppler Auto stats overlay problem


Doppler problems

Antares

BE

RC

RCFEREF voltage bad

RC

Check top marking on U78 and U79


(near connector P508), if marked with
KLT23 then this failure mode is possible
and RC board should be replaced, if
marked with XEL23 then this failure
mode is not possible. Note: Not all
KLT23 parts are defective, so only
replace RC board that have these parts
and a history of the problem.

TR

Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Refer to
Antares (Channel Map / p. 51)and then
interchange TR boards. A TR-related
imaging fault will move with the associated TR as indicated by the channel
map.

VI
BE memory

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BE

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49

Image Problem

Test

Board

Entire image has problems

B mode, BC mode
tests

BE

Error message

TR, RC,
BE, VI

Grid artifact in far field

RC

Image break up

RM

Image overlay problems

RM

Incorrect color

VI

Large areas of color


noise in image (16
channel grouping)

RC memory,
receive test, B
mode, BC mode

RC

Large dropouts in image RC memory,


(16 channel grouping)
receive test, B
mode, BC mode

RC

Light or dark lines in the


image

TR

M-mode problems

BE memory

Troubleshooting Suggestion

Refer to log files in C:/Syngo/log directory. Files such as ImagingBE.log and


ImagingCrashDataWdyMthDDHHMMSS
Year0.txt.

Moving the focal point closer to the skinline will make transmit failures easier to
identify. This reduces the number of
transmit channels fired at the same time.
Using Cine playback can make a bad
channel easier to identify. Refer to
Antares (Channel Map / p. 51)and then
interchange TR boards. A TR-related
imaging fault will move with the associated TR as indicated by the channel
map.

BE

No image

VI

Poor image resolution

RC

Problems with digital


imaging

BE memory, b
mode, BC mode
tests

BE

Radial line color noise

B mode, BC mode
tests

BE

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Troubleshooting Guide

Image Problem

Test

Board

Troubleshooting Suggestion

Single channel problems

TR

Refer to Antares (Channel


Map / p. 51)and then interchange TR
boards. A TR-related imaging fault will
move with the associated TR as indicated by the channel map.

System locks up

RM

Vertical lines in image

RC memory,
receive test, B
mode, BC mode

RC, VI

Firmware failures
Firmware failures are logged in the fwlog.txt file located in the C:/syngo/log directory.
Always start at the end of the file to review the most current firmware information.
For firmware failures, the board where the failing device is located is the probable cause.
The board controlling the programming operation is the next probable - but less likely cause.
A firmware load/upgrade normally takes place if a new board, module or 4D transducer is
recognized. Firmware may also be upgraded as part of a software patch or combine code
load. For details on how to access a FW log, see (Appendix C: Examples of ImagingBE
and Firmware Logs / p. 56) and (Appendix D: How to Boot in Safe Mode / p. 59).
Tab. 18

Firmware Failures

Board

Device

Board which controls


programming

BE

SIP DSP

RM and BE

SIP

BE

FPA

BE

FPB

BE

PCI

BE

DEC

BE

VI

ENC
ACLK
VCLK

Antares

RC

RTC

BE

TR

TR

BE

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Board

Device

Board which controls


programming

TI

TI

BE

RM

Program BIOS

RM

Channel Map

The following figures show the Antares Channel map, from left to right. The map is broken
down into segments for ease of use.
Image channels from left to right refers to the channels displayed on the system monitor, from left to right. Channel 0 is the left-most channel while channel 191 is the
right-most for a 192-element transducer. Channel 32 is the left-most and channel 159 is
the right-most channel for a 128-element transducer.
Diagnostic channel references refers to the numbering system used in diagnostic test
results.
Transmit receive PWA (TR) identifies which TR board - TR0, TR1 or TR2 - corresponds
to a particular channel or set of channels.
TXPG ASIC identifies which TXPG ASIC corresponds to a particular channel or set of
channels.
Receive Beanformer (RXBF) ASIC identifies which RXBF ASIC corresponds to a particular channel or set of channels.

Fig. 24: Channels 0-31

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Fig. 25: Channels 31-63

Fig. 26: Channels 64-127

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Fig. 27: Channels 128-159

Fig. 28: Channels 160-191

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Appendix A: Test Results and Test Summary

An example of a test results and a test summary can be found in: (US03-101.840.71 /
System Logs.exe).

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Appendix B: How to Access ImagingBE and Firmware Logs

If the Local Service Page is available:


1. Select Presets
2. Select Service in the left plane
3. Select Local Service
4. Type in the service key - Level 7 or higher is required
5. Select Utilities
6. Select Escape to OS from the dropdown menu.
7. Type EXPLORER in the parameter field and select Go in the lower right corner.
8. Select the C Drive under My Computer.
9. Select the Syngo Directory
10. Select Log.
11. Identify the ImagingBE.log, ImagingBE.1.log, ImagingBE.2.log and the fwlog.txt
files.
12. Double click the file to open. The log should open in Notepad.
If the Local Service Page is NOT available:
1. Boot the system in safe mode. See (Appendix D: How to Boot in Safe Mode / p. 59)
The system is booted up in safe mode with a prompt.
2. Type EXPLORER at the command line and select Enter.
3. From Explorer, select the C Drive under My Computer.
4. Select Syngo.
5. Select Log.
6. Identify the ImagingBE.log, ImagingBE.1.log, ImagingBE.2.log and the fwlog.txt
files.
7. Double click the file to open. The log should open in Notepad.

What to look for in a ImagingBElog

The ImagingBE log will display test results. Any problems or faults will be noted in the log
and will be preceded by the word ERROR!

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Appendix C: Examples of ImagingBE and Firmware Logs

Imaging Log

At each reboot, a new BE log is generated. ImagingBE.log is the log from last reboot. The
system saves up to 3 BE logs at a time. Scroll through the log and look for error indications.
An example of a BE log can be found in: (US03-101.840.71 / System Logs.exe).

Firmware (FW) Log

The FW log gets updated every time a firmware load is executed. Typically, a firmware
load takes place if a new module or board is installed. The system checks the firmware
revision and loads new firmware if necessary.
A firmware load can take place if a 4D transducer is connected or a software patch or
combine code is installed.
If firmware is loaded or if an attempt is made to load firmware, information will be
appended to the fw log. The most recent information will be at the end of the log.
What to look for in a FW log
Firmware tests check to see if the correct firmware has been/is installed on the system. If
the test discovers that the fw is not current, it will search for the proper fw revision and
attempt to load the correct version. It will then attempt to verify that the correct firmware
was properly loaded. The firmware log will alert the CSE to the status of the firmware.
Firmware Log Example
The following information is an example of a firmware log pulled from an Antares system.
The log itself can also be found in: (US03-101.840.71 / System Logs.exe).
Firmware log
Mon Oct 04 15:33:57 2004
Zm System : Software Installed
Mon Oct 04 15:57:18 2004
Back End : Configuration mismatch Back End PCI FW rev expected 29.29, actual 29.22
Mon Oct 04 15:57:19 2004
Video Interface : Configuration mismatch Video Interface VCLK FW rev expected 5.0,
actual 4.0
Mon Oct 04 15:57:19 2004
Back End : Loading c:\zdt\program_PCI_29.29_0.sbs to Back End
Mon Oct 04 15:58:33 2004

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Back End : Loading c:\zdt\program_PCI_29.29_1.sbs to Back End


Mon Oct 04 15:59:46 2004
Back End : Verify c:\zdt\verify_PCI_29.29_0.sbs on Back End
Mon Oct 04 15:59:49 2004
Back End : Verify c:\zdt\verify_PCI_29.29_1.sbs on Back End
Mon Oct 04 15:59:53 2004
Video Interface : Loading c:\zdt\program_VCLK_5.0_0.sbs to Video Interface
Wed Oct 06 10:30:54 2004
Receive Control : Configuration mismatch Receive Control RTC FW rev expected 07.15,
actual 07.02
Wed Oct 06 10:30:54 2004
Back End : Configuration mismatch Back End DSP FW rev expected 1.75, actual 1.70
Wed Oct 06 10:30:54 2004
Back End : Configuration mismatch Back End FPA FW rev expected 4.5, actual 3.5
Wed Oct 06 10:30:54 2004
Back End : Configuration mismatch Back End PCI FW rev expected 29.29, actual 29.14
Wed Oct 06 10:30:54 2004
Transducer Interface : Configuration mismatch Transducer Interface TI FW rev expected
5.53, actual 5.29
Wed Oct 06 10:30:54 2004
Realtime Manager : Configuration mismatch Realtime Manager BIOS FW rev expected
1.0.7, actual 1.0.6
Wed Oct 06 10:30:55 2004
Receive Control : Loading c:\zdt\program_RTC_07.15_0.sbs to Receive Control
Wed Oct 06 10:32:08 2004
Receive Control : Loading c:\zdt\program_RTC_07.15_1.sbs to Receive Control
Wed Oct 06 10:33:21 2004
Back End : Loading c:\zdt\program_dsp_1.75 to Back End
Wed Oct 06 10:34:42 2004
Back End : Verify c:\zdt\program_dsp_1.75 on Back End
Wed Oct 06 10:34:42 2004
Back End : Loading c:\zdt\program_FPA_4.5_0.sbs to Back End
Wed Oct 06 10:35:55 2004
Back End : Loading c:\zdt\program_FPA_4.5_1.sbs to Back End
Wed Oct 06 10:37:08 2004
Back End : Verify c:\zdt\verify_FPA_4.5_0.sbs on Back End

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Wed Oct 06 10:37:12 2004
Back End : Verify c:\zdt\verify_FPA_4.5_1.sbs on Back End
Wed Oct 06 10:37:15 2004
Back End : Loading c:\zdt\program_PCI_29.29_0.sbs to Back End
Wed Oct 06 10:38:28 2004
Back End : Loading c:\zdt\program_PCI_29.29_1.sbs to Back End
Wed Oct 06 10:39:41 2004
Back End : Verify c:\zdt\verify_PCI_29.29_0.sbs on Back End
Wed Oct 06 10:39:44 2004
Back End : Verify c:\zdt\verify_PCI_29.29_1.sbs on Back End
Wed Oct 06 10:39:48 2004
Transducer Interface : Loading c:\zdt\program_TI_5.53_0.sbs to Transducer Interface
Wed Oct 06 10:41:01 2004
Transducer Interface : Verify c:\zdt\verify_TI_5.53_0.sbs on Transducer Interface
Wed Oct 06 10:41:04 2004
Realtime Manager : Loading c:\zdt\program_BIOS_1.0.7.bin to Realtime Manager
Wed Oct 06 10:41:27 2004
Realtime Manager : Verify c:\zdt\program_BIOS_1.0.7.bin on Realtime Manager

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Appendix D: How to Boot in Safe Mode

To be able to access important information at times, it may be necessary to boot in safe


mode. Before the system will boot into safe mode, certain settings need to be temporarily
altered - USB legacy must be enabled and the system splash screen must be disabled.

NOTE

Disconnect the QuickStart battery, if installed.

To enable USB Legacy:


1. Ensure the system is completely powered down and not in standby mode.
2. Turn on power using the green power switch, located near the CD-R.
3. Press and hold the Ctl and Browser keys on the keyboard.
NOTE

If this does not work, power down system and retry. Instead of
holding down the Ctl and Browser keys, hold down the Ctl key and
then quickly and continuously tap the Browser key.

4. The system will boot to the BIOS setup menu.


5. Use the left-right arrow keys to navigate to the Advanced header.
6. Use the Up-Down arrow keys to navigate to Legacy Support.
7. Press Enter on the keyboard.
8. Select Enable from the drop down menu.
To be able to boot into safe mode, the splash screen must first be disabled. The following
steps are only necessary if the system has software rev 3.0 installed.

NOTE

In the Windows BIOS, the screen is called a clean screen and is


the same thing as the splash screen. The term splash screen will
be used exclusively except when referencing text taken directly
from the Windows BIOS.

How to disable the splash screen:


1. From the main BIOS, select Keyboard Features.
2. Press Enter on the keyboard.
3. Navigate to the Clean Screen entry.
4. Select Disable from the drop down menu.
How to Boot in safe mode
1. Once the splash screen and the Legacy USB settings are changed, press the Text D
key on the keyboard. The system will start to reboot.
2. Press and hold the Text B key on the keyboard.

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3. Continue holding the key until the system starts beeping, then release the key.
4. A screen will come up asking how the system should be booted. Select Safe Mode
with a Command Prompt.
5. Press Enter on the keyboard
6. The system will ask which OS should be loaded. Choose MS Windows Professional and press Enter on the keyboard.
7. The system will boot to Safe Mode with a Command Prompt.

NOTE

Antares

After leaving Safe Mode and rebooting the system, the Antares will
not restore the BIOS defaults. Please re-enter the BIOS and change
the Clean Screen setting to Enable and the USB Legacy setting to
Disable.

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Appendix E: Test Descriptions

The main goals for the Antares system diagnostics are:


1. Accurate diagnosis of defective Field Replaceable Units (FRUs).
2. Local execution with no external test equipment.
3. Remote execution via Siemens SRS.
The test functions are individually executable address the following FRUs:
Field Replaceable Units

Back-end Board
Transmit Receive Board
Receive Control

Continuous Wave Beamformer (for future use)


Transducer Interface
Control panel
RealTime Manager
Video Input/Output
Input / Output Board
Physio Module
E Module

The individually executable test functions and the FRUs they address are described in the
following outline.
Unless otherwise specified these tests require no external test equipment.

Front-end Segment

Real Time Controller Memory Test


Standard memory test performed on all testable registers and memory spaces.
Test Coverage - Real Time Controller Memory Test
Coverage for this test includes the FEBus interface from the BE board, the RTC FEBus
interface the RTC internal and the external RTC SRAM

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Fig. 29: Test Coverage, Real Time Controller Memory Test

Receive Control Sequencer Test


Functional test of the ability of the RC to program the TR cards and its own RXBF ASICs
at high speed. The target registers and tables are first cleared. Patterns are stored in the
RC index state machines tables. A sequence is loaded that is expected to move the patterns out to the TXPG and RXBF ASICs. The sequence is executed and the results verified.
Test Coverage - Receive Control Sequencer Test
Coverage for this test include the local uP bus from the RTC to the RXBF asics, the
TCBus to the TR and TI boards. The local interfaces on the TR board, the Control EPLD
and the TXPGs, the local interface and the Control EPLD on the TI board.

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Fig. 30: Test Coverage - Receive Control Sequencer Test

Receive Beamformer ASIC Memory Test


Standard memory test performed on all testable registers and memory spaces.
Test Coverage - Receive Beamformer ASIC Memory Test
This test covers the RXBF internal registers and SRAM plus the FEBus interface to the
RTC and the local uP bus.

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Fig. 31: Test Coverage, Receive Beanformer ASIC Memory Test

Receive Beamformer ASIC Built-in Self-test


A file list of register values is loaded into each asic. The device is programed to initiate a
BIST function and the return signatures are compared with expected values. A self contained RAM BIST is also executed and the results are displayed.
Test Coverage - Receive Beamformer ASIC Built-in Self-test
This test covers the RXBF internal registers and SRAM plus the FEBus interface to the
RTC and the local uP bus

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Fig. 32: Test Coverage - Receive Beamformer ASIC Built-in Self-test

Transmit Pulse Generator ASIC Memory Test


Standard memory test performed on all testable registers and memory spaces.
Test Coverage - Transmit Pulse Generator ASIC Memory Test
This test covers the TXPG internal registers and SRAM plus the TCBus interface to the
TR and the local uP bus.

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Fig. 33: Test Coverage, Transmit Pulse Generator ASIC Memory Test

Transmit Pulse Generator ASIC Built-in Self-test


The TXPG Built-in Self Test is composed of three sub-tests described in the following sections.
Txpg pass counter test
This test will exercise the TXPG by generating 255-4.5 mhz waveforms per channel from a
minimum length 8 nibble data pattern loaded into the Hout and Lout lower memories. The
memory will be loaded with a minimum ram length nibble pattern so that the number of
ram Pass Counters of each channel will be exercised extensively. All channels will be set
to 0 delay to speed up testing.
Txpg nibble counter test
The test will exercise the TXPG by generating 33-2.48 mhz waveforms from a maximum
ram length data pattern of 696 nibbles loaded into lower memory for even channel checks
and upper memory for odd channel checks.
Txpg delay counter test

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This test will exercise the TXPG by generating only one 4.5 mhz pulse sequence per
channel after a maximum length channel delay.
Test Coverage - Transmit Pulse Generator ASIC Built-in Self-test
This test covers the TXPG internal logic and SRAM plus the TCBus interface to the TR
and the local uP bus.

Fig. 34: Test Coverage, Transmit Pulse Generator ASIC Built-in Self-test

Receive Test
A signal source on the RC is routed through the TI to all receive channels and sampled by
each RXBF ADC. Signal analysis on samples in each RXBF SRAM are used to verify
each receive channel.
Test Coverage - Receive Test
Coverage includes the RC boards FEBus interface, RTC, RXBFs, gain controls and
TCBus interface; the TR boards TCBus interface, receive amplifiers and signal paths and
gain controls; TI boards BIT test signal routing and internal power divider.

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Fig. 35: Test Coverage - Receive Test

Transmit Tests
The test will be done by transmitting on each channel in turn or multiple channels delayed
with increasing delay per channel and examining the signal received in the RXBF SRAM
of channel 16. This TRRCS channel can be connected to the TIRCMSR inputs which permit an independent signal path. The resistive power combiner on the TI board can be
directed to this measurement path. Signal analysis on these samples will verify that each
of the transmitters fire.
The transmit test must be executed twice, once for each of the 2 transmit voltage supplies.
Test Coverage - Transmit Tests
Coverage includes the RC boards FEBus interface, RTC, RXBF channel 16, and TCBus
interface; the TR boards TCBus interface, transmit pulsers and signal paths and transmit
voltage controls; TI boards BIT test signal routing and internal power combiner or the
external PCD.

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Fig. 36: Test Coverage - Transmit Tests

Continuous Wave Transmit Test (SCW TX Pwr Calibration)


This test is in reality a test of the TR boards. It has been accomplished by designing and
implementing a SCW Transmit power calibration test. The test sets up the transmitters to
transmit in Infinite Pulse Mode, at 1.818 MHz. Using an External Power divider combiner
as a load the waveform of the CW signal produced by transmitting on 64 channels is captured in RXBF channel 16 via the TIRCMSR circuit. Analysis of the data provides a value
for the absolute power per channel. The test then increments the Transmit power control
code and repeats the data gathering and analysis process. The output of the test is a set
of calibration values that are used by OPSW to cause each system to behave the same in
regard to SCW transmit power requests.
The Data that is stored in the RC board ID prom is made available to OPSW via a text file.
The text file is generated by the test and any time Zdt starts up.
Test Coverage - Continuous Wave Transmit Test
Not applicable to the CB.

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Continuous Wave IQ Phase and Gain Calibration Test
This test injects a signal from an external source into the CB boards Pencil Probe CW
input. The external source delivers a signal whos frequency is the current operating frequency plus two kilo Hertz. The CB board is properly set up for this mode of operation.
The signal is processed as a PPCW signal and IQ data is gathered at the SIP. The Baseband IQ data is analyzed for Phase difference and amplitude ratio. The phase difference
from exactly 90 deg of the Q data and the amplitude ratio of I/Q are saved and stored in
the CB boards IDProm. A calibration value for each operating frequency, each high pass
filter setting and each baseband gain setting is stored. The total number of values is 162
(9X2X9).
The Data that is stored in the CB board ID prom is made available to OPSW via a text file.
The text file is generated by the test and any time Zdt starts up and detects that the CB
Serial number has changed from the last time the file was generated. (The CB board
Serial number is imbedded in the file).
Test Coverage - Continuous Wave IQ Phase and Gain Calibration Test
The test covers the Pencil probe CW input amplifier, Frequency specific band pass filter
section, RF mixer section, base band gain section, the selectable high pass filter section,
the low pass anti-aliasing section and the Analog to Digital converter section.
Pencil Probe CW Receive Test
The Pencil probe CW receive test sets up the CB board from the test selectable operating
frequency, base band gain and high pass filter settings. The pseudo random signal generator resident on the RC board is used to inject a test signal into the Pencil Probe CW input
via the TI board diagnostic test circuit. IQ data is gathered at the SIP and Analyzed for signal level at a particular frequency. The raw time domain data is processed by a
Cooley-Tukey radix-2, DIF fft function. It provides a frequency resolution of 9.5367 Hz.
The pseudo random generated will provide frequency content that will span more than
one bin but will be consistent from machine to machine.
Steerable CW Receive Test
The Steerable CW receive test sets up the CB board from the test selectable operating
frequency, base band gain and high pass filter settings. The pseudo random signal generator resident on the RC board is used to inject a test signal into all of the TR RF signal
paths via the TI board diagnostic test circuit and power divider. IQ data is gathered at the
SIP and Analyzed for signal level at a particular frequency. The raw time domain data is
processed by a Cooley-Tukey radix-2, DIF fft function. It provides a frequency resolution of
9.5367 Hz. The pseudo random generated will provide frequency content that will span
more than one bin but will be consistent from machine to machine.
Pencil Probe CW Transmit Test
The Pencil Probe CW transmit test sets up the CB board from the test selectable operating frequency and transmits its CW signal to the TI board which as been configured to
direct the PPCW transmit to the TIRCMSR circuit. The data is gathered via TRRCS channel 16. The data is analyzed for power and compared to and expected absolute value.

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Power supply and Reference Test


A 14 bit ADC on the RC board will be accessed to convert power supply and reference
signal voltages. These are all DC measurements and will have PASS/FAIL limits applied
to each signal individually. A measurement bus has be defined to allow each board
accessed to drive the input to the single A/D with the power supplies and references for
that board.
In addition to the Power supply and reference test there is a sub-set test that accesses
only the available power supplies. Most are available on the RC, the TI and CB are
accessed for the others. There are 5 Digital supplies (PSD) and 12 Analog supplies
(PSA). The diagnostic A/D can access 8 of the Analog supplies, 10 if there is a CB board
and ONE Digital supply. The 4 digital supplies will more than likely preclude the BE board
from working at all if they are non-functional.
Test Coverage - Power supply and Reference Test
Coverage includes the RC boards Diagnostic ADC, input muxes, local uP bus and the
RTC and its FEBus interface; the TR boards diagnostic analog mux; the TI boards diagnostic analog mux.

Fig. 37: Test Coverage - Power supply and Reference Test

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Control Dac Test

The Control Dac test exercises the TGC, AAC, TXV0, TXV1, PSMON0 and PSMON1 control dacs. Each dac output, or a derivative of it is available at the mux of each TR board.
For general tests related to the RC board the mux on the first TR board is used. For TR
board specific tests the mux on the Board under test is used.
The mux output drives the Diagnostic A2D converter on the RC board. Each dac is incremented over its entire range. The acquired values from the ADC are processed for Slope,
Offset and RMS deviation. Limits are applied to each of these values.
The PSMON0 and 1 dacs are not directly tested. These dacs are tested by setting the
PSMON dac then incrementing the TXV dac until the corresponding interrupt occurs. The
TXV value is acquired and when all PSMON values have been exercised then the same
Slope, Offset and RMS calculations and limits are applied. The Slope and Offset values
from the TXV test, which is always executed first, are used to minimize errors in this calculation.
Test Coverage - Control Dac Test
These tests exercise the RC board Dacs and ADC the TXV power supplies and Various
analog buffers on the RC and TR boards.

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Fig. 38: Test Coverage - Control Dac Test

Transducer Interface Memory Test


Standard memory test performed on all testable registers and memory spaces.
Test Coverage - Transducer Interface Memory Test
Coverage includes the TI board register and memory.

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Fig. 39: Test Coverage, Transducer Interface Memory Test

Transducer Interface Probe Relay Test


The Capacitive combiners on the TI board which can be directed to the TIRCMSR bus will
be used to verify that a transmitter can transmit across each relay tree for each of the
three positions of the probe connect relays. A version of the transmit test will be used to
do this verification test. The purpose of the test is to find broken relays so minimal signal
analysis will be done.
Test Coverage
Coverage includes the same hardware as plus the TI boards capacitive combiners.

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Fig. 40: Test Coverage, Transducer Interface Probe Relay Test

Back-end Segment

PCI FPGA Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
on the BE PCI FPGA.
Test Coverage - PCI FPGA Memory Test
The internal memory spaces in the BE PCI FPGA.

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Fig. 41: PCI FPGA Memory Test Coverage

Digital Receiver ASIC Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
of each of the DR ASICS. Note that there are 4 separate tests, one for each ASIC.
Test Coverage -Digital Receiver ASIC Memory Test
The internal memory spaces in the DR ASICs and the BE local bus.
Digital Receiver ASIC Built-in Self-test - BE
Standard ASIC signature test. The resulting digital signature is compared to simulation
results. Note that there are 4 separate tests, one for each ASIC.
Test Coverage -Digital Receiver ASIC Built-in Self-test
The internal memory spaces in the DR ASICs and the BE local bus.

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Fig. 42: DR Memory & BIST Test Coverage

Echo Processor ASIC Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
in the EP ASIC.
Test Coverage -Echo Processor ASIC Memory Test
The internal memory spaces in the EP ASIC and the BE local bus.
Echo Processor External Memory Test - BE
Standard barberpole memory test performed on the EP external Persistence SRAM.
Test Coverage -Echo Processor ASIC External Memory Test
The EP ASIC interface for external SRAM, the SRAM memory devices and the BE local
bus.
Echo Processor ASIC Built-in Self-test - BE
The BIST setup for the EP is imported directly from the ASIC design simulation. A CRC
signature is generated and compared to simulation results.
Test Coverage -Echo Processor ASIC Built-in Self-test
This test covers the EP internal registers and SRAM plus the local uP bus.

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Fig. 43: EP Memory & BIST Test Coverage

Flow Processor ASIC Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
on the FP ASIC. Note that this test is skipped for all BE boards with P/N 7466746 or later.
These have an updated FP ASIC that does not support reading from the ASIC.
Test Coverage -Flow Processor ASIC Memory Test
The internal memory spaces in the FP ASIC and the BE local bus.

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Fig. 44: Test Coverage -Flow Processor ASIC Memory Test

Flow Processor CTB Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
on the FP ASIC.
Test Coverage -Flow Processor ASIC Memory Test
The external Corner Turning Buffer (CTB) memory space and the BE local bus.

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Fig. 45: Flow Processor Memory Test Coverage

Flow Processor FPGA Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
in the EP ASIC.
Test Coverage -Flow Processor FPGA Memory Test
The internal memory spaces in the FP FPGA and the BE local bus.
Flow Processor FPGA External Memory Test - BE
Standard barberpole memory test performed on the FP external Persistence SRAM.
Test Coverage -Flow Processor FPGA External Memory Test
The FP FPGA interface for external SRAM, the SRAM memory devices and the BE local
bus.

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Fig. 46: FP FPGA Memory Test Coverage

Scan Converter ASIC Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
in the SC ASIC.
Test Coverage -Scan Converter ASIC Memory Test
The internal memory spaces in the SC ASIC and the BE local bus.
Scan Converter External Memory Test - BE
Standard barberpole memory test performed on the SC Cine and Raster buffer SDRAM.
Test Coverage -Scan Converter ASIC External Memory Test
The SC ASIC interface for external SDRAM, the SDRAM memory devices and the BE
local bus.

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Fig. 47: SC Memory & Bist Test Coverage

SIP FPGA Memory Test - BE


Standard barberpole memory test performed on all testable registers and memory spaces
from the host CPU.
Test Coverage -SIP FPGA Memory Test
All internal RAM accessible by the CPU via PCI.
Digital Signal Processor IPC Test - BE
Diagnostic DSP firmware is loaded into the DSP program RAM via the Host Port Interface
(HPI) and a set of Inter-Processor Command (IPs) packets are sent from the host CPU to
the DSP. The DSP performs a checksum of each packet and sends it back to the host.
Test Coverage -Digital Signal Processor Memory Test - BE
Test Coverage -Digital Signal Processor IPC Test
Control and interrupt interface between the SIP FPGA and the DSP.
Test Coverage -Digital Signal Processor Memory Test - BE
Diagnostic DSP firmware is loaded into the DSP program RAM via the Host Port Interface
(HPI) and a memory test performed on all DSP external memory spaces.

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Fig. 48: DSP Test Coverage

Video Interface Segment

Decoder FPGA Memory Test - VI


Standard memory test performed on all testable registers and memory spaces in the VI
Decoder FPGA.
Test Coverage -Decoder FPGA Memory Test
A series of audio tones are generated by the BE DSP and are heard on the system speakers. The operator is prompted to indicate pass or fail.
Encoder FPGA Memory Test - VI
Standard memory test performed on all testable registers and memory spaces in the VI
Encoder FPGA.
Test Coverage -Encoder FPGA Memory Test
The internal memory spaces in the Encoder FPGA and the VI local bus.

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VPDM ASIC Memory Test - VI
Standard memory test performed on all testable registers and memory spaces in the VI
VPDM ASIC except for the external SDRAMs.
Test Coverage -VPDM ASIC Memory Test
The internal and external memory spaces in the VPDM ASIC and the VI local bus.
VPDM SDRAM Test - VI
Four memory tests are available for the external SDRAM associated with the VPDM. Two,
the Address Data Test and the Bank Address Test, are enabled by default but may be
optionally disabled for troubleshooting support. Two other tests, the Checkerboard Test 0
and Checkerboard Test 1, may be enabled for troubleshooting support.
Test Coverage -VPDM ASIC Memory Test
The Address Data Test accesses all memory locations the external SDRAM. The test
checks the operation of all address and data lines, and identifies row and column addressing errors. The test cannot identify bank addressing errors.
The Bank Address Test identifies bank addressing errors.
The two checkerboard tests may be used to write alternating ones and zeros to every bit
in SDRAM.
Each test returns up to 30 error messages identifying the SDRAM LUT index, the device,
bank, row, and column of the failing location, and the expected and actual data read from
the location.

Control Panel Tests - CP

Executes the CP power-on self test on the CP sub-processor and reads the result back.
The POST tests executed are:

CPU Check
RAM Check
Boot Block CkSum
App Code CkSum
Stuck Key

Control Panel Manual Test


A graphical layout of the control panel is presented on the system monitor showing all the
keys, knobs, sliders and toggle switches.
The controls on the display highlight when that control is used. The operator presses each
key, turns and presses each knob, slides the sliders and toggles the toggles.

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Physio POST Test


Execute the built-in power-on self test on the external Physio Signal module and reports
the result. Possible errors include:

Physio POST: ROM Error


Physio POST: SRAM Error
Physio POST: I/O Error
Physio POST: Software Error

System Level Tests - RC, BE, VI

The approach for each of the mode functional tests is to load a static test pattern into the
RXBF delay SRAMs and to program the entire system (excepting transmit channels) to
beamform and image this data in each of the specified modalities.
After a fixed number of frames the sequencer is stopped. Register data and CRC values
for memory data are examined to verify system operation in the specified imaging mode.
For each mode of operation a meaningful visual pattern is displayed on the system.
Register data and CRC values isolate the section of the EM that is responsible for a test
failure.
Tests are defined for the imaging modes listed below.
B-Mode
The test emulates B-Mode imaging operation for a C5-2 transducer set for maximum
depth and 4 parallel beams.
The test stimulus is a 2.2 Mhz sine wave pattern loaded into all RXBF Delay SRAMs.
Imaging is enabled for a fixed number of frames then halted. Register values are tested for
the RC board, for the VPSC ASIC on the BE board, and for the VPDM ASIC on the VI
board. When register values indicate successful operation, CRC values are calculated
from the following: Synthetic Aperture memories associated with all 4 DR ASICs on the
BE board, RP Raster memory associated with the VPSC ASIC on the BE board, and raster memory associated with the VPDM ASIC on the VI board. If register values indicate
that data were not processed as expected at any point, subsequent CRC values are not
calculated.
B-Mode System Test Coverage
The entire digital B-Mode data path is tested, from the RXBF ASICs on the RC board
through to the raster video area of SDRAM and the VPDM ASIC on the VI board.

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Fig. 49: B-Mode System test Coverage

BC-Mode
The test emulates BC-Mode imaging operation for a C5-2 transducer with a color ROI set
for minimum width and maximum height.
The test stimulus is a 2.2 Mhz sine wave pattern loaded into all RXBF Delay SRAMs.
Imaging is enabled for a fixed number of frames then halted. Register values are tested for
the RC board, for the VPSC ASIC on the BE board, and for the VPDM ASIC on the VI
board. When register values indicate successful operation, CRC values are calculated
from the following: Synthetic Aperture memories associated with two DR ASICs on the BE
board, RP Raster memory associated with the VPSC ASIC on the BE board, and raster
memory associated with the VPDM ASIC on the VI board. If register values indicate that
data were not processed as expected at any point, subsequent CRC values are not calculated.
BC-Mode System Test Coverage
The entire digital BC-Mode data path is tested from the RXBF ASICs on the RC board
through to the raster video area of SDRAM and the VPDM ASIC on the VI board. Both the
echo path through the DR and EP ASICs and the flow path through the FP ASIC and FP
FPGA are evaluated.

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Fig. 50: BC Mode System Test Coverage

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Appendix F: Board Tests and Related Failures

Diagnostic Test Tools

In this Stage, the higher level FRU diagnostic test suites can be run.
To access the diagnostic tests, a site-specific service access key Level 7 is needed. Service access keys for the Antares are based on the system serial number. The CSE or user
who requires a Service key obtains it through Service.
1. Select Presets from the imaging toolbar or from the keyboard.
2. Select Service

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3. Select Local Service.

Fig. 52:

4. The Service Authentication page appears. Enter the service access key and click OK.
The Service access key is a 20-digit alphanumeric password. The first 14 digits are
placed in the first field and the last six are placed in the second field. Clicking the Set as
Default box will save only the first 14 digits upon reboot. The final six must me entered
manually after each entrance to the local service page. if the Set as Default box is not
checked, the entire access key must be re-entered on reboot.

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5. The Service Home page appears. Click TestTools to go to the TestTools screen. A
message will appear saying: Please insure [sic] that all probes are disconnected and REMOVED from the three connectors of the system.
This is REQUIRED for tests to operate properly. Ensure that all transducers are disconnected from the transducer interface, then click OK.
6. The TestTools screen allows access to all of the higher level FRU tests, including the E
Module test, E Module board level tests, transducer interface test, Power Supply test,
Physio Module test, transducer tests and CD-ROM tests.

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7. Select Board Test, a sub-menu for E Module test. A new menu will appear which will
show all the available board tests.

Fig. 55: Board Tests

8. Select the appropriate test and click Start to run the tests. An Estimated Time counter
shows approximately how much time is needed to complete the diagnostic tests. The
counter will count down during the tests, which is indicated by the letters dn next to the
timer. When the estimated time has been exceeded, the counter will start counting up,
indicated by the letters up.

Fig. 56:

9. After the tests are completed, scroll to the bottom of the scroll box and check the status
of the tests. If the test fails, a detailed report of the failure can be found on the Reports
page.

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Test target areas
The next section will show a series of tables which explain the tests performed in each
section of the system, which board is targeted in each section of the test and the primary
focus of that test. The tests will be executed as part of the board tests.
Tab. 19

Front End Test target areas

Test Front End

TR Board
Test

RC Board
Test

E Module
Test

RC Memory

FE Memory

RC Cntrl Seq

RTC

Receive Beamformer ASIC Memory


Test

RC Memory

FE Memory

Receive Beamformer ASIC Built-in


Self-test

RC Memory

FE Memory

Real Time Controller Memory Test


Receive Control Sequencer Test

TR Cntrl Seq

RTC

Transmit Pulse Generator ASIC


Memory Test

TR memory

FE Memory

Transmit Pulse Generator ASIC


Built-in Self-test

TR memory

FE Memory

Receive Test

TR receive

Receiver

TI Module
Test

Receiver

Receive Color Test


Transmit Tests

TR transmit

TR Transmit

Continuous Wave Transmit Test


(SCW TX Pwr Calibration)
Continuous Wave IQ Phase and
Gain Calibration Test
Pencil Probe CW Receive Test
Steerable CW Receive Test
Pencil Probe CW Transmit Test
Power supply and Reference Test

TR Diags

RC Diags

Refs

Refs

Transducer Interface Memory Test

TI Memory

Transducer Interface Probe Relay


Test

Probe Relay

Thermistor Measurement Test

Thermistor

Overcurrent Test

Overcurrent

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Tab. 20

93

Backend Test Target Areas

Test Backend

BE

EM

PCI FPGA Memory Test - BE

BE Memory

BE Memory

Digital Receiver ASIC Built-in Self-test - BE

BE Memory

BE Memory

Echo Processor ASIC Memory Test - BE

BE Memory

BE Memory

Echo Processor External Memory Test - BE

BE Memory

BE Memory

Echo Processor ASIC Built-in Self-test - BE

BE Memory

BE Memory

Flow Processor ASIC Memory Test - BE

BE Memory

BE Memory

Flow Processor CTB Memory Test - BE

BE Memory

BE Memory

Flow Processor FPGA Memory Test - BE

BE Memory

BE Memory

Flow Processor FPGA External Memory Test - BE

BE Memory

BE Memory

Scan Converter ASIC Memory Test - BE

BE Memory

BE Memory

Scan Converter External Memory Test - BE

BE Memory

BE Memory

SIP FPGA Memory Test - BE

BE Memory

BE Memory

Digital Signal Processor IPC Test - BE

BE Memory

BE Memory

Digital Signal Processor Memory Test - BE

BE Memory

BE Memory

Digital Signal Processor Program Verify- BE

BE Memory

BE Memory

Digital Receiver ASIC Memory Test - BE

Tab. 21

Test Video Interface target areas

Test Video Interface Segment

VI

EM

Decoder FPGA Memory Test - VI

VI Memory

VI Memory

Encoder FPGA Memory Test - VI

VI Memory

VI Memory

VPDM ASIC Memory Test - VI

VI Memory

VI Memory

VPDM SDRAM Test - VI

VI Memory

VI Memory

Tab. 22

Basic Test target areas

Test

RC

BE

VI

EM

B Mode

B Mode

B Mode

B Mode

Physio POST Test


System Level Tests - RC, BE, VI+
B Mode

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Test

RC

BC-Mode

BE

VI

EM

BC Mode

BC Mode

BC Mode

Doppler Audio Check - BE, VI, IO, Speakers

Audio

Test Summary and Test Results


The executed tests will produce a series of results which can be found in the Report Files
area. To bring up the information:
1. In the upper right corner, select Reports. This will bring up the Report Files page.
2. Click Test Results to bring up a directory of results.

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3. Find and click Test Results.htm in the Hierarchal listing to show a detailed report of
the test, which may be used for further troubleshooting.

Fig. 58:

4. If multiple TestResults.htm items appear in the log, use the date and time to determine which summary is the most recent.
NOTE

If the E Module test or any of the board tests fails, scroll through
the test results to identify which module/board is the root cause.
Use the information in (Appendix A: Test Results and Test
Summary / p. 54)

5. A brief summary of the test results can also be found in TestSummary.

Transmit test

The transmit test exercises all 192 transmit circuits (EM level test) or all 64 transmit circuits (TR0, TR1, TR2 level tests). Antares has two transmit voltage sources (TXV0 and
TXV1). The transmit test uses TXV0 and then TXV1; the resulting sets of data (192 or 64
rows) are analyzed independently. The outputs of the transmit circuits on the TR board
are routed to the TI board where a resistor combiner combines the 192 or 64 channels
onto one signal line. This signal line is routed from the TI to the RC board. On the RC
board the signal is routed to the RXBF ASIC corresponding to channel 16 and the waveforms are stored in the SRAM of this ASIC. The stored SRAM data is then analyzed.

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Tab. 23

Transmit Receive Tests and Related Failures

Failing EM
board type

Failing EM board data


presentation

Corresponding Image
indication

Troubleshooting Suggestion

TR

Median Pwr to Chan Variation limit failures Typically


1 or 2 channels out of
range, or 8 consecutive
channels corresponding to
TXPG groupings (refer to
(Channel Map / p. 51))

Image may indicate a


dead channel corresponding to the failing channel.
Refer to (Channel
Map / p. 51)to correlate
diagnostic failure to imaging observation

Refer to (Channel
Map / p. 51) to link failing
channel to TR board.

Absolute THI power limit


failures

Image may indicate a


dead channel in THI mode
corresponding to the failing channel, refer to
(Channel Map / p. 51)to
correlate diagnostic failure to imaging observation.

Refer to (Channel
Map / p. 51) to link failing
channel to TR board.

Typically 1 or 2 channels
out of range, or 8 consecutive channels corresponding to TXPG
groupings (refer to (Channel Map / p. 51))
All 192 channels failing
Absolute Median and
Mean Power Limits

The TR test will indicate


which board is failing. Swap
TR boards to ensure the failures are board-related.

The TR test will indicate


which board is failing. Swap
TR boards to ensure the failures are board-related.
If this occurs 1 of the 3 TRs
is the probable cause;
It is possible to remove a TR
board, boot up the system,
and execute TR tests on the
others.
When the defective TR is
removed, the transmit test
will pass on the other TRs

RC

Antares

Absolute Median and


Mean Power limit failures,
where all channels or a
large number of channels
fail. This would be caused
by a problem on the RC
unique to processing of
the combined signal on
the RC.

Image may not indicate a


problem since RC failures
of this type are limited to
diagnostic related hardware and unique diagnostics measurement path.

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Failing EM
board type

Failing EM board data


presentation

Corresponding Image
indication

TI

Absolute Median and


Mean Power limit failures,
where all channels or a
large number of channels
fail. This would caused by
a problem with the resistive combiner on the TI.

Image may not indicate a


problem since TI failures
of this type are limited to
diagnostic related hardware and unique diagnostics measurement path.

RM, BE, VI

RM, BE or VI not known to


cause ONLY a transmit
test failure.

Troubleshooting Suggestion

Receive Test

The receive test exercises all 192 receive circuits (EM/RC level test) or all 64 receive circuits (TR0, TR1, TR2 level tests). The receive test uses two gain settings (26 and 14); the
resulting two sets of data are analyzed independently. The RC board has a stimulus
source that is used for the receive test. This stimulus source is routed to the TI board
where a resistor divider distributes this stimulus to the 192 or 64 channels. From the TI,
these signals are routed to the TR where filtering and gain is applied. From the TR these
signals are routed to the RC board and then the waveforms are stored in the SRAM of
respective RXBF ASICs. The stored SRAM data is then analyzed.

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Tab. 24

Receive Test and Related Failures

Failing EM
board type

Failing EM board data presentation

Corresponding
Image indication

Troubleshooting
Suggestion

TR

Rel to Med Chan Variation Limit failures, typically 1 or 2 channels out of


range

Image may indicate a


dead channel or noise
corresponding to the
failing channel, refer to
(Channel
Map / p. 51)to correlate diagnostic failure
to imaging observation.

Swap TRs and then


repeat test.

RC

One or two channel failures; channel


failures in groups of 16 corresponding
to a RXBF; or all channels failing in a
similar manner.

RM, BE, VI

RM, BE or VI not known to cause


ONLY a receive test failure.

Image may indicate a


dead channel(s) or
noise corresponding to
the failing channel,
refer to (Channel
Map / p. 51) to correlate diagnostic failure
to imaging observation.

Zm System B-Mode Test

If the failing channel(s) remains the


same then the RC
board is the cause.
If the failing channel
moves with the TR
per the (Channel
Map / p. 51) then TR
is the cause

This test inputs a known set of data into the RC board and the system processes this data
from the RC through the DR, EP, and SC sections of the BE and then to the VI board. A
CRC is a method of detecting a 1 bit mismatch. Once a CRC fails, this failure will propagate through the remaining CRC checks. Thus the true failure information is contained in
the first failing CRC read from top to bottom.

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Tab. 25

99

Zm System B-Mode Test.

Failing EM
board type

Failing EM board data presentation

RC

RC can cause CRC failures starting at Gross to subtle image If a DR on the BE


Board is the first failthe DR SA memory checks or EP pers artifacts
ure, the RC has a
Buffer checks on the BE Board.
higher probability than
RC will not cause CRC failures starting
the BE of causing the
at SC Raster or VI Image
failure; If the EP pers
BE can cause CRC failures starting at
Buffer is the first failthe DR SA memory checks, EP Pers
ure, the RC and BE
Buffer checks, or SC Raster
have equal probability
of causing the failure

BE

VI

VI can cause CRC failure starting at


the VI Image check

False Failure

This test sometimes has a problem


with data transfer between BE and VI,
which creates a false failure indication

Corresponding
Image indication

Troubleshooting
Suggestion

Press the freeze button before entering


the test tools menu
and then repeat the
test. If BE to VI transfer problem remains,
then it is a true failure.

Zm System BC-Mode Test

This test inputs a known set of data into the RC board and the system processes this data
from the RC through the DR, EP, FP, and SC sections of the BE and then to the VI board.
A CRC is a method of detecting a 1 bit mismatch. Once a CRC fails, this failure will continue through the remaining CRC checks. Thus the true failure information is contained in
the first failing CRC.

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Tab. 26

Zm System BC-Mode Test

Failing EM Failing EM board data presentation


board type
RC

Corresponding
Image indication

Troubleshooting
Suggestion

RC is likely to cause CRC failures start- Digital image noise


ing at the DR SA memory checks
RC can but is unlikely to cause CRC
failures starting at EP pers Buffer
checks, or FP FPGA Even Pers checks
RC will not cause CRC failures starting
at SC Raster or VI Image on the BE
Board.

BE

BE can cause CRC failures starting at


the DR SA memory checks, EP Pers
Buffer checks, FP FPGA Even Pers
checks or SC Raster

VI

VI can cause CRC failure starting at


the VI Image check

RTC Sequence Test (RC sequence, TR0 sequence, TR1 sequence, TR2
sequence)

RTC FPGA programs the TR boards and RXBF ASICs at high speed. The target registers and tables are first cleared. Patterns are stored in the RC index state machines
tables. A sequence is loaded that is expected to move the patterns out to the TXPG and
RXBF ASICs. The sequence is executed and the results verified.
Tab. 27

RTC Sequence Test and related failures

Failing EM Failing EM board data presentation


board type

Corresponding
Image indication

Troubleshooting
Suggestion

RC

Failures in address range: 0xC000000


to 0xC43FFFF

TR0

Failures in address range: 0xC460000


to 0xC47FFFF

Typically will shutdown imaging, leaving a screen with no


ultrasound image

TR1

Failures in address range: 0xC480000


to 0xC49FFFF

TR interchange; if
failure follows TR
with interchange then
TR board is source of
problem; if failure
does not move then
RC is source of problem

TR2

Failures in address range: 0xC4A0000


to 0xC4BFFFF

TI

Failures in address range: 0xC4C0000


to 0xC4DFFFF

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Failing EM Failing EM board data presentation
board type
RC

101
Corresponding
Image indication

Troubleshooting
Suggestion

Since the RTC is the component used


to implement this test, a RTC failure is
more likely to create failures on
addresses that span multiple boards.
If the LED on RC board is off, this test
is expected to failure.

FE memory (includes RC memory, TR0 memory, TR1 memory, TR2 memory)

Standard memory test performed on all testable registers and memory spaces in the frontend. Buses used are PCI bus between RM and BE; Febus between BE and RC, and
TCbus between RC and TR.
Tab. 28

FE memory (includes RC memory, TR0 memory, TR1 memory, TR2 memory)

Failing EM Failing EM board data presentation Corresponding


board type
Image indication

Troubleshooting
Suggestion

RC

Failures in address range:


0xC000000 to 0xC43FFFF; RXBF
failures

TR0

Failures in address range:


0xC460000 to 0xC47FFFF; TXPG
failures

TR interchange; if failure follows TR with


interchange then TR
board is source of
problem; if failure does
not move then RC is
source of problem

TR1

Failures in address range:


0xC480000 to 0xC49FFFF; TXPG
failures

TR2

Failures in address range:


0xC4A0000 to 0xC4BFFFF; TXPG
failures

RM/BE

Since the RM and BE are used to


implement this test, a RM or BE failure is more likely to create failures on
addresses that span multiple boards.
Also the BE memory test is likely to
fail as well.

Damaged
connector
pin

Damage connector pins


(shorted/open) can create multiple
TCbus related failures.

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DC cal/DC cal check

Adjusts a system parameter, measures DC offset of all 192 channels and verifies that all
are within a set of test limits. The initial parameter adjustment is executed in the tune up
menu. The EM and individual board tests execute the a subsequent verification of limits.
Tab. 29

DC cal/DC cal check

Failing EM
board type

Failing EM board data presentation Corresponding


Image indication

Troubleshooting
Suggestion

TR

Can cause a DC cal failure (more


likely than RC or TI)

RC

Can cause a DC cal failure (less likely


than TR; more likely than TI)

TR interchange; if failure follows TR with


interchange then TR
board is source of
problem; if failure does
not move then RC is
source of problem

TI

Can cause a DC cal failure (least


likely)

Probe Relay test

The probe relay test uses a test method similar to the receive test. Both use a stimulus
generated on the RC board and both route the signals for analysis through the TR to the
RC where the data is stored in the RXBF SRAM for analysis. The main difference is in the
routing of the stimulus on the TI board. For this test the stimulus is routed through the
relays on the TI board before being output to the TR boards.
Tab. 30

Probe Relay test

Failing EM Failing EM board data presentation


board type
RC

An RC board with a receive problem


can cause this test fail. Typically all
relays for probes A, B and C will fail
when the RC board is at fault.

TR

A TR board with a receive problem can


cause this test fail. Typically all relays
for probes A, B and C will fail when the
TR board is at fault.

TI

A true relay fault on the TI board will


create a single fault or a fault with an
entire relay bank.

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Corresponding
Image indication

Troubleshooting
Suggestion

TR Swap

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BE memory

Standard memory test performed on all testable registers and memory spaces in the frontend. Buses used are PCI bus between RM and BE and local BE buses
Tab. 31

BE memory

Failing
Failing EM board data
EM board presentation
type

Corresponding Image indication Troubleshooting


Suggestion

BE

Doppler problems, gross image


problems

All failures should be


caused by BE

VI memory

Standard memory test performed on all testable registers and memory spaces in the frontend. Buses used are PCI bus between RM and VI and local VI buses
Tab. 32

VI memory

Failing
Failing EM board data presentation
EM board
type

Corresponding
Image indication

VI

no image, incorrect
colors

All failures should be caused by VI

Control DAC test

Troubleshooting
Suggestion

The RC board contains the Digital to Analog Converters (DAC) used to control five variable voltages on the Antares system. The five voltages are VTGC, VFC, VMID, TXV0, and
TXV1. This test uses all possible digital inputs to the DACs in ascending order to produce
a ramp analog output. The test then analyzes the Slope (m), Offset (b), and RMS (standard error) for the resulting output (y=mx + b). For VTGC, VFC, and VMID these voltages
are routed from the RC to the TRs. From the TRs, these are routed to a separate measurement signal path that returns to the RC, where a serial Analog to Digital converter
(ADC) is used to measure voltages. For TXV0 and TXV1, the output of the DACs are
routed to the PSA and the resulting TXV0 and TXV1 voltages are routed from the PSA
back to the TRs. The same measurement path to the ADC is used for these voltages as
for the other three voltages. Pass/Fail criteria is based on the calculated Slope, Offset,
and RMS values. A TXV0 and TXV1 trip point test is also part of this test group. Plots of
the data are also displayed as part of the test.

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Tab. 33

Control DAC test

Failing
Failing EM board data presentation
EM board
type
RC

Since the actual DACs and associated circuitry is contained on the RC board, the RC
board is a primary cause of failure for these
tests. Especially slope, offset and gross
RMS failures. The plots that deviate significantly from a straight line are usually indicative of a RC fault.

Corresponding
Image indication

Troubleshooting
Suggestion
Always use either
the EM test group
or TR0 test group
to execute the
Control DAC test.
The control DAC
test in the RC test
group does not
test all of the Control DAC circuitry.

TXV PSM timer failures are caused by RC


only
TR

The TR can cause a RMS failure on the


TXV0 and TXV1 voltages due to a marginal
part in the measurement path that routs the
voltages to the ADC on the RC board.
There are 3 TRs in the system and for this
test only 1 is needed to rout the voltages to
the RC board. When the EM or RC is test is
executed TR0 is used. When TR0 is tested
TR0 is used. When TR1 is tested TR1 is
used. When TR2 is tested TR2 is used. If
an RMS failure occurs due to a RC board
the failure would occur when testing all
three TRs. If a RMS failure occurs due to a
TR board then the failure would only occur
when testing that TR board. A TR board
caused RMS failure is unique to diagnostics
and does not affect imaging performance.

PSA

PSA can cause TXV0 or TXV1 DAC test


failures or TXV0 or TXV1 TRIP failures

TI

There is a high accuracy 2.5V reference on


the TI that is used to calibrate the ADC on
the RC used for the measurement. An
inaccurate 2.5V reference could affect the
measurements, but this is unlikely.

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A2D Diag Test

The RC board has an ADC that is used to measure DC voltages in the system. For A2D
Diag test various system DC voltages on the RC board, the TR board, and the TI board
are routed via multiplexers to this ADC on the RC board. Some of these voltages are created on the PSA and PSD directly, while others are created using regulators on individual
boards.
Tab. 34

A2D Diag Test

Failing
Failing EM board data presentation
EM board
type
RC

Corresponding
Image indication

Troubleshooting
Suggestion

A defective RC could cause all measurements to fail.


A defective RC could cause the voltages
created by RC regulators to fail.

TR

A defective TR could cause those voltages routed from the TR to fail.

TI

A defective TI could cause the voltages


created by RC regulators to fail
A defective TI could cause those voltages
routed from the TR to fail
There is a high accuracy 2.5V reference
on the TI that is used to calibrate the ADC
on the RC used for the measurement. An
inaccurate 2.5V reference could affect
the measurements, but this is unlikely.

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