Flexible

Transistor

King

Electrical

C.

Ho

and

Engineering
University

Sarma

Sastry

Southern

Angeles,

CA

Abstract

Department

California
90089-0781

for a wider
The

This

paper

describes

Transistor

Matrix

eration.

FTM

Matrix,

FTM

addition,
pin

a new

(FTM)

uses

two

can

the

style

called

for large

scale

CMOS

generate

and

of metal.

different

module

the

transistor

dle

gen-

to

better

control

Flexible

Compared

significantly

can

the

results.

aspect

a given

circuit

in

In

ratio,

1/0

sizes.

of a module

generator
style

better

known

called

Gate

Lopez

al.

[10] and

Matrix
cuit

layout

et.

al.

in

others

graded

[6]

and

automatic

lines in a Gate Matrix

of metal
another

of metal

layout

first

proposed

two

layers

area

style

of metal

reduction

In this
ible

paper,

allows

connects.
routing

the
In

area

will

duces

the

achieve

later,

to route
lower

1/0

positions

individual

bound

a layout

been

for large
two

and

algorithm

compact

with
uses
across

the
both
the

width

and
the

[9].

The

desired

aspect

ratio.

output

similar

Matrix
structure

was

to utilize
no

can

be viewed

The

Flex-

module

layout

interwith

this

the

the

is done

layers.

As

top

layer

This
and

of

[1]

to

Input

to the

file

card

of

main-

module

format

an

number
while

transistor

CIF

logic

transis-

generate

the

elimination,

as shown

as a matrix

columns
rows

consist

re-

allows

consist

and

generain SPICE

[7].

layer

tally

in

the

of signal

not

nets.

connected

terconnects

and

(n-plane).

any

diffusion
Not

allows

transistors

when

the

distinction

routing

run
All

bein the

horizon-

p-diffusion

interconnects

have

Interconnects

terminal

restricting

can

the

of signals

in

will

vertically

(metall).

corresponding

of tran-

and

run

to

which

be

are

placed

location
poly

1,

rows.

whereas

terminals

interconnects

their

to

transistors

nets

of metal

Figure
and

nets

Signal

p-plane

matrix.

and

signal

in

columns

between

elements

layer

and
in the

in the

nets

Both

as column

bottom

(n-diffusion)
be placed

symbolically

of intersecting

of interconnects

signal

them

top

any-

of gate

across

the

intwo

planes.

FTM

secondary

and

the

where

as the

specific

Structure
of FTM,

(meta12)

(M3 ) is

However,

by

in

any
circuit

reduces

to the

is a layout

of metal

an addiM3

any

technique

layout

format

be

iteratively

necessary.

layer

of metal.

$1.50

rein-cut
then

in the

The

Separating
and

Rm8d.

the
An

two

to the

signal

(RGnd).

Since

row

only

interconnects

can

be

any

space

placed
left

corresponding
is left

Rm,d

in

three

Vd,d ( Grid)
is

Rmzd.
Rv&i

At
and

v~~

as having

are used by signal

nets

are used by diffusion

R Vdd,

outside

both

the

end

of

RGnd

will

be filled

contacts,

and

in row

any

diffusion

contacts.

R&d

columns

to

planes,
terminal

the

algorithm,
with

To ensure

no transistor

is

R vdd

the

enough

channel

can

and RGnd.

2a shows how each column

ally be viewed

all

is placed

located

of substrate

substrate

rows:

spans

connected

row

in row

beplaced
in rowsR
Figure

are
which

net

not

type
for

planes

interconnect

connected

28th ACM/l EEE Design Automation

.395 -7/91/0006/0475

It

or impose

can

rows

is in a file

space

0-89791

the

is not

n planes.

of the

uses

placement.

assume
input

tween

a single

metal

poly

the

to

layouts;

p and

first

not

i.e.

be referred

is shared

two

It

initial

tor

does

style,

sizing.

be cus-

CMOS

han-

and

transistor

cannot

Permission
to copy without fee all or part of this materml ,S granted
prowded that the copies are not made or distributed for dmect commercial
advantage, the ACM copyright notice and the title of the pubhcation and
Its date appear, and notice m given that copying M by permission of the
Association for Computing Machinery. To copy otherw]se, or to repubhsh,
reqmres a fee and/or specific permission.

01991 ACM

pin

sistors

scale

can

(height/width),

of gate

layers

area

top

realized.

for

ratios

number

known

poly

transistor

et.

any cir-

circuits.

in FTM

A.

Gate
from

is designed

style,

utilizes

on the

Wing

Matri~

layouts

parameters:

and de-

in layouts.

has

is

by

to utilize

CMOS

delays

more

FTM

signals

O.

ratios.

to generate

load

uses only

scale

(FTM),

the

circuits

running

ratio

in [5], and

Matrix

FTM

by

Metal-Metal

large

transistors

be shown

of metal

M3,

FTM,
to

aspect

taining

of the

generation.

capacitive

Matrix

use of diffusion

overlapping

variable

columns

under-

proposed

used

the aspect

Kang

Gate

Matrim
Like

CMOS

has been made

we present

Transistor

scale

due to the fixed

to reduce

over

generation.
also

for

One

layout

efficiently.

by S. M.

the

gate signals

Gate

and no provision

layer

both
used.

first

of

efficiency

can be used to layout

layout,

Furthermore,

The

on

later

in a high

Also,

a layout

being

was

was

which

result

performance.

tional

large

However,

in poly

tomized.

for

Matrix

for
style

style.

heavily

algorithm

styles

of transistors.

to bottom

the

Gate

is a layout

design

The

generate

layout

depends

and

Matrix.

D.

automatically

a pre-defined

lying

layout

following

the

tors.
will

of aspect
used

design

generator

range

algorithm

Gate

Introduction

A module

by

layout

layers

algorithm

positions

(FTM)

- Systems

of

Los

Matrix

five vertical
running

in FTM
tracks.

in meta12.

runs for source

can conceptuTracks

1 and 5

Tracks

2 and 4

and drain

terminals

of

Conference@
Paper 29.1
475

Sigml

column1

net,

column 2

,
,

,
,

Figure
1

Intcmonneot

Figure

Symbolic

1:

FTM

Contsxt

of an arbitrary

circuit

11111

(a)

Ti.(icj):

view

of

a single

% d.

~;=(icj):

FTM

Figure

layout

can

be placed

simplify

the

columns,

all

the

signal.

same
As

parts:

vertical

poly

layout

in

run.

/3c(c):

the

0(s):

several

rows

3c).

Vertical

poly

contact
3a in

to

are given

below

S = {sl,...,s}:}:

Paper 29.1
476

nets

an

the

used

width

r.

~. , t4})

of

and

n plane

effect

several
to

bring

and

of signal

signal

net

s C S.

(see

gate

signals

drain

are
can

contacts

FTM

notation.
with

structure
The

and

the

definitions

examples

thesetofsignal

taken

layout

of various
from

nets.

S(ti),
g(ti),

column

{ii,

=
the

element

24, ilO,

same

i12})

column

with

s5})

the channel of transistor

will be needed if it is an

(rc(tl)

rg(tl)

which

{s2,

= {13})

in which
t;

the

between

source,

are located,

15, ~,j(tl)

r.

gate

and

respectively.

10)

(ti

and the set of rows

[12, 13])

of rows between

gate

respectively.

in-

track

assigned.

~d(t:)

and the set of rows

rg(ti)
and the set of rows

signal nets to which interconnects

to the
ti are connected,
and drain of transistor
(s(tl)

= s1, g(tl)

(~n(s;)
(an(sl)

= s4, d(tl)

{1, 5})

to which

= s2)

signal

net

si is

= 1)

The
its

Us(ti),

tracks

ad(~i):

sistor

rC!Sp.SCtiVely.

nets

algorithm,

A set

of signal

quantities

ists a track
overlap

1.

.,s5})

(~s(ti)j

tCs source

Signal

(S = {sl,..

(0(s1)

of rows

d(ti):

source,

of Figure

Figure

to

of transistor

(tl)

interval

an(si):

configuration.
the

is con-

interval
of rows between
Zg(ti):
Tc(tc).
(Zg(tl)
= [13, 151)

the poly

3b shows the transistor

c IC

~c(ti).
(~d(tl)
= [10,
13])

from

inside

where

icj

sharing

rows

rd(ti):

interval

Td(ti):

Figure

of transistors.

the row

poly

from

anywhere

interconnect

(/3=(s4)

nets

transistor.

rg(ti),

Zs (t;):

diffusion

signals

covers.

the set of rows to which

Several rows

(r.(tl)
= 12,

tran-

transistor
parts

c lC

into
and

transistors

Vertical

drains

except

on

icj

interconnects

T is connected.

set

(ti),

of

divided
runs

(Zn(sl)

s4)

the

drain

to carry

by overlapping

can be assigned

Figure

no

only

of transistors.

source

be

oversized

into

are

sources

p or

have

is formed
of

gates

bring

to the

some

columns.

have

set
U

oversized

in

and

diffusion

a column,

split

runs
the

is located.

we need

be

of a transistor

a different

look

contacts

limit

can

vertical

signal

channel
or

to

To describe

to

a transistor
two

within

The

corresponding

(T = {tl,.

interconnect

tiis assigned.

FTM,

of rows
and

3. A channel

diffusion.

are used

2a will

net to which

(/3i.(ii)

c E S

column

in an intersection

3a,

Since

and

terconnects

With

algorithm

Figure

span

channel

Figure

a channel,

interconnects

(lC

net S; E S covers.

of columns

signal

Tc(ti).
(Z.

in Figure

runs

how

placed

sist or configurations

shown

interconnects.

of

= [1, 2])

nected.

for gate terminals

jog insertion.

at intersections

contacts

show;

several

2b shows

without

runs

of rows signal

interval

(Z_;c(il)

ra??c

3 is used by poly

an actual
To

set

interval

interval

r. (t i ):

Track

only

the

[12, 16])

rneta12

numdl

0)

Internal

of transistors.

layout

, t~, }: the set of transistors.

Zn(s;):

transistors.

of transistor

( a, b ) = open interval
li?llpoly

2:

3: Examples

b ] = closed

[a,

12345

Figure

(c)

= {iCl, . . . , icn,c}:
{ii, . . . ,;12})

IC

T={tI,...
trsck#

(h)

layout

(a)

and

(fYs(tl)

sharing
nets

2, Ud(Sl)

S c S can share
such that

in different

VS; ,Sj C S, Zn(S:)

4})

{2,

diffusion

to which

runs

are

tran-

assigned,

A)

a column:

assignment

are placed

Ud(ti)

drain

a column

signal

tracks,

if there

ex-

nets whose intervals

i.e.

T7a(Sj) # ~ +

an(si)

# ~n(s~).

F$It

Figure

4: Examples

of transistors

sharing

Vdd

................
...
.. -0

sharing

a column

IC

of interconnects

overlap,

can

IC

share

different

a row
signals

Transistors

# /31c(iC~)

sharing

5: (a) Random

Figure

3.1

T can share

a column

if there

exists

t; c T such

rc(ti ) for each transistor

that:

In

Random
the

initial

each placed
(NMOS)

1. Intervals

of vertical

do not overlap,
Vti, tj G
2. Intervals

poly

runs carrying

different

row

T,g(ti)
#g(tj)* Zg(ti)n

of vertical

diffusion

Vti, tJ c T,

Z_g(tj)

runs carrying

4.

(b)

Schematic

different

sig-

in a separate

column.

are not

n Ts(tj)

Us(ti)
# c7$(tj).

c T,

Vti, tj

3. No channel

d(tl)

+ Z_s(ti) n Z.(tj)

= #

# d(tj)

is unique

figures.
initial

5a. Figure

left

accessibility

the

are

for PMOS

in the p-plane
assigned

to any

Furthermore,
placement

row

of an in-

5b is the corresponding

of certain

matrix,

two

are added.

and right

signal

pseudo

boundaries

at the

and

Cleft

columns

nets which

nets

columns

Pseudo-columns

and right-most

and

two

C,jght

of the matrix,

re-

are required

to be accessible

are respectively

connected

to

+ Z_~(ti) n Z_d(tj) = d

same

of the matrix,

rows

as gates

of

rows 12toP and Rbottom

nected

@~c(tj).

initial

for each transistor,

from

n rc(tj)

= #.

the top

nets which

and bottom

the locations

corresponding

In

boundaries

and will

signal

net

to

are con-

respectively.

Figure

rows

are required

of the pseudo

boundaries
steps.

to Rtop whereas

connected

are the top and bottom

Signal

to Rtop and Rbottom,

directly
placement,

at their

i.e.

respectively.

any of the successive

Vti, tj G T, rc(ti)

the

row

are not

A random

All signal

be accessible

assignment

in

transistors

CIe~~ and Cr~ght through

additional
interconnects.
These additional
interconnects
can be placed in either of the planes.

i.e.
Vti, tj G T, ~g(ti)

shown

the

rows

Pseudo
to the

in a separate

in Figure

of

spectively.
from

Cd(tj).

is assigned

transistors,

To ensure
pseudo

and

Interconnects

diagram.

are the left-most

~s(ti)
# ~d(tj).

or ~d(ti)

is shown

schematic

nets

of transistors

empty.

boundaries

S(t:) # S(tj) +- Z$(ti)

placement
signal

Channels

and

verter

i.e.

Vt:, tj c T, ~(ti) # d(tj)

4. Channel

placement

initial

are each placed

(n-plane).

signals

i.e.

nals do not overlap,

or

initial

placement,

Rmzd is left

R bottom

n Zac(iC~) = ~.

Z:c(iCj)

a column:

assignment

or

..

~:

;!
\

of an inverter

A set of transistors

if the
do not

i.e.

a channel

;:

(a)

carrying

ic~ G ICY, ~lc(iCj)

ViCj,

a!
.. ?,... . .

,
:;;

a row:

A set of interconnects
intervals

RH

... .... ..
. . . . .. . . .

.. ...
.. .
::::
~;~:;

Interconnects

;;

.. .............

After

strips

the

are fixed

not be moved

5, signal

nets

by

in is

out is connected

to

R.bottom.
5. For each

tic T, the set of rows rc(ti)

corresponding
Examples

are within

its

plane.

of transistors

3.2

sharing

a column

are shown

in Fig-

ure 4.

3
cuit

objective
with

while

of vertical

cross any vertical

size between

of the

maintaining

The

algorithm

columns
area while

is to layout

using

number

the desired

aspect

the

of columns
ratio,

1/0

cir-

connects

and rows)

between

given

starts

by

circuit.

the rein-cut

generating

The

all the topological

and horizontal
partitions

cross the partitions.

two row partitions

rein-cut

and column
cut

line.

is to mini-

elements

The

is the number
The

is the number

that

vertical

cut

of inter-

horizontal

cut

of column

size

elements

that

initial

Vertical rein-cut first partitions

the set of column elements
into a left and a right
half of similar
sizes such that the
vertical cut size between the two halves is minimized.
Each

place-

After

rein-cut,

the

half is recursively

to minimize

the

single

requirements.

is

cross the partitions.

placement

eliminated

rein-cut

and horizontal

of interconnects

two column

initial

algorithm.

and rows are iteratively

satisfying

a random

random

that

horizontal

pin positions

sizes.

for the given

improved

algorithm

least area (minimum

and transistor
ment

objective

and

mize the number

Algorithm

The

The

Vertical

column

based on [2].

partitioned

element.
Figure

The

until

each partition

partitioning

6a shows the matrix

contains

procedure
of Figure

used is
5a after

Paper 29,1
477

cut line

+Verticsl

::;:;
.. ~;:::.
:~:~
:,.
.. .

::::

~;~~
:::
~:

...7 ..

+J
~~
. . ... .. .. . . .. .
:;
:.
..
:::
.- --+-+

,
:;

---.,

,.
...
7 ::
.......... ......

ti
. .. . .. . . .

crnd
it2
. . . . . . . . . ...+...

. .. .. . . .

. . . .. .

:..,

..

row

(column).

find
will

a column
(row) that
proceed to eliminate

case that

-in. --...

column

eliminating

6:

step

(b)

Vertical

After

rein-cut.

(a)

Four
ing

cdaf-,

points

rections

After

one

partitioning

: tl

. . ... .

.. ... . ..

. ... .. .. i

~:;
. . . . . . . . . . ..o*

reaches

left

(left

::::
::::

after

both

-.,

..
.

(Cteft

Cright

of crx~ht

to right)

cptr

The

possible

Moving

it

after

the complete

vertical

cut size of the matrix

Horizontal
similar

sizes such

first

that

each partition
maximum

from

4 to 3.

3.3
Before

both

horizontal

a bottom

cut

Let

M.(c)

element

half

of

size between

the

l.(i)

interconnect.

Figure

size of the matrix

can be chosen

enough

the rows

arbitrarily.

Instead

rit hm such as the one discussed

procedure

A column

to reduce

(row)

$ic(~)

rein-cut.
is reduced

to other

columns

each iteration,

to

to the

a column

to the left
to the right

ele-

of column

of column

R(i)

in

which

be defined

column

as the set of

in the same row as interconnect

I i ~ R(i),

Zic(i)

I i G R(i),

Zi.

i. Then
< Zic(i)j

# Pic(~)}}

and
=

min{min{Z:C(i)
#

are the left and right

for the channel

(a)

<

~i.(~),

flic(~)}}

can be expanded,
respectively.
interconnect
i c j?=(c), MC(c)

boundaries

within

which

interconnect

With /.(i) and u.(i) for each

can be determined
ss

are assigned

a folding

algo-

M=(c)

uses an

of columns

and

if all the elements

in it

uses the current

as-

( l.(i),

Z&(i)

).

16P=(C)
Let

C(c)

gorithm

(rows).

the algorithm

when

of columns

Let

of transis-

the number

possible
element

in row 7.

of channel

in [8], our algorithm

is eliminated

be moved

purpose

of using

pro-

possible

upper-most

change

interval

Pic(i)

channels

the clean-up

restrict
the interval
of columns
can be moved.
For example,
in

channels

space is left

to which

to fur-

A clean-up

and each interconnect

max{max{~:c(i)

elimination

Since the only

be the
placed

rows.

elements

c can be moved.

interconnects

is possible

partitioned

and horizontal

or row is eliminated,

is to ensure

Paper 29.1
478

and

a signal

row

to rows.

of each transistor,

During

vertical

the set of interconnects

a top

vertical
cut

and

any column

are moved

maximum

back to the

each column

net ss can be moved

net S1 cannot

due to the interconnects

6 to 3.

ei-

row.

column

8, signal

signal

u=(i)

tors are assigned

elimination

the matrix

Each half is recursively

cent tins

Column

assignment

The

the horizontal

shows the mat rix after

The

into

6b shows

from

partitions

planes

two halves is minimized.

until

rein-cut.

is reduced

rein-cut

in each of the two

Figure

but

to

when

to the left-most

to the
moves

column

column

a right

stops

First,

element

Since the spans of interconnects

min-

the

scan.

elimination.

possible

to

procedure

and

procedure

starts
When

cdir-

indicate

elimination,

each interconnect

the

algorithm

set

of columns

moves each column

and

the steps for

and will not

or the scan returns

row

Figure
step.

be

and

after

the

will

direction.

the number

Then,

routine:
the startThe diby cd~r and

describe
is similar

will

column

3.3.1

Cut

partitioning

iteration.

elimination

and c&.

After

reduce

the

in the direction

a complete

lower-most

),

(C/ef~)

is eliminated

the right-most

vertical

such that

or row can be elim-

a column,

at Cptr

after

row.

and

the matrix
in the next

following
will
Row elimination

ment is moved, interconnects

in which a column element

one vertical

cannot

the algorithm
It is often the

and Tptr indicate

scans, respectively.

column

cedure

horizontal

algorithm

and row scans are indicated

columns

a column

in

cptr
and row

starting

column

::

change

The

process is initiated

..

:
..
::
. . . . . . . . ...&...
::
. . .::. . . . . . . .
:~
:..
;:::
,:::

. . . . . . . . . . ...!t2. .

..

.. . .

. . . &..

. . .. .

7: Matrix

.+4

::
:~;

..

rows.

used

To eliminate

the

(right)

ther

..

the

possible

Tdir.

of column

left

ther

Figure

are

and

of column

scanning

;;;

. . . . . . .::
.. .

..

If

to eliminate

can be eliminated,
a row (column).

becomes

variables

Cptr, Tptr,

Cptr

~;~~;

..

to deter-

inat ed.

.. .. ..
::
. .. .. . .. . .. . .. .. ...
::
::-.
.
~:~
::;:

completion

.- . . ..+d

try

stops when no more column

be described.

Figure

Ad,

be eliminated.

will

an iteration

a row will

elimination

T dir, respectively.
column elimination.

(a)

ratio,

should

algorithm

If during

Elimination

... ... .... ...

;:;

. ..
:::::
;f;;

::~

~;f:

aspect

or a row

::.
:
.
,
.::::
~;;;:
..;..;..
B

:::
:.

::,:

~;;::

.
. .. . . . .

::
::

:::

g::

--,

.;:

Gnii ~
.. . .. . . .. .. .. . .. .

..

Jq-+

a column

Ad < Ac (Ad > A=), the

........ ........y.
.
...
:::
...-.:--.y~-0+.

.. . .
::
:

----

.. .. .

~::{~

whether

.:
::
. . . . . . . .:: . .

..

A=, and the desired

ratio,

mine

tl
.. . . .

~;

..

pect

::;;

be moved

be the

tries

to find

while

column

in which

a column

reducing

within

the vertical

c is placed.
M=(c)
cut

where

size around

The

al-

c can
C(c).

row 8 -7 ..

..... ................. .

one used in the previous

....

be assigned

..

~ . . . . . . . . . . . . .. .. . . . . .

M;C(i),

..

cutl (c)

(cw.(c))

be

N-1

i+2

find

a column

the

To relocate

another

occupying

element

that

number

of interconnects

in

channel

If there

be moved.

exists

Otherwise

circuits

>

cut,(c),

est column

left

be added.

If none

proceeds
cut,(c)

of C(c)

to find

the column

the

element

MC(C),

two tracks.

can be added

right

c cannot

not be described

will

find

of C(c)

The

channel

c can

is true

if

be added

to
col-

[3] algorithm

with

is more complicated
However,

assignment

The

tween

and

interval

in which

an interconnect

can be moved

Table

is re-

All

obtained

can

be

by

moved.

nect

i can

x(s)

= {Z~(s~)

intervals

the
The

be moved

in

interval

ill~(i)

be the

in which

of rows

is kfic(i)

Zn(sj)

which

Let

transistors,
=

in

of signal

of
z

which

itl~(i)

Vsi, Sj E 0(s)}

intervals

interval

interconnect
intercon-

Mt(i).

Let

be the set of row

nets

in 0(s)

overlap.

Then
I 2 E x(s),

from

min{min{i

I i ~ x(s),

Zn(s)

< i}}

lines

and top

s can be expanded,

boundaries

respectively.
M.(i)

within

which

transistors

net

the

search

Therefore,

we dont
have a procedure
to find the exact
which interconnect
i can be moved.
To limit
space,

the set of transistors

to be checked
cedure

a pessimistic

every

time

used for checking

estimate

of lkf~ (z) is used.

connected

to i are required

interconnect
the transistors

z is moved.

The

pro-

is the same as to the

3.6 times
trix

has

layout.
The

when

ratios.

Table
ratio

2.8.

also

been

number

average
The

Gate

when

minimum

the transistors

the minimum,

of

number

more

transis-

can generate

area used per transisfor

the resultant
ratio.
is not

Even
the

a positive

out

is

of gate

number

average

Matrix

needed

A delay

carried

layout

maximum

is due to the large

the

and 1789,um2,
generating

the

aspect

ratio

though

the resul-

same

as the

40~o

area only

itt

longer

1.

sized transistors
layout

The

than

sizes are increased

the delay of FTM

desired

size has on the lay-

comparison

for

with

correlation.

the layout

the minimum.

are

the amount

the size of each transistor

the minimum,

half

the bot-

are 19sec., 163sec. and 287sec.,

aspect

obtained

SCMOS

from

The

to the

itt2

time

2 shows

it does show

dif-

by Gate

2pm

twice

reason

The minimum

average

using

such that

are 969pm 2, 1162pm2

alu and itt2

lay of the FTM

layout

using

3 shows the effect of transistors

to 40 times
Currently,
M*(i)
within

the

is about

alu and itt2

ratio,

obtained

by FTM

per gate line for alu is 4.5. With

out area of it t 1. When

).

width

for
from

for itt 1, alu and itt2 are

Figure
9 shows the lay-

respect

itt 1 and

per gate line

aspect

in the

layout

the area obtained

aspect

with

to the desired

Figure

u.(s)

alu

is estimated

are positioned

We think

In both

for ittl,

aspect

Matrix

column

are generated

two different

alu.

of transistors

And,

= ( 1s(s),

[4].

circuits.

are inserted

Gate

1 for itt2

tors per gate line on the average,

respect

signal

No jogs

with

pins

of transistors

in alu.

tant
are the bottom

of

from

of 118, 316 and 474 transis-

for it t 1 and itt 2 is about

for

number

respectively.
=

can

the effectiveness

were obtained

the top and half are accessible

respectively.

and

1/0

of alu with

tor in ittl,

i < Tn(s)}},

elim-

be moved.

area obtained

ratios

the layouts
The

area reduction

layouts
US(S)

circuits

consist

the

aspect

a more efficient
1s(s) = max{max{i

such

being

the channel

cannot

tom. The maximum

area reduction
3770, 1970 and 3570, respectively.

terconnect

i can be moved.

transistor

itt 1 and itt 2 are sequential

1 compares

Matrix.

outs

imposed

to

set of transistors

compaction.

desired

stricted
by column
elements.
Let Jfs (i) be the interval
of rows, imposed
by the signal
net @ac(i), in which
inrows,

three

are minimized.

itt 1 after

accessible

interconnects

to

proceeds

results

and the area used in table

ferent

if one

the

assignment,

We do not have the actual

technology.
Moving

for

the data given in [4] and the average

the procedure

for the transistors

All

it also has to
are assigned

to the row currently

a valid

alu and itt2

columns

from

exists.
3.3.2

is a combinational
circuit.
The Gate Matrix
layouts of itt 1
and SIU was manually
compacted
so that the separation
be-

itt2

used to check if a transistor

paper.

ittl,

that

are used to demonstrate

style.

respectively.

process.

to an existing

first

Circuit
tors,

be moved.

column

in this

the layout

to which

reverse

c cannot

net can be added

to an existing

will

a valid

the algorithm

element

procedure

a clos-

element

uses the lefi-edge

The

to find

on the left,

c can be added.

within

try

the column

column

If column

the algorithm

only

to which

a closest

To check if a signal
umn,

will

can be found

> CutI(c).

any column

algorithm

c can be added.

a row,

the algorithm

the channel

Three

If cui?l(c)

interconnect

as the channels

is assigned

Experimental

element

to eliminate
of transistors

the same column

no channel

column

can

Within

as in moving

to which

assignment

closest

to which

no channel

eliminated.

transistor

a channel,

B.(c) that start at C(C) and extend to the left (right).

If
Cuf[(c) = Ctdr(c),
the algorithm
proceeds to find a column
to C(c)

that

procedure

row

of

tries

all the channels

inated.
Let

the

channel

the algorithm

the row.

8: Moving

to find

Moving

relocate

:{

Figure

being

be moved.

When

. . . . . .. .

except

..

..

columu

section
currently

uses a similar

element

3.3.3

2 . . .. . . . ..+. . ...+.....
1

will

. . . . . z......

3 --;q

the algorithm

a column

xl
5 . . . . . . . . .. . . . . .. . . . . . . . . . . . . . .. .
..
. .. .. .%... .. . . .. .. .
4

to the row

is increased
increased

with

Gate

worst

case

the Gate

are used.

de-

Matrix

However,

to around
becomes

to
Ma-

times

3570 shorter

Paper 29.1
479

3.5 -

t3
~ 2.5 -

.
.

2-

1.5 -

10

20

40

i )

on the

layout

30

transistor sizes
Table

9: Two

Figure

different

Gate

ITM

Matrix
(pm)

name

layouts

aspect

[1] M.

0.5

180958

121264

114390

117216

127428

alu

455490

392768

367200

421200

446000

itt2

1307016

1024556

847878

866680

847400

1: Area

compared

to Gate

Matrix

sizes

area

Breuer,

Idth

Design

class

of Min-cut

Placement

Automation

Conference,

Algopp. 284-

290, 1977.

0.25

ittl

Table

A.

rithms,

ratio

0.75

of transistor

References

of alu

area (~m)

Desired

3: Effect

[2] C.

M.

Fiduccia,

Heuristic

R.

sign Automation

Proc.

Mattheyses,

18h

Network

Conference,

[3] A. Hashimoto,
mizing
Channel

layout

M.

for Improving

Linear-Time
19th De-

pp. 175-181,

J. Ste~ens,
Assignment

Design

Partitions,

Wire
within

Automation

1982.

Routing
by OptiLarge Apertures,

Workshop,

pp.155-168,

1971.
than

Gate

5
This

Matrix

Concluding
paper

second

of metal

shown

in general

that

a layout

effectively
the

is approximately

reduction
multiple

sizes.

in layout
similar

are currently

the

board.

Gate

running

uses the
area.

aspect

ratio

enhanced
These

[5] S. M. Kang,

It

MOS

Matrix
time

the program
aspect ratio

i.e. the p and n blocks

to a checker

under

the

area can be further

p and n blocks

in a way

that

layout

over

In addition,
pin positions,

We believe

that

to reduce
and

The

and

sign, vol.
of

has
and

Layout

authors

would

like

for providing

Dr.

the Gate

enhancements

Omar

Matrix

Wing

and

Dr.

MA:

Paper 29.1
480

ratio

(M3)

Trans.

S. Law,

for MOS

IEEE
320-323,

for High-Speed

Computer-Aided

Sept.

pp. 1671-1675,

and

vol. CAD-2,
K. Zhang,

Technical

Engineering

and Computer

Berkeley,

August

0.

S. Huang,

Wing,
IEEE

Matrix
Electron

to

VLSI

Sgsterns,

1980.

IEEE

Logic

Trans.

no. 3, July

report,

Multiple
Arrays:

Cornputer-

1983.

A. R. Newton,

scm, and A. Sangiovanni-Vincentelli,

User Guide,

Gate

Trans.

1980.

Introduction

Applications,

Design,

De-

1987.

Dense

IEEE

VLSI,

Addison-Wesley,

D. O. Peder-

SPICE

Version

Department

Science,

Univ.

and R. Wang,

Gate

.2G

of Electrical
of California,

1981.

Trans.

4, no. 3, pp. 220-231,

aspect

pp.

Matrix

and H-F.

[9] A. Vladimirescu,

layouts.

out,

2: Resultant

Matrix,

[8] G. D. Micheli,
A. Sangiovanni-VincentelIi,
Constrained
Folding
of Programmable

[10]

Table

Gate
Papers,

no. 5, pp. 886-891,

L. Conway,

Reading,

Aided

to thank

Technical

IEEE

vol. ED-27,

[7] C. Mead,

are organized

development.

CAD-6,

Method

Devices,

the

by using

Layout,

[6] A. D. Lopez,

Acknowledgement

Shuo Huang

Improved

of

Metal-Metal

VLSI

Theory

Digest

1986.

generator

35%

and O. Wing,

IC6AD-86

area reduction

program
is acceptable.
ability
to control
1/0

transistor

[4] S. Huang

remarks

has presented

layer

has been
the
the

and at a 3470 area reduction.

Computer-Aided
July

1985.

Design,

Matrix

Lay-

vol. CAD-