M-Tech (VLSI)

Block diagram generated

RTL Schematic circuit generated

BIET, ECE Dept

Page 1

M-Tech (VLSI)
Exp No 1

Date

LOGIC GATE
Objective: To design the basic Logic gates and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
AND GATE:
Verilog Programming:
Behavioral:
module and1( a, b, y);
input a, b;
output y;
reg y;
always @(a or b)
begin
case ({a, b})
2'b 00: y = 1'b0;
2'b 01: y = 1'b0;
2'b 10: y = 1'b0;
2'b 11: y = 1'b1;
default: y = 1'bz;
endcase
end
endmodule
Structural:
module and1( input a, b, output y);
and g1(y, a, b);
endmodule

BIET, ECE Dept

Page 2

Data Flow:
module and1( input a,b, output y);
assign y = a &b;
endmodule
Test Bench :
module and_tb;
// Inputs reg a;
`
1

reg b;

Outputs wire y;
/

Instantiate the Unit Under Test (UUT)

and1 uut (

.a(a),
.b(b)
.y(y)
);

initial
begin
Initialize Inputs a = 0;
b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 {a, b} =2'b00;
#4 {a, b} =2'b01;
#4 {a, b} =2'b10;
#4 {a, b}= 2'b11;
end

endmodule

Simulated Waveforms :

Block diagram generated

RTL Schematic circuit generated

OR GATE:
Verilog Programming:
Behavioral:
module or1( a, b, y);
input a, b;
output y;
reg y;
always @(a or b)
begin
case ({a, b})
2'b 00: y = 1'b0;
2'b 01: y = 1'b1;
2'b 10: y = 1'b1;
2'b 11: y = 1'b1;
default: y = 1'bz;
endcase
end
endmodule
Structural: module or1(input a,b, output y );
or g1(y, a, b);
endmodule
Data Flow: module or1(input a, b, output y );
assign y = a | b;
endmodule
Test Bench :
module or_tb;
/ Inputs reg a;
` reg b;
/ Outputs wire y;

// Instantiate the Unit Under Test (UUT) or1 uut (

.a(a),
.b(b)
.y(y)
);

initial begin
Initialize Inputs a = 0;
b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 {a, b} =2'b00;
#4 {a, b} =2'b01;
#4 {a, b} =2'b10;
#4 {a, b}= 2'b11;
end
endmodule

Simulated Waveforms :

Block diagram generated

RTL Schematic circuit generated

NAND GATE:
Verilog Programming:
Behavioral:
module nand1( a, b, y);
input a, b;
output y;
reg y;
always @(a or b)
begin
if(a == 0)
y = 1'b1;
else
y = ~b;
end
endmodule
Structural:
module nand1( input a, b, output y);
nand g1(y, a, b);
endmodule
Data Flow:
module nand1( input a, b, output y);
assign y = ~(a & b);
endmodule

Test Bench :

module nand_tb;
/ Inputs reg a;
1 reg b;
/ Outputs wire y;
/ Instantiate the Unit Under Test (UUT) nand1 uut (
.a(a),
.b(b)
.y(y)
);
initial
begin
Initialize Inputs a = 0;
b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 {a, b} =2'b00;
#4 {a, b} =2'b01;
#4 {a, b} =2'b10;
#4 {a, b}= 2'b11;
end
endmodule

Simulated Waveforms :

Block diagram generated

RTL Schematic circuit generated

NOR GATE:
Verilog Programming:
Behavioral:
module nor1( a, b, y);
input a, b;
output y;
reg y;
always @(a or b)
begin
if(a == 1)
y = 1'b0;
else
y = ~b;
end
endmodule
Structural:
module nor1( input a, b, output y );
nor g1(y, a,b);
endmodule
Data Flow:
module nor1( input a, b, output y );
assign y = ~(a|b);
endmodule

Test Bench
module nor_tb;
/ Inputs reg a;
reg b;
/ Outputs wire y;
/ Instantiate the Unit Under Test (UUT) nor1 uut (
.a(a),
.b(b)
.y(y)
);

initial
begin
Initialize Inputs a = 0;
b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 {a, b} =2'b00;
#4 {a, b} =2'b01;
#4 {a, b} =2'b10;
#4 {a, b}= 2'b11;
end
endmodule

Simulated Waveforms:

Block diagram generated

RTL Schematic circuit generated

EXOR GATE:
Verilog Programming:
Behavioral:
module exor1( a, b, y);
input a, b;
output y;
reg y;
always @(a or b)
begin
if (a == b)
y = 1'b0;
else
y = 1'b1;
end
endmodule

Structural:
module exor1( input a, b, output y);
xor g1(y, a, b);
endmodule
Data Flow:
module exor1( input a, b, output y);
assign y = (a ^b);
endmodule

Test Bench :
module exor_tb;
/ Inputs reg a;
1
reg b;
Outputs wire y;
Instantiate the Unit Under Test (UUT) exor1 uut (
.a(a),
.b(b)
.y(y)
);
initial begin
Initialize
Inputs a = 0;
b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 {a, b} =2'b00;
#4 {a, b} =2'b01;
#4 {a, b} =2'b10;
#4 {a, b}= 2'b11;
end
endmodule
/
/

/
/

Simulated Waveforms:

Block diagram generated

RTL Schematic circuit generated

EXNOR GATE:
Verilog Programming:
Behavioral:
module exnor1( a, b, y);
input a, b;
output y;
reg y;
always @(a or b)
begin
if(a == b)
y = 1'b1;
else
y = 1'b0;
end
endmodule
Structural:
module exnor1( input a, b, output y);
xnor g1(y, a,b);
endmodule
Data Flow:
module exnor1( input a, b, output y);
assign y = ~(a ^b);
endmodule
Test Bench :
module exnor_tb;
/ Inputs reg a;
` reg b;
/ Outputs wire y;
/ Instantiate the Unit Under Test (UUT) exnor1 uut (
.a(a),
.b(b)
.y(y) );

initial
begin
Initialize Inputs a = 0;
b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 {a, b} =2'b00;
#4 {a, b} =2'b01;
#4 {a, b} =2'b10;
#4 {a, b}= 2'b11;
end
endmodule

Simulated Waveforms:

Result: The basic Logic gates And, Or, Nand, Nor, Exor and Exnor are designed and their
functional operations are verified using XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 2

Date
ADDERS AND SUBTRACTORS

Objective: To design a basic Adder circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
HALF ADDER:
Verilog Programming:
module halfadder(a,b,sum,carry);
input a;
input b;
output sum;
output carry;
reg sum, carry;
always @(a or b)
begin
sum = a ^ b ;
carry = a & b;
end
endmodule
Test Bench :
module test_v;
reg a;
reg b;
wire sum;
wire carry;
// Instantiate the Unit Under Test
(UUT) halfadder uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry));

initial begin
// Initialize Inputs a = 0;
b = 0;
#100; a = 0; b = 1;
#100; a = 1; b = 0;
#100; a = 1; b = 1;
#100;
end
endmodule
Simulated Waveforms:

Block diagram generated

RTL Schematic circuit generated

FULL ADDER:
Verilog Programming:
module fulladder(a, b,cin, sum, carry);
input a;
input b;
input cin;
output sum;
output carry;
reg sum, carry;
always @(a or b or cin)
begin
sum = a ^ b ^ cin ;
carry = a & b & cin;
end
endmodule
Test Bench :
module t1_v;
reg a;
reg b;
reg cin;
wire sum;
wire carry;
/ Instantiate the Unit Under Test (UUT) fulladder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.carry(carry) );
Initial
begin
/ Initialize Inputs
a = 0; b = 0; cin = 0;
#100; a = 0; b = 0; cin =1;
#100; a = 0; b = 1; cin =0;
#100; a = 0; b =0 ; cin =1;
#100; a = 1; b = 0; cin =0;
#100; a = 1; b = 0; cin =1;
#100; a = 1; b = 1; cin =0;
#100; a = 1; b = 1; cin =1;
end
endmodule

Simulated Waveforms:

Block diagram generated

RTL Schematic circuit generated

HALF SUBTRACTOR:
Verilog Programming:
module gate(a, b, diff, borrow);
input a;
input b;
output diff;
output borrow;
reg diff, borrow;
always @(a or b)
begin
diff = a ^ b ;
borrow = ~a &b;
end
endmodule
Test Bench :
module tb_v;
reg a;
reg b;
wire diff;
wire borrow;
/ Instantiate the Unit Under Test (UUT) gate uut (
.a(a),
.b(b),
.diff(diff),
.borrow(borrow) );
initial
begin
/ Initialize Inputs
a = 0; b = 0;
#100; a = 0; b =1;
#100; a = 1; b =0;
#100; a = 1; b =1;
end
endmodule

Simulated Waveforms:

Block diagram generated

RTL Schematic circuit generated

FULL SUBTRACTOR
Objective: To design a basic full subtractor circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module gate(a, b, c, diff, borrow);
input a;
input b;
input c;
output diff;
output borrow;
wire abar;
reg diff, borrow;
assign abar = ~a;
always @(abar or b or c)
begin
diff = a ^ b ^ c;
borrow = (abar & b)|(abar & c)|(b&c);
end
endmodule
Test Bench :
module tb_v;
reg a;
reg b;
reg c;
wire diff;
wire borrow;
/ Instantiate the Unit Under Test
(UUT) gate uut (
.a(a),
.b(b),
.c(c),
.diff(diff),
.borrow(borrow) );
initial
begin
/ Initialize Inputs

a = 0; b = 0; c = 0;
#100; a = 0; b = 0; cin =1;
#100; a = 0; b = 1; cin = 0;
#100; a = 0; b =0 ; cin =1;
#100; a = 1; b = 0; cin =0;
#100; a = 1; b = 0; cin =1;
#100; a = 1; b = 1; cin =0;
#100; a = 1; b = 1; cin =1;
end
endmodule
Simulated Waveforms:

Result: The Basic Adder and Subractor circuits are designed and there functional operations
are verified using XILINX ISE simulator .

Block diagram generated

RTL Schematic circuit generated

Exp No 3

Date
Parallel Adder

Objective: To design a basic Parallel Adder circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module Parallel_adder( input [3:0] a,b, output [3:0] sum, output carry);
wire c1, c2, c3;
ha u1(a[0], b[0], sum[0], c1);
fa u2(a[1], b[1], c1, sum[1], c2);
fa u3(a[2], b[2], c2, sum[2], c3);
fa u4(a[3], b[3], c3, sum[3], carry);
endmodule
module ha( input a,b, output sum,cout );
assign sum = a ^b;
assign cout=a&b;
endmodule
module fa( input a,b,cin, output sum,cout );
assign sum = a ^ b ^ cin;
assign cout = (a & b)|(b & cin)|(a & cin);
endmodule
Test Bench
/
/

module PA_tb;
Inputs reg [3:0] a; reg [3:0] b;
Outputs wire [3:0] sum; wire carry;

Instantiate the Unit Under Test (UUT) Parallel_adder uut (

.a(a),
.b(b),
.sum(sum),
.carry(carry) );
Initial
begin
Initialize Inputs a = 0; b = 0;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 a = 4'b0001; b =4'b1001;
#4 a = 4'b1011; b =4'b1011;
#4 a = 4'b0011; b =4'b1111;
#4 a = 4'b0101; b=4'b1011;
#4 a = 4'b1001; b=4'b0011;
#4 a = 4'b1001; b=4'b1101;
#4 a = 4'b0111; b=4'b0001;
#4 a = 4'b1011; b=4'b1011;
#4 a =4'b01111;b=4'b1111;
end
endmodule

Simulated Waveforms:

Result: Basic Parallel Adder circuit is designed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No

Date
Carry Select Adder

Objective: To design a basic Carry Select Adder circuit and to verify its functional operation
using VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module carry_select_adder(
input [3:0] a,b,
input cin,
output [3:0] sum,
output cout);
wire s01, s02, s03, s04, s11, s12, s13, s14, c01, c02, c03, c04, c11, c12, c13, c14,
c1, c2, c3;
fa u1(a[0], b[0], 0,s01,c01);
fa.u2(a[1], b[1], 0,s02,c02);
fa.u3(a[2], b[2], 0,s03,c03);
fa u4(a[3], b[3],0,s04,c04);
fa u5(a[0], b[0], 1,s11,c11);
fa.u6(a[1], b[1], 1,s12,c12);
fa.u7(a[2], b[2], 1,s13,c13);
fa.u8(a[3], b[3], 1,s14,c14);
mux m1(s01,s11,cin,sum[0]);
mux m2(s02,s12,c01,sum[1]);
mux m3(s03,s13,c02,sum[2]);
mux m4(s04,s14,c03,sum[3]);
mux m5(c01,c11,cin,c1);
mux m6(c02, c12, c1, c2);
mux m7(c03, c13, c2, c3);
mux m8(c04, c14, c3, cout);
endmodule
module fa(input a,b,cin, output sum,cout);

assign sum = a ^ b ^ cin;

assign cout = (a & b)|(b & cin)|(a & cin);
endmodule
module mux( input a,b, input select, output y);
assign y = ((select == 0)?a:b);
endmodule
Test Bench:
module cs_adder_tb;
/ Inputs reg [3:0] a; reg [3:0] b; reg cin;
/ Outputs wire [3:0] sum; wire cout;
/ Instantiate the Unit Under Test (UUT) carry_select_adder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout) );
initial
begin
/ Initialize Inputs a = 0; b =0; cin = 0;
/ Wait 100 ns for global reset to finish #100;
// Add stimulus here
/ a = 4'b1001;
b = 4'b0110; cin = 0;
#4 cin = 1;
#4 a = 4'b1010; b = 4'b0110; cin = 1;
#4 cin = 0;
#4 a = 4'b1101; b = 4'b0010; cin = 0;
#4 cin = 1;
#4 a = 4'b1011; b = 4'b1110; cin = 0;
cin = 1;
end
endmodule

Simulated Waveforms:

Result: Basic Carry Select Adder circuit is designed and its functional operation is verified
using XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 4

Date
3 to 8 DECODER

Objective: To design a basic 2 to 4 decoder circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module dec3x8( a,b,c,E, y);
input a,b,c,E;
output [7:0]y;
wire abar;
wire[7:0]y1;
reg [7:0] y;
assign abar = ~a;
dec2x4 dec1(b, c, abar, y1[3:0]);
dec2x4dec2(b,c,a, y1[7:4]);
always @(E or a or b or c or y1)
begin if(E == 1)
y[7:0]=y1[7:0];
else
y = 7'bz;
end
endmodule
DEC2x4:
module dec2x4( input a,b,E,output [3:0] y);
assign y[0] = (~a) & (~b) & E ;
assign y[1] = (~a) & (b) & E ;
assign y[2] = (a) & (~b) & E ;
assign y[3] = (a) & (b) & E ;
endmodule

Test Bench:
module dec3x8_tb;
/ Inputs reg a; reg b; reg c; reg E;
/ Outputs wire [7:0] y;
/ Instantiate the Unit Under Test (UUT) dec3x8 uut (
.a(a),
.b(b),
.c(c),
.y(y) );
initial begin
/ Initialize Inputs
a=0;b=0; c=0;
#100; E=1;
// Add stimulus here end
always begin
#8 a =~a;
#4 b =~b;
#2 c =~c;
end
endmodule
Simulated Waveforms:

Result: Basic 3 to 8 decoder circuit is designed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 5

Date
8 to 3 ENCODER

Objective: To design a basic 8 to3 encoder circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module beh(i, e, y);
input [7:0] i;
input e;
output [2:0] y;
reg [2:0] y;
always @(e or i)
begin
if(e==1'b1)
begin
case(i)
4'b00000001: y=2'b000;
4'b00000010: y=2'b001;
4'b00000100: y=2'b010;
4'b00001000: y=2'b011;
4'b00010000: y=2'b100;
4'b00100000: y=2'b101;
4'b01000000: y=2'b110;
4'b10000000: y=2'b111;
endcase
end
else
begin
y =2'bzz;
end
end
endmodule

Test Bench :
module enc_tb;
/ Inputs reg [7:0] i; reg e;
/ Outputs wire [2:0] y;
/ Instantiate the Unit Under Test (UUT) enc_beh uut (
.i(i),
.e(e),
.y(y) );
initial
begin
/ Initialize Inputs i = 0;
e = 1;
/ Wait 100 ns for global reset to finish #100;
/ Add stimulus here
#4 i=8'b00000001;
#4 i=8'b00000010;
#4 i=8'b00000100;
#4 i=8'b00001000;
#4 i=8'b00010000;
#4 i=8'b00100000;
#4 i=8'b01000000;
#4 i=8'b10000000;
end
endmodule
Simulated Waveforms:

Result: Basic 8 to3 encoder circuit is designed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp no 6

Date
1: 4 DEMULTIPLEXER

Objective: To design a basic 1:4 de-multiplexer circuit and to verify its functional operation
using VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module demux ( din,sel,dout);
output [3:0] dout ;
reg [3:0]dout;
input din ;
wire din ;
input [1:0]sel;
wire [1:0] sel;
always @ (din or sel)
begin
case (sel)
0 : dout = {din,3'b000};
1 : dout = {1'b0,din,2'b00};
2 : dout ={2'b00,din,1'b0};
default : dout={3'b000,din};
endcase
end
endmodule
Test Bench :
module test_v;
reg din;
reg [1:0] sel;
wire [3:0] dout;
/ Instantiate the Unit Under Test
(UUT) demux uut (
.din(din),
.sel(sel),
.dout(dout)
);
Initial
begin
/ Initialize Inputs

din =1; sel =0;

#100; din =1; sel =1;
#100; din =1; sel =2;
#100; din =1; sel =3;
#100;
end
endmodule

Simulated Waveforms:

Result: 1:4 demultiplexer circuit is designed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 7

Date
8:1 MULTIPLEXER

Objective: To design a basic 8:1 multiplexer circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module beh(d, e, s, y, ybar);
input [7:0] d;
input [2:0] s;
input e;
output y;
output ybar;
reg y ;
reg ybar;
always @(s or d or e)
if(e == 1'b1)
begin
y=4'bzzzz;
end
else
begin
case(s)
3'b000 : y=d[0];
3'b001 : y=d[1];
3'b010 : y=d[2];
3'b011 : y=d[3];
3'b100 : y=d[4];
3'b101 : y=d[5];
3'b110 : y=d[6];
3'b111 : y=d[7];
endcase
end
endmodule

Testbench
module tb_v;
reg [7:0] d;
reg e;
reg [2:0] s;
wire y;
wire ybar;
/ Instantiate the Unit Under Test (UUT) beh uut (
.d(d),
.e(e),
.s(s),
.y(y),
.ybar(ybar)
);
initial
begin
/ Initialize Inputs
e = 1;s = 3'b000;d = 8'b10101010;
#100; e=0;s=3'b000;d=8'b10101010;
#100; e=0;s=3'b001;d=8'b10101010;
#100; e=0;s=3'b010;d=8'b10101010;
#100; e=0;s=3'b011;d=8'b10101010;
#100; e=0;s=3'b100;d=8'b10101010;
#100; e=0;s=3'b101;d=8'b10101010;
#100; e=0;s=3'b110;d=8'b10101010;
#100; e=0;s=3'b111;d=8'b10101010;
#100;
end
endmodule
Simulated waveforms

Result: 8:1 Multiplexer circuit is designed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 8

Date
4 BIT COMPARATOR

Objective: To design a basic comparator circuit and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module beh(A, B, AeqB, AgtB, AltB);
input [4:0] A;
input[4:0]B;
outputAeqB;
outputAgtB;
output AltB;
reg AeqB,AgtB,AltB;
always@(AorB)
begin
AeqB = 0;
AgtB = 0;
AltB = 0;
if(A ==B)
AeqB =1;
else if (A >B)
AgtB = 1;
else
AltB = 1;
end
endmodule
Test Bench :
module tb_v;
reg [4:0] A;
reg [4:0] B;
wire AeqB;
wire AgtB;
wire AltB;
// Instantiate the Unit Under Test
(UUT) beh uut (
.A(A)

.B(B),
.AeqB(AeqB),
.AgtB(AgtB),
.AltB(AltB)
);
Initial
begin
// Initialize Inputs A = 4'b0000;B = 4'b0000;
#100;A=4'b0001;B=4'b0000;
#100;A=4'b0000;B=4'b0001;
#100;
end
endmodule
Simulated Waveforms:

Result: Basic 4 bit comparator gate is designed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 9

Date
FLIPFLOPS
Objective: To design basic Flip-flops and to verify their functional operation using VERILOG
programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
SR Flip Flop:
Verilog Programming:
module srff(q,q1,r,s,clk);
output q,q1;
input r,s,clk;
reg q,q1;
always @(posedge clk)
begin
q=1'b0;
q1=1'b1;
case({s,r})
{1'b0,1'b0}: begin q=q; q1=q1; end
{1'b0,1'b1}:begin q=1'b0; q1=1'b1;end
{1'b1,1'b0}: begin q=1'b1; q1=1'b0;end
{1'b1,1'b1}:begin q=1'bx;q1=1'bx;end
endcase
end
endmodule
Test Bench:
module test_sr;
reg s;
reg r;
reg clk;
wire q;
wire q1;
// Instantiate the Unit Under Test
(UUT) srff_beh uut (
.S(S),
.R(R),
.CLK(CLK),
.q(q),
.q1(q1)
);
Initial
begin
// Initialize Inputs

S = 0; R = 0; CLK = 0;
#100;S=1;R=0;CLK=0;
#100; S =0;R=1;CLK = 0;
#100; S = 0; R = 0;CLK = 1;
#100; S = 0; R = 1;CLK = 1;
#100; S = 1; R = 0;CLK = 1;
#100; S = 1; R = 1;CLK = 1;
#100;
end
endmodule

Simulated Waveform:

Block diagram generated

RTL Schematic circuit generated

JK FLIPFLOP:
Verilog Programming:
module jk_beh(j,k,clk,q,qb);
input j;
input k;
input clk;
output q;
output qb;
reg q, qb;
initial
begin
q=1'b0;
qb=1'b1;
end
always @(posedge clk)
begin
case({j,k})
{1'b0,1'b0}:begin q=q;qb=qb; end
{1'b0,1'b1}:begin q=1'b0;qb=1'b1; end
{1'b1,1'b0}:begin q=1'b1;qb=1'b0; end
{1'b1,1'b1}:begin q=1'b1;qb=1'b0; end
endcase
end
endmodule
Test Bench:
module test_jk;
reg j;
reg k;
reg clk;
wire q;
wire qb;
/ Instantiate the Unit Under Test (UUT) jk_beh uut (
.j(j),
.k(k),
.clk(clk),
.q(q),
.qb(qb)
);
initial
begin
/ Initialize Inputs
j = 0; k = 0; clk = 0;
#50; j = 0; k = 0;clk=1;
#100; j = 0; k = 1;clk=0;
#50; j = 0; k = 1; clk =1;
#100; j = 1; k = 0;clk=0;
#50; j = 1; k = 0; clk = 1;
#100; j = 1; k = 1; clk = 0;
#50; j = 1; k = 1; clk = 1;
#100;

end
endmodule
Simulated Waveform:

Block diagram generated

RTL Schematic circuit generated

D FLIPFLOP:
Verilog Programming:
module dfp(D,CLK,Q);
input D;
output Q;
input CLK;
reg Q;
always @(posedge CLK)
Q = D;
endmodule
Test Bench:
module test_D;
reg D;
reg CLK;
wire Q;
/ Instantiate the Unit Under Test (UUT) dfp uut (
.D(D),
.CLK(CLK),
.Q(Q)
);
initial
begin
/ Initialize Inputs
D = 0; CLK = 0;
#100; D = 0; CLK = 1;
#100; D = 1; CLK = 0;
#100; D = 1; CLK = 1;
#100;
end
endmodule
Simulated waveform:

Block diagram generated

RTL Schematic circuit generated

T FLIPFLOP:
Verilog Programming:
module t(q,q1,t,clk);
input t,clk;
output q,q1;
reg q,q1;
initial
begin
q=1'b1;
q1=1'b0;
end
always@(posedge clk)
begin
if(t==1'b0)
begin
q=q;
q1=q1;
end
else
begin
q=~q;
q1=~q1;
end
end
endmodule
Test Bench:
module test_tflip;
reg t;
reg clk;
wire q;
wire q1;
/

Instantiate the Unit Under Test (UUT) t uut (

.q(q),
.q1(q1),
.t(t),
.clk(clk) );
initial
begin
/ Initialize Inputs
t = 0; clk =0;
#100; t = 0; clk=1;
#100; t = 1; clk=0;
#100; t = 1; clk=1;
#100;
end
endmodule

Simulated Waveform:

Result: The basic flip-flops are designed and their functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 10

Date
MOD 10 DECADE COUNTER

Objective: To design basic mod 10 decade counter and to verify its functional operation using
VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
Verilog Programming:
module
modcounter(clk,reset,dout);
output [3:0] dout ;
reg [3:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout=0;
always @(posedge (clk))
begin
if (reset) dout <=0;
else if (dout<9)
dout <= dout+1;
else
dout <= 0;
end
endmodule
Test Bench:
module test;
reg clk;
reg reset;
Outputs
wire [3:0] dout;
// Instantiate the Unit Under Test
(UUT) modcounter uut (
.clk(clk),
.reset(reset),
.dout(dout)

);
initial
begin
clk = 0;
reset = 0;
#200;
reset = 1'b1;
end
always #5 clk= ~clk;
endmodule
Simulated Waveform:

Result: Mod 10 decade counter is de signed and its functional operation is verified using
XILINX ISE simulator

Block diagram generated

RTL Schematic circuit generated

Exp No 11

Date
PATTERN RECOGNIZER USING MEALY FSM

Objective: To design a Mealy finite state machine pattern recognizer of bit sequence of 101
using VERILOG programming language.
Tools Required:
3. XILINX ISE Project Navigator
4. Personal Computer
State Diagram :

Verilog Programming:
module mealy(clk, reset, a, y);
input clk;
input reset;
input a;
output y;
reg [1:0] state, nextstate;
parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;
always @(posedge clk, posedge reset)
if(reset)
state <= s0;
else state <= nextstate;
always@(*)
case(state)
s0 : if (a )
nextstate =s0;
else
nextstate = s1;
s1 : if (a ) nextstate
=s2; else
nextstate = s1;
s2 : if (a )
nextstate =s0;

else
nextstate = s1;
default : nextstate = s0;
endcase
assign y = (a & state==s2);
endmodule
Test Bench:
module test_v;
reg clk;
reg reset;
reg a;
wire y;
/ Instantiate the Unit Under Test (UUT) meelay uut (
.clk(clk),
.reset(reset),
.a(a),
.y(y)
);
initial
begin
/ Initialize Inputs
clk = 0; reset = 0; a = 1'b0;
#10; a = 1'b1;
#10; a = 1'b0;
#10; a = 1'b0;
#10; a = 1'b1;
#10; a = 1'b0;
#10; a = 1'b1;
#10; a = 1'b0;
#10; reset = 1 ; a = 1'b1;
#10; a = 1'b0;
#10;
end
always #5 clk = ~ clk;
endmodule

Simulated waveform:

Result: A Mealy finite state machin e pattern recognizer of bit sequence of 101 is designed
and its operation is verified using XILINX I SE simulator.

Block diagram generated

RTL Schematic circuit generated

PATTERN RECOGNIZER USING MOORE FSM

Objective: To design a Moore finite state machine pattern recognizer of bit sequence of 101
using VERILOG programming language.
Tools Required:
1. XILINX ISE Project Navigator
2. Personal Computer
State Diagram :

Verilog Programming:
module moore(clk, reset, a, y);
input clk;
input reset;
input a;
output y;
reg [1:0] state, nextstate;
parameter s0 = 3'b000;
parameter s1 = 3'b001;
parameter s2 = 3'b010;
parameter s3 = 3'b011;
always @(posedge clk, posedge reset)
if(reset)
state <= s0;
else
state <= nextstate;
always@(*)
case(state)
s0 : if (a)
nextstate =s0;

else
nextstate = s1;
s1 : if (a)
nextstate =s2;
else
nextstate = s1;
s2 : if (a)
nextstate =s0;
else
nextstate = s3;
s3 : if (a)
nextstate =s2;
else
nextstate = s1;
default : nextstate = s0;
endcase
assign y = (a & state==s3);
endmodule
Test Bench:
module test_v;
reg clk;
reg reset;
reg a;
wire y;
/ Instantiate the Unit Under Test (UUT) moore uut (
.clk(clk),
.reset(reset),
.a(a),
.y(y)
);
initial
begin
/ Initialize Inputs
clk = 0; reset = 0; a = 1'b0;
#10; a = 1'b1;
#10; a = 1'b0;
#10; a = 1'b0;
#10; a = 1'b1;
#10; a = 1'b0;
#10; a = 1'b1;
#10; a = 1'b0;
#10; reset = 1 ; a = 1'b1;
#10; a = 1'b0;
#10;
end
always #5 clk = ~ clk;

endmodule

Simulated waveform:

Result: A Moore finite state machine pattern recognizer of bit sequence of 101 is designed
and its operation is verified using XILINX I SE simulator.