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NTLTS3107P

Power MOSFET

20 V, 8.3 A, Single PChannel,


Micro8 Leadless Package
Features

Low RDS(on) for Extended Battery Life


Surface Mount Micro8 Leadless for Improved Thermal Performance
Low Profile (<1.0 mm) Optimal for Portable Designs
Low TurnOn Voltage
This is a PbFree Device

Applications

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V(BR)DSS

RDS(on) TYP
12.2 mW @ 4.5 V

20 V

Optimized for Load Management Applications


Charge Control in Battery Powered Systems
Cell Phones, DSC, Notebooks, Portable Games, etc.

26.2 mW @ 1.8 V
PChannel MOSFET
S

Symbol

Value

Unit

DraintoSource Voltage

VDSS

20

GatetoSource Voltage

VGS

$8.0

ID

8.3

Continuous Drain
Current (Note 1)

Steady State

TA = 25C
TA = 85C

6.0

t v 10 s

TA = 25C

12

Power Dissipation
(Note 1)

Steady State

TA = 25C

Continuous Drain
Current (Note 2)

Steady State

PD

t v 10 s

D
W

1.6

TA = 25C

ID

TA = 25C

3.7
W

IDM

25

TJ, TSTG

55 to
150

Source Current (Body Diode)

IS

1.6

Lead Temperature for Soldering Purposes


(1/8 in from case for 10 s)

TL

260

tp = 10 ms

Operating Junction and Storage Temperature

THERMAL RESISTANCE RATINGS


Parameter

Symbol

Max

Unit

JunctiontoAmbient Steady State (Note 1)

RqJA

80

C/W

JunctiontoAmbient t v 10 s (Note 1)

RqJA

38

C/W

JunctiontoAmbient Steady State (Note 2)

RqJA

160

C/W

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surfacemounted on FR4 board using 1 sq. in. pad size
(Cu. area = 1.127 sq. in. [1 oz] including traces).
2. Surfacemounted on FR4 board using minimum recommended pad size
(Cu. area = TBD sq. in.).

Semiconductor Components Industries, LLC, 2005

1
1

0.8

October, 2005 Rev. 0

MARKING
DIAGRAM

5.9

PD

Pulsed Drain
Current (Note 1)

3.3
TA = 85C

Power Dissipation
(Note 2)

8.3 A

15.6 mW @ 2.5 V

MAXIMUM RATINGS (TJ = 25C unless otherwise stated)


Parameter

ID MAX

Micro8 Leadless
CASE 846C
A
Y
WW
G

3107
AYWW
G

= Assembly Location
= Year
= Work Week
= PbFree Package

PIN ASSIGNMENT
Drain

Drain

Drain
Drain

Source

Source

Source

Gate

Drain

(Bottom View)

ORDERING INFORMATION
Device

Package

Shipping

NTLTS3107PR2G

Micro8
(PbFree)

2500/Tape & Reel

For information on tape and reel specifications,


including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

Publication Order Number:


NTLTS3107P/D

NTLTS3107P
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise specified)
Symbol

Test Condition

Min

DraintoSource Breakdown Voltage

V(BR)DSS

VGS = 0 V, ID = 250 mA

20

DraintoSource Breakdown Voltage


Temperature Coefficient

V(BR)DSS/TJ

Parameter

Typ

Max

Unit

OFF CHARACTERISTICS
V
11

Zero Gate Voltage Drain Current

IDSS

VGS = 0 V,
VDS = 16 V

GatetoSource Leakage Current

IGSS

VDS = 0 V, VGS = $8.0 V

TJ = 25C

mV/C
10

mA

100

nA

1.2

ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
DraintoSource On Resistance

Forward Transconductance

VGS(TH)
VGS(TH)/TJ
RDS(on)

gFS

VGS = VDS, ID = 250 mA

0.45
3.4

mV/C

VGS = 4.5 V, ID = 8.0 A

12.2

16

VGS = 2.5 V, ID = 7.0 A

15.6

21

VGS = 1.8 V, ID = 5.8 A

26.2

VDS = 5 V, ID = 8.0 A

25

mW

CHARGES AND CAPACITANCES


Input Capacitance

CISS

Output Capacitance

COSS

Reverse Transfer Capacitance

CRSS

4645

6500

VGS = 0 V, f = 1 MHz,
VDS = 16 V

465

650

285

400
60

VGS = 4.5 V, VDS = 16 V,


ID = 8.0 A

Total Gate Charge

QG(TOT)

40

Threshold Gate Charge

QG(TH)

3.0

GatetoSource Gate Charge

QGS

GatetoDrain Miller Charge

QGD

11

td(on)

30

pF

nC

7.0

SWITCHING CHARACTERISTICS (Note 4)


TurnOn Delay Time
Rise Time
TurnOff Delay Time
Fall Time

tr
td(off)

VGS = 4.5 V, VDS = 10 V,


ID = 8.0 A, RG = 3.0 W

tf

ns

20
250
80

DRAINSOURCE DIODE CHARACTERISTICS (Note 3)


Forward Diode Voltage

Reverse Recovery Time

VSD

VGS = 0 V,
IS = 1.6 A

TJ = 25C

0.7

TJ = 125C

0.5

tRR

75

Charge Time

ta

28

Discharge Time

tb

Reverse Recovery Charge

VGS = 0 V, dIS/dt = 100 A/ms,


IS = 1.6 A

QRR

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2

100

ns

47
81.5

3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.


4. Switching characteristics are independent of operating junction temperatures.

1.2

nC

NTLTS3107P

5V

4V

ID, DRAIN CURRENT (A)

4.5 V

24
3.6 V
3.2 V

16

2.8 V
2.4 V

RDS(on), DRAINTOSOURCE RESISTANCE (W)

32

VGS = 10 V

2V

TJ = 125C

Figure 2. Transfer Characteristics

0.018
TJ = 25C
0.014
TJ = 55C
5

10
15
20
ID, DRAIN CURRENT (A)

25

30

0.026
VGS = 2.5 V

TJ = 25C

0.018

TJ = 55C

0.014

0.01

0.019
VGS = 2.5 V

0.017
VGS = 3.5 V

0.015
VGS = 4.5 V
6

12

18

24

30

ID, DRAIN CURRENT (A)

RDS(on), DRAINTOSOURCE RESISTANCE (W)

TJ = 25C

0.016

10
15
20
ID, DRAIN CURRENT (A)

25

30

Figure 4. OnResistance versus


Drain Current and Temperature

0.02

0.018

TJ = 125C

0.022

Figure 3. OnResistance versus


Drain Current and Temperature
RDS(on), DRAINTOSOURCE RESISTANCE (W)

Figure 1. OnRegion Characteristics

TJ = 125C

VGS, GATETOSOURCE VOLTAGE (V)

0.022

0.014

TJ = 55C

TJ = 25C

VDS, DRAINTOSOURCE VOLTAGE (V)

VGS = 4.5 V

16

10

0.026

0.01

24

1.8 V

1.2 V

RDS(on), DRAINTOSOURCE RESISTANCE (W)

ID, DRAIN CURRENT (A)

32

0.06
0.055
0.05
0.045

ID = 13.2 A

0.04
0.035
0.03
0.025

ID = 3.5 A

0.02
0.015
0.01

Figure 5. OnResistance versus Drain Current


and Gate Voltage

VGS, GATETOSOURCE VOLTAGE (V)

Figure 6. OnResistance versus Gate Voltage

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3

1.4

0.2
VGS, THRESHOLD VARIANCE (V)

RDS(on), DRAINTOSOURCE RESISTANCE


(NORMALIZED)

NTLTS3107P

ID = 8 A
VGS = 4.5 V
1.2

0.8

0.6

50

25

25

50

75

100

125

150

VGS, GATETOSOURCE VOLTAGE (V)

C, CAPACITANCE (pF)

0.3
0.4
50

25

25

50

75

100

Figure 8. Threshold Voltage

6000
4000

Coss

0
4

12

16

125 150

5
ID = 3.2 A
TJ = 25C

4.5
4
3.5
3
2.5
2
1.5
1
0.5
0

20

10

20

30

40

50

60

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (V)

Qg, TOTAL GATE CHARGE (nC)

Figure 9. Capacitance Variation

Figure 10. GatetoSource and


DraintoSource Voltage versus Total Charge

10000

100
IS, SOURCE CURRENT (A)

VDS = 10 V
ID = 1 A
VGS = 10 V

1000
t, TIME (ns)

0.2

Figure 7. OnResistance Variation with


Temperature

Ciss

0.1

TJ, JUNCTION TEMPERATURE (C)

TJ = 25C
VGS = 0 V

2000

TJ, JUNCTION TEMPERATURE (C)

10000
8000

ID = 250 mA

0.1

td(off)
100

tf

10

td(on)
tr

10

100

VGS = 0 V
TJ = 25C

10

0.1

0.4

0.8

1.2

1.6

RG, GATE RESISTANCE (W)

VSD, SOURCETODRAIN VOLTAGE (V)

Figure 11. Resistive Switching Time


Variation versus Gate Resistance

Figure 12. Diode Forward Voltage versus


Current

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NTLTS3107P
PACKAGE DIMENSIONS
MICRO8 LEADLESS
CASE 846C01
ISSUE B

INDEX AREA

2X

W
Y

SEATING
PLANE

NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETER.
3. THE TERMINAL #1 IDENTIFIER AND TERMINAL
NUMBERING CONVENTION SHALL CONFORM TO
JESD 951 SPP012. DETAILS OF TERMINAL #1
IDENTIFIER ARE OPTIONAL, BUT MUST BE
LOCATED WITHIN THE ZONE INDICATED. THE
TERMINAL #1 IDENTIFIER MAY BE EITHER A
MOLD OR MARKED FEATURE.
4. DIMENSION D APPLIES TO METALLIZED
TERMINAL AND IS MEASURED BETWEEN
0.25 MM AND 0.30 MM FROM TERMINAL TIP.
DIMENSION L1 IS THE TERMINAL PULL BACK
FROM PACKAGE EDGE, UP TO 0.1 MM IS
ACCEPTABLE. L1 IS OPTIONAL.
5. DEPOPULATION IS POSSIBLE IN A
SYMMETRICAL FASHION.
6. OPTIONAL SIDE VIEW CAN SHOW LEADS 5 AND
8 REMOVED.

AA
8
7

NOTE 6

6
5

0.15 T
K AA
C

2X

TOP VIEW

0.15 T

0.10 T

8X

DIM
A
B
C
D
E
F
G
H
J
K
L
L1
P
U

0.08 T

NOTE 4

0.10 T W Y
0.05 T W
D

8X

SIDE VIEW

8X

6X

DETAIL Z

L1

NOTE 4

F
P

SOLDERING FOOTPRINT*

DETAIL Z
U

MILLIMETERS
MIN
MAX
3.30 BSC
3.30 BSC
0.85
0.95
0.25
0.35
1.30
1.50
2.55
2.75
0.65 BSC
0.95
1.15
0.25 BSC
0.00
0.05
0.35
0.45
0.00
0.10
1.28
1.38
0.20

4X

2.75
H
VIEW AAAA
1.23

1.50

0.40
8X

3.60

0.58

8X 0.33

0.65 PITCH

*For additional information on our PbFree strategy and soldering


details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
1 suitability of its products for any particular purpose, nor does SCILLC assume any liability
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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NTLTS3107P/D

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