Beruflich Dokumente
Kultur Dokumente
Controllability
Observability
Others
Testability Metrics including
o SCOAP
o PCOLA/SOQ
o Sensitized Path Oriented Testability Scoring or SPOTS (TM)
Structured DFT for ICs
Fault Models and Simulation
Automatic Test Pattern Generation (ATPG)
Scan Concepts including MUX DFF and LSSD
Random Access Scan
Test Compression
Low Pin Count Test (LPCT)
At-Speed Testing Using Scan
Scan Standards for ICs (IEEE-1500, 1149.7)
IDDQ Testing
Logic BIST
Memory BIST
Board Level DFT and BIST
Ad Hoc Design for Testability
Electronic Manufacturing Test Strategies
Boundary Scan (JTAG/IEEE-1149.1)
JTAG and IEEE-1149.4, .6, .7
PCOLA/SOQ for various test strategies
Probing and Fixturing Guidelines
Flying Probe Testability Guidelines
Vectorless Test and the IEEE-1149.8.1
Automatic Optical and X-Ray Inspectability
Electrical Design Guidelines
Partitioning to Functionally Independent Sub-Systems
Power Level Partitioning
System Level Partitioning
Mechanical Partitioning
Partitioning Using Degating Circuits
Analog DFT and BIST
IO Mapping
Towards a Contactless Board Level Test
Built-In Self Test (BIST)
BIST Classification