Sie sind auf Seite 1von 17

University of San Carlos

Talamban, Cebu City


School of Engineering
Department of Electrical &Electronics Engineering

Synchronization and Metastability


EXPERIMENT No. 2
ECE413NL
Digital Electronics and Switching Theory 2
Submitted by:
Honoridez, Norch Van
Lobrigas, Jake
Maraya, Ashley Tatiana

Submitted to:
Engr. Judilyn Acas

Experiment Done on: 07/04,11/2016


Report Submitted on: 07/18/2016
Abstract

Table of Contents
Cover Page

Abstract
i
Table of Contents
ii
I.

Introduction
1

II.

Materials and Equipment


1

III.

Experimental Procedure
1
Data &Results

IV.
V.

Analysis (Discussion / Questions)


3

VI.

Conclusion
4

References
4
Appendices
4

I.

Introduction

II.

Materials and Equipment


Qt
Materials
y
1
2
10K 4 w
1
1
1

III.

SPDT Toggle Switch


74LS74 IC
74LS00 IC

Qty
1
1

Equipment
Digital Trainer
Digital Oscilloscope

Experimental Procedure
A. Proper operation of a D Flip-flop. Obtaining the
state equation of a D Flip-flop.
a. The circuit (refer Annex 1) was constructed.
b. SW1 was set so that A=0. It should always be the
starting state of the NAND latch. Before D flip-flop was
triggered, it was made sure that the input D was stable
and that the initial state Q(t) has been set previously
using the NP and NC (async PRESET and async CLEAR
respectively) lines. NP=NC=1 for a normal operation of
the D flip-flop since these lines are active low. D flip-flop
was triggered by activating and cycling the SW1 SPDT
switch (A=0 to A=1 and A=0). This action produced a
rectangular pulse without contact bounce on output A
of the NAND latch.
c. The table shown below was followed to have the circuit
cycled. The resulting Q(t+1) was filled after each
trigger. The datasheet of 74LS74 was utilized to make
sure the set-up and hold-times were not violated.
Table 1A. Behavioral Table for D Flip-flop
D
Q(t)
Q(t+1)
0
0
0
1
1
0
1
1

B. Improper way of loading a 1 to the D Flip-flop


a. The circuit (refer to Annex 2) was constructed. It was
attempted to load a 1 to the D flip-flop.
b. A=0 was set by having SW1 moved to position 3. D flipflop was cleared, where Q(t)=0, by D2=1, D3=1-0-1.
c. A 1 was sent to the D input by having SW1 moved
from position 3 to position 1. The action set A=1 at the
same time it gave a rising edge (PET) to the clock input
of the D flip-flop. The PET loaded the D input to the flipflop and made Q(t+1)=D. Refer to the discussions
regarding whether or not Q(t+1)=1 after it was
triggered.
d. Steps 2 and 3 were repeated several times to obtain
more data. Results were recorded (refer to Table 2).
C. Improper way of loading a 0 to the D flip-flop.
a. The circuit (refer to Annex 3) was constructed. It was
attempted to load a 0 to the D flip-flop.
b. SW1 was moved to position 1 by having A=1 and B=0
set. D flip-flop was set, where Q(t)=1, by D2=1-0-1,
D3=1.
c. A 0 was sent to the D input by having SW1 moved
from position 1 to position 3. The action set A=0 at the
same time it gave a rising edge (PET) to the clock input
of the D flip-flop through output B of the NAND latch.
The PET loaded the D input to the flip-flop and made
Q(t+1)=D. Refer to the discussions regarding whether
or not Q(t+1)=0 after it was triggered.
d. Steps 2 and 3 were repeated several times to obtain
more data. Results were recorded (refer to Table 3).
D.Synchronizers
a. A gate synchronizer took an external time command (or
signal) and produced an output that lasted for an even
number of clock pulses where it started with the first
pulse after the command (or signal) arrived and ended
the first pulse after the command (or signal) went away.
The output gate exactly a whole number of clock pulses
in length and approximately equal to input command

length (pulse width T >> system clock period). The


length of the synchronized output command was
approximately equal to the external command. It
precisely began with a system clock pulse and ended
with one. As the input signal arrived, the D input was
set. The output stayed high until the next pulse then
dropped.
b. A clock synchronizer was constructed by having the
gate synchronizer modified. This was done by adding a
gate. We can get a whole number of the system clock
pulse out. These were approximately equal to the
length of the input pulse but it was always a whole
number of the clock cycles that began and ended
synchronously with the system clock.
1. A gate synchronizer circuit (refer to Annex 4) was
constructed. The output signal, which is located at
the 5th pin of 74LS74 IC, and the system clock signal,
which is located at the 15th pin of 74LS76 IC, was
monitored using the two channel digital storage
oscilloscope (DSO).
2. SW1 was momentarily pushed to produce a ~1
second pulse from the 6th pin of MC14538 which was
the input to the 74LS74 flip-flop. The pulse was not
synchronized with the system clock of 74LS74.
3. The output signal, which is located at the 5 th pin of
74LS74 IC, was observed in relation to the clock
signal found at the 15th pin of the 74LS76 IC. The two
waveforms captured by the DSO was drawn (refer to
Figure 1).
4. Refer to the discussions on how the synchronizer
worked in line of the following questions: Was the
output synchronized with the system clock? Was the
pulse width of the input (~1 second pulse)
maintained at the output?
5. The clock synchronizers circuit (refer to Annex 5) was
constructed. The output signal, which is located at
the 1st pin of the 74LS02 IC), and the system clock
signal, which is located at the 15 th pin of the 74LS76

IC, was monitored using a two channel digital storage


oscilloscope (DSO).
6. SW1 was momentarily pushed to produce a ~1
second pulse from the 6th pin of MC14538 which was
the input to the 74LS74 flip-flop. The pulse was not
synchronized with the system clock of 74LS74.
7. The output signal, which is located at the 1 st pin of
74LS74 IC, was observed in relation to the clock
signal found at the 15th pin of the 74LS76 IC. The two
waveforms captured by the DSO was drawn (refer to
Figure 2).
8. Refer to the discussions on how the synchronizer
worked in line of the following questions: Was the
output synchronized with the system clock? Was the
pulse width of the input (~1 second pulse)
maintained at the output?

IV.

Analysis (Discussion / Questions)

Fig.1 Schematic Diagram Using D Flip flop


Fig.1 shows the schematic diagram of the circuit used for the
first part of the experiment, this shows that the flip-flop being
used is a D flip-flop. The purpose of this part of the experiment is
to be able to properly load bits within the D flip-flop and obtain its
state equation. Compared to the other flip-flops, the operation of
a D Flip-flop is much more simpler. This type of flip-flop has a
single input as an addition to the input for clock. This is useful
whenever a single data bit which can either 0 or 1 is to be stored.
Ideal Truth Table for D Flip-flop
Obtained Truth Table from the Experiment

D
0
0
1
1

Q(t)
0
1
0
1

Q(t+1)
0
0
1
1

Table 1. Obtained Truth Table for D flip-flop


Table 1 contains the ideal and obtained truth table of a D
flip-flop , it can be observed that the obtained truth table is
identical to the ideal truth table. This means that the connections
made were correct and data is being loaded properly to the flipflops. This table shows that if there is a 1 or logic HIGH on the D
input whenever a clock pulse is being applied, the flip-flops SETs
and thus, stores a data bit 1. Whenever, there is a 0 or logic LOW
on the D input when a clock pulse is being applied, the flip-flop
stores a logic low data bit or 0 and it also RESETs. The truth table
in Table 1 shows the summary of the operations of the positive
edge-triggered D flip-flop. From the schematic diagram, we can
say that it is a positive edge-triggered since the input of its clock
does not contain any bubble which denotes an inverter. Although
negative edge-triggered flip-flops do work in the same way except
that the negative edge-triggered flip-flops is being triggered at

the falling edge of the clock while the positive edge-triggered is


triggered at its rising edge.

Fig.2 Improper Way of Loading '1' to the D Flip-flop


Fig.2 shows the improper way of loading '1' to the D flip-flop,
it can be observed that compared to the previous schematic
diagram which was Fig.1 , that the outputs of the logic gates in
the Fig.2 are connected to both D and Clock meanwhile in Fig.1
only the clock is being connected to the D flip-flop. Following the
set of procedures provided by the manual, we have obtained the
following results:

Trial

Q(t)

Q(t+1)

2
0
3
0
4
0
5
0
Table 2. Truth Table Improper Way

0
0
0
0
of Loading '1'

It can be observed in Table2 that the present and next state


are always equal to 0 even after triggering. The next state doesn't
become logic HIGH or 1 because the circuit used is an improper
way of loading '1' to the D flip-flops.

Fig.3 Improper Way of Loading '0' to the D flip-flop


Fig.3 shows the improper way of loading '0' to the D flip-flop,
it can be observed that compared to the previous schematic
diagrams which was Fig.1 and Fig.2 , that the outputs of the logic
gates in the Fig.1 are connected to the clock and Fig.2 are
connected to both D and Clock meanwhile in Fig.3 only the clock
is being connected to the output of the Logic gate B (U7 B) while
D input is connected to logic gate A (U7 A). Following the set of
procedures provided by the manual, we have obtained the
following results:
Trial
Q(t)
Q(t+1)
1
1
1
2
1
1
3
1
1
4
1
1
5
1
1
Table 2 shows
that
the present
and nextWay
state
Table
2. Truth
Table Improper
of are always 1
even after triggering the circuit
this is
Loading
'0' because the circuit being
used is the improper way of loading '0' to the D flip-flop.

Fig.4 Gate Synchronizer


Obtained Waveform

Ideal Waveform

Table 3. Ideal Vs. Obtained Waveform for Gate Synchronizers


Table 3 shows the comparison of the obtained and ideal
waveform, from the obtained waveform, the yellow waveform is
the same as the (Blue) channel B for the obtained waveform while
the green waveform is the same as the (Pink) Channel C of the
ideal waveform. The yellow waveform of Channel A from the

ideal waveform figure shows the clock pulse. In the Gate


synchronizer, the output waveform is directly obtained from the D
Flip-flop, which means that the output generated is the same as
the ones being inputted by the outside world command which was
taken from the MC14538 IC in this case. The output isn't always
synchronized since the asynchronous signal changes only after
one clock cycle before an output is being generated.

Fig.5 Clock Synchronizer

Obtained Waveform

Ideal Waveform

Table 4. Ideal Vs. Obtained Waveform for Clock Synchronizers


Fig.5 shows the schematic diagram of the clock synchronizer,
for this, we add a NOR gate in the its Q' output of the D Flip-Flop
and the clock pulse obtained in the output with the same length
as the Pulse. The output obtained has an output in the Q (Blue,
Channel B )that is always high for the entire cycle while the
output of Q' connected to the NOR Flip-flop (Pink, Channel C)is
always in-synch with the clock pulse (yellow, Channel A). The
inverter at the clock is used to see the output after 1 second
pulse that is being generated by the MC14538 IC. From the
obtained waveform, it can be observed that 1 second pulse from
the asynchronous signal, the output will be synchronized with the
clock. From the low output, the switch is toggled and the D Flipflop and an input data of 1, the Q' becomes LOW and this gives a
HIGH output whenever the clock is also LOW. With the addition of
the inverted, the clock becomes HIGH and when being
interconnected with the Q', the clock becomes low which means
that the output becomes HIGH whenever the clock is HIGH, due to
the characteristic of a NOR gate with an input of Q' and inverted
clock, the output becomes low the clock is also low, which means
that the inverted clock becomes HIGH thus resulting in a LOW
output when inputted in the NOR gate.

V.

Conclusion

References
Leap Electronics CO., LTD. (n.d.). Leaptronix Manual. Fromhttps://groups.google.com/forum/#!
topic/ece413nnl/85t4nnN6zzE
USC DEEE., Laboratory Manual for ECE413NL. Digital Measurements Using Logic Analyzer.,
pp1-12.

Appendices

ANNEX 1

ANNEX 2

ANNEX 3

ANNEX 4 GATE SYNCHRONIZER CIRCUIT

ANNEX 5 CLOCK SYNCHRONIZER CIRCUIT