UNIT - III: 8051 MICROCONTROLLER

Hardware Architecture, pintouts Functional Building Blocks of Processor

Memory organization I/O ports and data transfer concepts Timing Diagram
Interrupts-Comparison to Programming concepts with 8085.
INTRODUCTION
A microcontroller is a device which integrates a number of the Components of a
microprocessor system onto a single microchip and optimized to interact with the
outside world through on board interfaces; ie., it is a little gadget that houses a
microprocessor, ROM (Rod only Memory), RAM (Random Access Memory), I/o
(Input Output functions) and various other specialized Circuits all in one package.
A microcontroller has a CPU (a microprocessor) in addition to a fixed amount of
RAM, ROM, I/o posts, and a timer are all embedded together on one chip.
On the other hand, a microprocessor is normally optimized to co-ordinate the flow
of information between separate memory and peripheral devices which are located
outside itself. Connections to a microprocessor includes address, Control and data
buses that allow it to select one of its peripherals and send to or retrace data from
it. Because a microcontrollers processor and peripherals are built on the same
silicon, the devices are self contained and rarely have any bus structures extending
outside their packages.
So a microcontroller incorporates onto the same microchip following:
The CPU Core,
Memory (both RAM and ROM)
Some Parallel digital I/o
Microcontrollers will also combine the other devices such as
(i) A timer module to allow the microcontroller to perform tasks for certain
time periods.
(ii) A Serial I/o port to allow data to flow between the microcontroller and
the other devices such as a PC or another microcontroller
(iii) An ADC to allow the microcontroller to accept analogue input data for
processing

8051 Microcontroller Architecture

The figure also shows the usual CPU components: program counter, ALU,
working registers, and clock circuits.
The 8051 architecture consists of these specific features:
Eight-bit CPU with registers A (the accumulator) and B
Sixteen-bit program counter (PC) and data pointer (DPTR)
Eight-bit program status word (PSW)
Eight-bit stack pointer (SP)
Internal ROM or EPROM of 4 KB in 8051.
Internal RAM of 128 bytes:
Four register banks, each containing eight registers
Sixteen bytes, which may be addressed at the bit level
Eighty bytes of general-purpose data memory
32 numbers of Input/Output pins arranged as four 8-bit Ports: PO-P3
Two 16-bit timer/counters: TO and TI
Full duplex serial data receiver/transmitter: SBUF
Control registers: TCON, TMOD, SCON, PCON, IP, and IE
Two external and three internal interrupt sources
Clock frequencies including body work 3.5 to 33MHz.
Bus: Basically Bus is a collection of wires which work as a communication
channel or medium for transfer of Data. These buses consist of 8, 16 or more
wires. Thus these can carry 8 bits, 16 bits simultaneously. Buses are of two types:
Address Bus
Data Bus
Address Bus: Microcontroller 8051 has a 16 bit address bus. It used to address
memory locations. It is used to transfer the address from CPU to Memory.
Data Bus: Microcontroller 8051 has 8 bits data bus. It is used to carry data.
Oscillator: As we know Microcontroller is a digital circuit device, therefore it
requires clock for its operation. For this purpose, Microcontroller 8051 has an on-

chip oscillator which works as a clock source for Central Processing Unit. As the
output pulses of oscillator are stable therefore it enables synchronized work of all
parts of 8051 Microcontroller.
Timing and Control Unit: It provides necessary timing and control signal for all
the operations. The signals associated with this unit are PSEN, EA, ALE and RST.
Arithmetic Logic Unit (ALU): It performs all arithmetic operations like addition,
subtraction, multiplication, division, integer multiplication, integer division, string
handling and logical operations like AND, OR, NOT and EX-OR.
A Register (Accumulator) : A register is an 8-bit general-purpose register used
for storing intermediate results obtained during operation.
B Register : It is an 8-bit register, always used with A register. Multiplication
and division can be performed only upon numbers stored in the A and B registers.
All other instructions in the program can use this register as a spare accumulator
(A).
Program Status Word (PSW) Register

PSW register is one of the most important SFRs. It contains several status bits that
reflect the current state of the CPU. Besides, this register contains Carry bit,
Auxiliary Carry, two register bank select bits, Overflow flag, parity bit and userdefinable status flag.
Stack Pointer (SP) Register: A value stored in the Stack Pointer points to the first
free stack address and permits stack availability. Stack pushes increment the value
in the Stack Pointer by 1. Likewise, stack pops decrement its value by 1
Data Pointer Register (DPTR) : DPTR register is not a true one because it
doesn't physically exist. It consists of two separate registers: DPH (Data Pointer
High) and (Data Pointer Low). For this reason it may be treated as a 16-bit register
or as two independent 8-bit registers. Their 16 bits are primarly used for external

memory addressing. Besides, the DPTR Register is usually used for storing data
and intermediate results.
Input/Output Port: As we know that Microcontroller is used in Embedded
systems to control the operation of machines. Therefore to connect it to other
machines, devices or peripherals we requires I/O interfacing ports
in Microcontroller. For this purpose Microcontroller 8051 has 4 input/output ports
to connect it to other peripherals.
Timers/Counters: Microcontroller 8051 has 2 16 bit timers and counters. The
counters are divided into 8 bit registers. The timers are used for measurement of
intervals , to determine pulse width etc.
Interrupts: There are five interrupt sources in 8051 Microcontroller. Two of them
are external interrupts, Two timer interrupts and One serial port interrupt.
Memory (ROM): Microcontroller 8051 has 4KB of internal Code memory which
is used to store the program of Microcontroller, is known as Program memory. It is
known
as
'ROM'(Read
Only
Memory).
Memory (RAM): Microcontroller has 128 bytes of data memory to store data or
operands temporarily known as 'RAM'(Random Access Memory).
The area of direct and indirect addressing is made up of the first 128 bytes of
internal memory of the microcontroller. This in turn is divided into three
segments differentiated by their use.
1. The Register Banks,
memory

2. Address area bit by bit

3.

Scratch Pad

The Register Banks: The registers R0 to R7 are grouped into 4 banks of

registers, RB0 to RB3, so that totally 32 bytes are assigned as 32 registers.
Bit Addressable area: 16 bytes are used as bit addressable RAM memory
locations.
Scratch Pad memory: Remaining 80 bytes are used as scratch Pad memory.

Above this 128 bytes RAM memory another 128 bytes memory location used for
maintain Special Function Registers (SFR)
8051 Architecture:

Pins 1-8: Port 1 Each of these pins can be configured as bidirectional input/output
line. The Port 0 is bit addressable. This port also used as time multiplexed low
order Address/Data (AD0 to AD7) lines for accessing external memory.
Pin 9: RST A logic one on this pin disables the microcontroller and clears the
contents of most registers. By applying logic zero to this pin, the program starts
execution from the beginning.
VPD may be used to supply power to the internal RAM during power failure or
power down modes.

Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general purpose
Input/Output line. Besides, all of them have alternative functions.
Pin 10: RXD Serial asynchronous communication input or Serial synchronous
communication output.
Pin 11: TXD Serial asynchronous communication output or Serial synchronous
communication clock output.
Pin 12: INT0 Interrupt 0 input.
Pin 13: INT1 Interrupt 1 input.
Pin 14: T0 Counter 0 clock input.

Pin 15: T1 Counter 1 clock input.

Pin 16: WR Write to external (additional) RAM.
Pin 17: RD Read from external RAM.
Pin 18, 19: X2, X1 Internal oscillator input and output. A quartz crystal which
specifies operating frequency is usually connected to these pins. The frequency
range is 3.5 to 12 MHz.
Pin 20: GND Ground.
Pin 21-28: Port 2 : When there is no external memory is used then these port pins
are configured as general inputs/outputs.
In case external memory is used, the higher address byte, i.e. addresses A8-A15
will appear on this port.
Even though memory with capacity of 64Kb is not used, which means that not all
eight port bits are used for its addressing, the rest of them are not available as
inputs/outputs.
Pin 29: PSEN: If external ROM is used for storing program then logic zero (0)
appears on it every time the microcontroller reads a byte from memory.
Pin 30: ALE: This signal is used to enable the hardware latch for de-multiplex the
Address/Data. from port 3. This pin also acts as an input pin for the programming
pulse during the programming of the internal EPROM.
Pin 31: EA: Logic 1 (connected to 5V) applied to this pin indicates that the
processor access 4KB of internal memory (0000H to 0FFFH).
If logic 0 (Grounded) is applied then the processor access 64 KB of external
memory.(0000H to FFFFH)
Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be
used as general inputs/outputs.
Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is driven
high (1) or as data output (Data Bus) when the ALE pin is driven low (0).
Pin 40: VCC +5V power supply.

Memory Organization
The 8051 has two types of memory and these are Program Memory and Data
Memory.
Program Memory (ROM) is used to permanently save the program being
executed, while Data Memory (RAM) is used for temporarily storing data
and intermediate results created and used during the operation of the
microcontroller.
All 8051 microcontrollers have a 16-bit addressing bus and are capable of
addressing 64 KB memory.
Program Memory
The 8051 microcontroller have a 4 Kbyte ROM embedded.
Even though such an amount of memory is not sufficient for writing most of the
programs, the additional ROM memory (64KB) should be connected.
To interface a memory chip to the microprocessor, the following pins should be
connected
Address Bus
Data Bus
Memory chip select
Read Control
Write Control (Only in the case of RAM)
P2.0 to P2.7: High order address lines (A7 to A15)
P0.0 to P0.7: Time multiplexed Low order address/data (AD0 to AD7)
The chip select of memory should connected address decoder.
P0.6 and P0.7 provides Write and Read control signals.
ALE should be connected to Address Latch for enabling the latch when address
signals are appear in the Address/Data lines.
PSEN should be connected to Read/Out Enable pin of external ROM memory.
The microcontroller handle external memory depends on the EA pin logic state:
EA=0 In this case, the microcontroller completely ignores internal program
memory (4 KB) and executes only the program stored in external memory (64KB).
The 8051 access the external memory location starts from 0000H to FFFFH.

EA=1 In this case, the microcontroller executes first the program from built-in
ROM (4 KB), then the program stored in external memory.
The 8051 first access the internal ROM by start from 0000H to 0FFFH and then
access the external memory from 1000H to FFFFH

.
In both cases, P0 and P2 are not available for use since being used for data and
address transmission. Besides, the ALE and PSEN pins are also used.
Data Memory
The External Data Memory is used for storing the data. The maximum capacity of
RAM is 64 KB.
Besides, RAM memory built in the 8051 family includes many registers such as
hardware counters and timers, input/output ports, serial data buffers etc.

However, the first 256 memory locations (addresses 0-FFh) are the heart of
memory common to all the models belonging to the 8051 family.
Locations available to the user occupy memory space with addresses 0-7Fh, i.e.
first 128 registers. This part of RAM is divided in several blocks.
The first block consists of 4 banks each including 8 registers denoted by R0-R7.
The next memory block (address 20h-2Fh) is bit- addressable, which means that
each bit has its own address (0-7Fh). Since there are 16 such registers, this block
contains in total of 128 bits with separate addresses (address of bit 0 of the 20h
byte is 0, while address of bit 7 of the 2Fh byte is 7Fh).
The third group of registers occupies addresses 2Fh-7Fh, i.e. 80 locations, and does
not have any special functions or features.

Interfacing External Memory

If external program/data memory are to be interfaced, they are interfaced in the following
way.

Figure: Circuit Diagram for Interfacing of External Memory

Figure: Combined external program and data memory interface

External program memory is fetched if either of the following two conditions are satisfied.
1.

(Enable Address) is low. The microcontroller by default starts searching for

program from external program memory.

2. PC is higher than FFFH for 8051 or 1FFFH for 8052.

tells the outside world whether the external memory fetched is program memory or data
memory. is user configurable.
is processor controlled.
Special Function Registers (SFRs)
All the resources in the 8051 microcontroller can be accessed through special
function registers available in Internal data memory
There are 21 number of registers are available in 8051 microcontroller. They are
1.
ACC
Accumulator*
8-bit Register
2.
B
B Register*
8-bit Register
3.
PSW
Program Status Word*8-bit Register
4.
SP
Stack Pointer
8-bit Register
5.
DPTR (Low)
Data Pointer Low
8-bit Register
6.
DPTR (High)
Data Pointer High
8-bit Register
7.
P0
Port 0*
8-bit Register
8.
P1
Port 1*
8-bit Register
9.
P2
Port 2*
8-bit Register
10.
P3
Port 3*
8-bit Register
11.
IP
Interrupt Priority*
8-bit Register
12.
IE
Interrupt Enable*
8-bit Register
13.
TMOD
Timer/Counter Mode 8-bit Register
14.
TCON
Timer/Counter Control*
8-bit Register
15.
TH0
(Timer/Counter) 0 High
8-bit Register
16.
TL0
(Timer/Counter) 0 Low
8-bit Register
17.
TH1
(Timer/Counter) 1 High
8-bit Register
18.
TL1
(Timer/Counter) 1 Low
8-bit Register
19.
SCON
Serial Control*
8-bit Register
20.
SBUF
Serial Data Buffer
8-bit Register
21.
PCON
Power Control
8-bit Register

* These bytes are bit addressable as well

Each of these registers as well as each bit they include, has its name, address in the
scope of RAM and precisely defined purpose such as timer control, interrupt
control, serial communication control etc.
Even though there are 128 memory locations intended to be occupied by them,
8051 microcontrollers has only 21 such registers.

A Register (Accumulator) : A register is an 8-bit general-purpose register used

for storing intermediate results obtained during operation.
Prior to executing an instruction upon any number or operand it is necessary to
store it in the accumulator first.
All results obtained from arithmetical operations performed by the ALU are stored
in the accumulator. Data to be moved from one register to another must go through
the accumulator.
B Register : It is an 8-bit register, always used with A register. Multiplication
and division can be performed only upon numbers stored in the A and B registers.
All other instructions in the program can use this register as a spare accumulator
(A).

Program Status Word (PSW) Register

PSW register is one of the most important SFRs. It contains several status bits that
reflect the current state of the CPU. Besides, this register contains Carry bit,
Auxiliary Carry, two register bank select bits, Overflow flag, parity bit and userdefinable status flag.
P - Parity bit. If a number stored in the accumulator is even then this bit will be
automatically set (1), otherwise it will be cleared (0). It is mainly used during data
transmit and receive via serial communication.
Bit 1. This bit is intended to be used in the future versions of microcontrollers.
OV - Overflow occurs when the result of an arithmetical operation is larger than
255 and cannot be stored in one register. Overflow condition causes the OV bit to
be set (1). Otherwise, it will be cleared (0).

RS0, RS1 - Register bank select bits. These two bits are used to select one of four
register banks of RAM. By setting and clearing these bits, registers R0-R7 are
stored in one of four banks of RAM.
RS1 RS0 Space in RAM
0

Bank0 00h-07h

Bank1 08h-0Fh

Bank2 10h-17h

Bank3 18h-1Fh

F0 - Flag 0. This is a general-purpose bit available for use.

AC - Auxiliary Carry Flag is used for BCD operations only.

CY - Carry Flag is the (ninth) auxiliary bit used for all arithmetical operations and
shift instructions.
Stack Pointer (SP) Register
A value stored in the Stack Pointer points to the first free stack address and permits
stack availability. Stack pushes increment the value in the Stack Pointer by 1.
Likewise, stack pops decrement its value by 1.
Data Pointer Register (DPTR)
DPTR register is not a true one because it doesn't physically exist. It consists of
two separate registers: DPH (Data Pointer High) and (Data Pointer Low).
For this reason it may be treated as a 16-bit register or as two independent 8-bit
registers. Their 16 bits are primarily used for external memory addressing.
Besides, the DPTR Register is usually used for storing data and intermediate
results.
R Registers (R0-R7)
This is a common name for 8 general-purpose registers (R0, R1, R2 ...R7). They
occupy 4 banks within RAM. Similar to the accumulator, they are used for
temporary storing variables and intermediate results during operation.
Which one of these banks is to be active depends on two bits (RS1, RS0) of the
PSW Register. Active bank is a bank the registers of which are currently used.
P0, P1, P2, P3 - Input/Output Registers
There are four bidirectional Input /Output ports of 8-bit each. These 32 pins are bit
addressable and multifunctional pins for programming the resources.
P0 and P2 can be used as I/O ports or address lines for external memory.
P1 can be used as I/O ports.
P3 can be used as I/O port and used as important alternate functions like Serial
input, Serial Output, External interrupt lines, External interrupt lines, External
memory read and write strobe lines.

TMOD Register (Timer Mode)

The TMOD register selects the operational mode of the timers T0 and T1. The low
4 bits (bit0 - bit3) refer to the timer 0, while the high 4 bits (bit4 - bit7) refer to the
timer 1. There are 4 operational modes and each of them is described herein.

Timer Control (TCON) Register

TCON register is also one of the registers whose bits are directly in control of
timer
operation.
Only 4 bits of this register are used for this purpose, while rest of them is used for
interrupt control.

Timer 0 and Timer 1 register: The 8051 has two numbers of 16-bit timers. It is
available as four 8-bit registers like TH0, TL0, TH0 and TL1. These registers are
used to load the values during timer and counter functions. Also offers four modes
of operations like mode0, mode1, mode2 and mode3.
Serial Buffer Register (SBUF) : This register is used for serial data
communication. It holds the data to be transmitted and received. For this purpose,
SBUF is interconnected to two 8-bit shift registers.
Control and Status Registers: The Special function registers like Interrupt
Priority (IP), Interrupt Enable (IE), Power Control Register (PCON), Serial Control
(SCON) that are used for controlling the internal resources or to see the status of
these resources.

INPUT/OUTPUT PORTS (I/O PORTS)

The 8051 microcontrollers have 4 numbers of I/O ports each comprising 8 bits
which can be configured as inputs or outputs. Accordingly, in total of 32
input/output pins enabling the microcontroller to be connected to peripheral
devices are available for use.
Pin configuration, i.e. whether it is to be configured as an input (1) or an output
(0), depends on its logic state.
In order to configure a microcontroller pin as an output, it is necessary to apply a
logic zero (0) to appropriate I/O port bit. In this case, voltage level on appropriate
pin will be 0V.
Similarly, in order to configure a microcontroller pin as an input, it is necessary to
apply a logic one (1) to appropriate port. In this case, voltage level on appropriate
pin will be 5V.
Output pin
A logic zero (0) is applied to a bit of the P register. The output FE transistor is
turned on, thus connecting the appropriate pin to ground.
Input pin
A logic one (1) is applied to a bit of the P register. The output FE transistor is
turned off and the appropriate pin remains connected to the power supply voltage
over a pull-up resistor of high resistance.
I/O Port Configuration
Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it
floats
(tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.

Port 0
The P0 port is characterized by two functions. If external memory is used then the
lower address byte (addresses A0-A7) is applied on it. Otherwise, all bits of this
port are configured as inputs/outputs.

Port-0 Pin Structure

Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data
interfacing for accessing external memory.
When control is '1', the port is used for address/data interfacing. When the control is '0', the
port can be used as a normal bidirectional I/O port.
Let us assume that control is '0'. When the port is used as an input port, '1' is written to the
latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats.
This high impedance pin can be pulled up or low by an external source. When the port is used
as an output port, a '1' written to the latch again turns 'off' both the output MOSFETs and
causes the output pin to float.
An external pull-up is required to output a '1'. But when '0' is written to the latch, the pin is
pulled down by the lower MOSFET. Hence the output becomes zero.
When the control is '1', address/data bus controls the output driver MOSFETs. If the

address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'.
The output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower
transistor is 'off'. Hence the output is '1'. Hence for normal address/data interfacing (for
external memory access) no pull-up resistors are required.
Port-0 latch is written to with 1's when used for external memory access.
Port 1
P1 is a true I/O port, because it doesn't have any alternative functions as is the case
with P0, but can be configured as general I/O only. It has a pull-up resistor built-in
and is completely compatible with TTL circuits.

Port-1 does not have any alternate function i.e. it is dedicated only for I/O
interfacing. When used as output port, the pin is pulled up or down through
internal pull-up.
To use port-1 as input port, '1' has to be written to the latch. In this input mode
when '1' is written to the pin by the external device then it read fine.
But when '0' is written to the pin by the external device then the external source
must sink current due to internal pull-up. If the external device is not able to sink
the current the pin voltage may rise, leading to a possible wrong reading.
Port 2
Port-2 is used for higher external address byte or a normal input/output port. The
I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are

used for external memory access. Here again due to internal pull-up there is limited
current driving capability.

Port 3
All port pins can be used as general I/O, but they also have an alternative function.
In order to use these alternative functions, a logic one (1) must be applied to
appropriate bit of the P3 register. In terms of hardware, this port is similar to P0,
with the difference that its pins have a pull-up resistor built-in.
Each pin of Port-3 can be individually programmed for I/O operation or for alternate
function. The alternate function can be activated only if the corresponding latch has been
written to '1'. To use the port as input port, '1' should be written to the latch. This port also has
internal pull-up and limited current driving capability.
Alternate functions of Port-3 pins are P3.0 RxD
P3.1 TxD
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7

T0
T1

Note:
1. Port 1, 2, 3 each can drive 4 LS TTL inputs.
2. Port-0 can drive 8 LS TTL inputs in address /data mode. For digital output port, it
needs external pull-up resistors.
3. Ports-1,2and 3 pins can also be driven by open-collector or open-drain outputs.
4. Each Port 3 bit can be configured either as a normal I/O or as a special function bit.

TIMERS / COUNTERS
Timer Mode control (TMOD) Special Function Register:
TMOD register is not bit addressable.
TMOD
Address: 89 H

Timer/ Counter control logic:

Figure: Timer/Counter Control Logic

TCON is bit addressable. The address of TCON is 88H. It is partly related to Timer and
partly to interrupt.

Figure: TCON Register

The various bits of TCON are as follows.
TF1 : Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when
processor vectors to execute ISR located at address 001BH.
TR1 : Timer1 run control bit. Set to 1 to start the timer / counter.
TF0 : Timer0 overflow flag. (Similar to TF1)
TR0 : Timer0 run control bit.
IE1 : Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is
cleared when interrupt is processed.
IE0 : Interrupt0 edge flag. (Similar to IE1)
IT1 : Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level
triggered external interrupt.
IT0 : Interrupt0 type control bit. (Similar to IT1)
As mentioned earlier, Timers can operate in four different modes. They are as follows

Timer Mode-0: (13-bit UP counter)

In this mode, the timer is used as a 13-bit UP counter as follows.

Figure: Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count. Upper 3 bits of TLX
are ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt
is generated.
The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the
counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the
counter is controlled by
input. This mode is useful to measure the width of a given pulse
fed to
input.
Timer Mode-1: (16-bit mode)
This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit mode.

Figure: Operation of Timer in Mode 1

This is a 8 bit counter/timer operation. Counting is performed in TLX while THX stores a
constant value. In this mode when the timer overflows i.e. TLX becomes FFH, it is fed with
the value stored in THX. For example if we load THX with 50H then the timer in mode 2 will
count from 50H to FFH. After that 50H is again reloaded. This mode is useful in applications
like fixed time sampling.

Figure: Operation of Timer in Mode 2

Timer Mode-3: Split Mode (Two 8-bit counters)
Mode 3 configures timer 0 so that registers TL0 and TH0 operate as separate 8-bit timers. In
other words, the 16-bit timer consisting of two registers TH0 and TL0 is split into two
independent 8-bit timers. This mode is provided for applications requiring an additional 8-bit
timer or counter. The TL0 timer turns into timer 0, while the TH0 timer turns into timer 1.
Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0. Timer0 in
mode-3 establishes TL0 and TH0 as two separate counters.

Figure: Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0
and TF0 are available to Timer-0 lower 8 bits (TL0).

8051 Addressing Mods

8051 instruction set supports fix types of addressing modes as listed below.
1.
Register Addressing
2.
Direct Addressing
3.
Register indirect Addressing
4.
Immediate Addressing
5.
Based induced indirect Addressing

Register Addressing:
It permits access to eight Registers (R0 R7) of the register bank. Other Registers
used are A, B, DPTR
eg: MOV A, R7
The name of the Register will be specified in the instruction itself. So it is called
as Register addressing mode.
Direct Addressing:
In this mode of addressing, the operands are specified using the 8-bit address field,
in instruction format. Only internal data RAM and SFRS can be directly
addressed.
eg: MOV A, 4EH
The content which is present in the memory location 4E is moved to Register A.
Indirect Addressing:
In this mode of addressing, the 8-bit address of the operand is stored in a register
specified in the instruction. The Registers R0 and R1 of the selected bank of
registers or stack pointer can be used as address Registers for storing the 8-bit
address. The address register for 16-bit address can only be the data pointer
(DPTR).
eg:1 MOV A, @ R0
If R0 contains 5FH, and address location 5FH has 43H then after this instruction
43H will be stored in Accumulates
eg: 2 MOVX A, @ EPTR
Immediate Addressing
In this mode of addressing, an immediate data ie, a constant specified in the
instruction, after the Op-code byte.
eg: ADD A, # OFH
This instruction adds OFH with the content of A and the result will be stored in the
Accumulator (A)itself.
Based Induced indirect Addressing:
Only program memory can be accessed using this addressing mode. The DPTR or
PC register may act as the base Register And register A acts as index Register.

The summation of contents of the base register and index Register determines the
Operand address.
eg: MOVC A, A+ DPTR
If A = 02H, and DPTR = OE7EH and OE80H + 56H then after this instruction
56H will be stored in Accumulator (A)
Instruction Set of 8051:
Instruction sets of 8051 can be classified into four different categories. They are
1)
Data Transfer Instructions
2)
Arithmetic Instructions
3)
Logical Instructions
4)
Control Transfer instructions
8051 I/O Ports structure:
The 8051 has 32 I/o pins configured as four eight bit parallel posts (P 0, P1, P2 and
P3) All four posts are bidirectional i.e., each pin will be configured as input or
output or both. All post pins are multiplexed except the pins of post 1. Each post
consists of a latch, an output drives and an input buffer.
Post 0 (Pins 32 39):
Post 0 pins can be used as I/o pins. The output drives and input buffers of post 0
are used to access external memory. Post 0 outputs the low order bytes of the
external memory address, time multiplexed with data being written or read. Thus
post 0 can be used as multiplexed address/data bus.
Post 1 (Pins 1 8)
Post 1 Pins can only be used as I/o pins.
Post 2 (Pins 21 28)
The output drives of post 2 are used to access external memory. Post 2 outputs the
higher order byte of the external memory address when the address is 16 bits wide.
Otherwise, post 2 is used as an I/o post.

Post 3 (Pins 10 17)

All post pins of post 3 are multi functional. Therefore each pin, of post 3 can be
programmed to use as I/o or as one of the alternate function. They have special
functions as shown below including two external interrupts, two counter inputs,
two special data lines and two timing control strobes.
Serial Interface:
The RXD pin is used to receive the input serially and the TXD pin is used to
transmit the data serially. The serial communication is full duplex, meaning that
the 8051 can receive and transmit at the same time. The receiving unit is buffered
as well. Thus the reception of the second byte or the frame data can start even
before the first byte is received by the CPU.
Mode 0:
In this mode, the 8051 receives and transmits through the RXD pin. The TXD
outputs the shift clock. 8-bits of data are received or transmitted. While
transmitting the LSB of the byte is sent out first similarly, while receiving the LSB
is received first. The band rate in this mode is 1/12th of the oscillator frequency.
Once all the 8-bits of data byte are transmitted, the transmit interrupt (71) flag is
set and an interrupt is generated.
Similarly after receiving all 8-bits, the receiving interrupt (R1) flag is set and an
interrupt is generated.
Mode 1:
In this mode, the 8051 generates and transmits 10 bits of information through T XD
and receives 10 bits of information through R XD.
The first bit is the start bit followed by the 8-bits of data (LSB first) and then a stop
bit (high). The stop bit is loaded into a bit called RB8 in the SCON register. The
stop bit and start bit are automatically added by the 8051 CPU through hardware
while transmitting the data. The band rate is variable and is given by
f band

2SMOD X

Oscillator frequency

12d x [256d (7H1)]

32d
Mode 2:

In this mode, 11 bits are transmitted or received. This 11 bit frame is classified as
1 bit for start. 8 bits for data, 1 bit can be programmed and 1 bit for stop. The 9 th
data bit is programmable. This 9th bit is the 7B8 bit for transmission and RB8 bit
for reception in the SCON register
The band rate is programmable either 1/22th
f band 2

2 SMOD x
64d

or 1/64th of the oscillator frequency.

Oscillator frequency

Mode 3:
This mode is same as the mode 2 except for the band rate. Here the band rate is
variable and is same as mode 1.
SCON : (Serial Control Register)
The SCON Register is an 8 - bit Register used to program the start bit, stop bit and
data bits of data framing, among other things.
The following describes various bits of the SCON register.
SMO
SMO , SM1
SM2
REN
TB8
RB8
T1
R1

SM1

SM2
-

REN

TB8

RB8

T1

R1

Serial Post mode specifier

used for Microprocessor Communication
Set/cleared by software to enable/disable reception
Not widely used
Not widely used
Transmit Interrupt flag
Receive Interrupt flag

INTERRUPTS
An interrupt is a special feature which allows the 8051 to provide the hope of
"multitasking". An interrupt is triggered whenever a corresponding event occurs.

When the event occurs, the 8051 temporarily puts "on hold" the normal execution
of the program and executes a special section of code referred to as an interrupt
handler.
The interrupt handler performs whatever special functions are required to handle
the event and then returns control to the 8051 at which point program execution
continues as if it had never been interrupted.

8051 provides 5 vectored interrupts. They are

1.
2. TF0
3.
4. TF1
5. RI/TI
Out of these,
and
are external interrupts whereas Timer and Serial port
interrupts are generated internally.
The external interrupts could be negative edge triggered or low level triggered. All
these interrupt, when activated, set the corresponding interrupt flags.
Except for serial interrupt, the interrupt flags are cleared when the processor branches
to the Interrupt Service Routine (ISR).
The external interrupt flags are cleared on branching to Interrupt Service Routine
(ISR), provided the interrupt is negative edge triggered.
For low level triggered external interrupt as well as for serial interrupt, the
corresponding flags have to be cleared by software by the programmer.

The schematic representation of the interrupts is as follows Interrupt

Vector Location

Figure: 8051 Interrupt Details

Interrupt Enable register (IE): Address: A8H

EX0
ET0
EX1

interrupt (External) enable bit

Timer-0 interrupt enable bit
interrupt (External) enable bit

ET1

Timer-1 interrupt enable bit

ES

Serial port interrupt enable bit

ET2

Timer-2 interrupt enable bit

EA
Setting 1'

Enable/Disable all
Enable the corresponding interrupt

Setting 0'

Disable the corresponding interrupt

Each interrupt source can be programmed to have one of the two priority levels by setting
(high priority) or clearing (low priority) a bit in the IP (Interrupt Priority) Register.
A low priority interrupt can itself be interrupted by a high priority interrupt, but not by
another low priority interrupt.
If two interrupts of different priority levels are received simultaneously, the request of higher
priority level is served. If the requests of the same priority level are received simultaneously,
an internal polling sequence determines which request is to be serviced.

Thus, within each priority level, there is a second priority level determined by the polling
sequence, as follows.
Interrupt Source
Vector
Priority within level
location
External Hardware Interrupt (INT0)
0003H
Highest
Timer 0 Interrupt (TF0)
000BH
External Hardware Interrupt (INT1)
00013H
Timer 1 Interrupt (TF1)
001BH
Serial communication Interrupt (RI
0023H
Lowest
and TI)

Interrupt Priority register (IP)

0'

low priority

1'

high priority

Interrupt handling:
When an interrupt comes and the program is directed to the interrupt vector address, the

Program Counter (PC) value of the interrupted program is stored (pushed) on the stack.
The required Interrupt Service Routine (ISR) is executed. At the end of the ISR, the
instruction RETI returns the value of the PC from the stack and the originally interrupted
program is resumed.
The schematic diagram of the detection and processing of interrupts is given as follows.
Instruction Cycles

Figure: Interrupt Handling in 8051

Reset is a non-maskable interrupt. A reset is accomplished by holding the RST pin high for at
least two machine cycles. On resetting the program starts from 0000H and some flags are
modified.
Operand types
The 8051 supports data types likes bytes, short integers and bits. Bytes and short
integers are 8 bit variables.
Addressing Modes:
There are a number of addressing modes available to the 8051 instruction set,
as follows:
1.Immediate Addressing

2. Register Addressing

3. Direct Addressing

4. Register-Indirect Addressing

5. Base plus Index register indirect Addressing

Immediate Addressing
Immediate addressing simply means that the operand (which immediately follows
the instruction op. code) is the data value to be used. For example the instruction:
MOV A, #dada (8-bit)
Example:
MOV A, #99H
Accumulator
Number 99H
Moves the value 99 into the accumulator (note this is 99 Hexa-decimal since we
used 99H). The # symbol tells the assembler that the immediate addressing mode is
to be used.
Register Addressing
One of the eight general-registers, R0 to R7, can be specified as the instruction
operand. The assembly language documentation refers to a register generically as
Rn. An example instruction using register addressing is :
ADD A, Rn ; Add contents of register Rn to accumulator.
ADD A, R5 ; Adds register R5 to A (accumulator)
A (A+R5)
Example:
Accumulator
R5

Here the contents of R5 are added to the accumulator. One advantage of

register addressing is that the instructions tend to be short, single byte
instructions.
Direct Addressing
Direct addressing means that the data value is obtained directly from the memory
location specified in the operand. For example consider the instruction:
MOV A, Direct : The byte variable indicated by Direct5 (which is an address

location) is copied into register A.

Example:
MOV A, 47h : Copy the content in the direct address 47H to accumulator.

Internal RAM
Accumulator

47h
46h

The instruction reads the data from Internal RAM address 47h and stores this in
the accumulator. Direct addressing can be used to access Internal RAM,
including the SFR registers.
Indirect Addressing
Indirect addressing provides a powerful addressing capability, which needs to be
appreciated. An example instruction, which uses indirect addressing, is as
follows:
MOV A, @Ri
MOV A, @R0: The contents of register R0 give the address of the location from
where the operand is picked up.
Internal RAM
Accumulator

55h

R0

54h
53h

54h

Note: The @ symbol indicated that the indirect addressing mode is used. R0
contains a value, for example 54h, which is to be used as the address of the internal
RAM location, which contains the operand data. Indirect addressing refers to
Internal RAM only and cannot be used to refer to SFR registers.
Note: Only R0 or R1 can be used as register data pointers for indirect addressing
when using MOV instructions.

Base plus Index register indirect Addressing

This is an indirect instruction used to access the program memory. In this
instruction the operand on which the operation is to be performed, is not specified
directly.
The summation of contents of base register and index register determines the
operand address.
Example:
MOVC A, @A+DPTR
MOVC is a move instruction, which moves data from the external code memory
space. The address operand in this example is formed by adding the content of
the DPTR register to the accumulator value. Here the DPTR value is referred to
as the base address and the accumulator value us referred to as the index
address.