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Programmable Logic

Regular logic
Programmable Logic Arrays
Multiplexers/Decoders

Random Logic
Full Custom Design

ROMs

Field Programmable Gate Arrays


Xilinx Vertex

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 1

Regular Logic
Structured Design

Programmable Logic Arrays (PLAs)


Pre-fabricated building block of many AND/OR gates
Actually NOR or NAND
Personalized" by making or breaking connections among gates
Programmable array block diagram for sum of products form

inputs

AND
array

product
terms

OR
array

outputs

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 2

Enabling Concept
Shared product terms among outputs
example:

F0
F1
F2
F3

=
=
=
=

A +
A C'
B' C'
B' C

B' C'
+ AB
+ AB
+ A
input side:

personality matrix
product
term
AB
B'C
AC'
B'C'
A

inputs
A
B
1
1

0
1

0
1

1
0
0

outputs
F0 F1
0
1
0
0
0
1
1
0
1
0

1 = uncomplemented in term
0 = complemented in term
= does not participate
F2
1
0
0
1
0

F3
0
1
0
0
1

output side:
1 = term connected to output
0 = no connection to output
reuse of terms

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 3

Before Programming
All possible connections available before "programming"
In reality, all AND and OR gates are NANDs

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 4

After Programming
Unwanted connections are "blown"
Fuse (normally connected, break unwanted ones)
Anti-fuse (normally disconnected, make wanted connections)
A

AB
B'C
AC'
B'C'
A

F0

F1

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 5

F2

F3

Alternate Representation for High Fan-in


Structures
Short-hand notation--don't have to draw all the wires
Signifies a connection is present and perpendicular signal is
an input to gate
notation for implementing
F0 = A B + A' B'
F1 = C D' + C' D
A B C D
AB
A'B'
CD'
C'D

AB+A'B'
CD'+C'D
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 6

Programmable Logic Array Example


full decoder as for memory address

Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C

bits stored in memory

A B C

A'B'C'

F3 = A' B' C'


F4 = A' + B' + C'

A'B'C
A'BC'

F5 = A xor B xor C
F6 = (A xnor B xnor C)
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F1
0
0
0
0
0
0
0
1

F2
0
1
1
1
1
1
1
1

F3
1
0
0
0
0
0
0
0

F4
1
1
1
1
1
1
1
0

F5
0
1
1
0
1
0
0
1

A'BC
AB'C'

F6
0
1
1
0
1
0
0
1

AB'C
ABC'
ABC

F1 F2 F3 F4 F5
F6

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 7

PLA Design Example


BCD to Gray code converter
A
0
0
0
0
0
0
0
0
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
1

C
0
0
1
1
0
0
1
1
0
0
1

D
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1

X
0
0
0
0
1
1
0
0
0
0

Y
0
0
1
1
1
1
1
1
0
0

Z
0
1
1
0
0
0
0
1
1
0

minimized functions:
W=A+BD+BC
X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'

C 0

C 0

K-map for W

K-map for X

C 1

C 0

K-map for Y

K-map for Z

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 8

PLA Design Example (contd)


Code converter: programmed PLA
A B

minimized functions:

C D

W=A+BD+BC
X = B C'
Y=B+C
Z = A'B'C'D + B C D + A D' + B' C D'

A
BD
BC
BC'

not a particularly good


candidate for PLA
implementation since no terms
are shared among outputs

B
C
A'B'C'D

however, much more compact


and regular implementation
when compared with discrete
AND and OR gates

BCD
AD'
BCD'
W

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 9

PLA Design Example


BCD to Gray code converter
A
0
0
0
0
0
0
0
0
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
1

C
0
0
1
1
0
0
1
1
0
0
1

D
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1

minimized functions:
W=
X=
Y=
Z=

X
0
0
0
0
1
1
0
0
0
0

Y
0
0
1
1
1
1
1
1
0
0

Z
0
1
1
0
0
0
0
1
1
0

C 0

C 0

K-map for W

K-map for X

C 1

C 0

K-map for Y

K-map for Z

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 10

PLA Design Example #1


BCD to Gray code converter
A
0
0
0
0
0
0
0
0
1
1
1
1

B
0
0
0
0
1
1
1
1
0
0
0
1

C
0
0
1
1
0
0
1
1
0
0
1

D
0
1
0
1
0
1
0
1
0
1

W
0
0
0
0
0
1
1
1
1
1

X
0
0
0
0
1
1
0
0
0
0

Y
0
0
1
1
1
1
1
1
0
0

Z
0
1
1
0
0
0
0
1
1
0

C 0

C 0

BC

K-map for X
A

C 1

C 0

minimized functions:

K-map for W

W=
X=
Y=
Z=

K-map for Y

K-map for Z

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 11

PLA Design Example #2


A B

Magnitude comparator
A

C D
A'B'C'D'

C 0

C 1

K-map for EQ

K-map for NE

A'BC'D
ABCD

AB'CD'
AC'
A'C
B'D
BD'

A'B'D
B'CD

C 1

C 0

ABC

BC'D'

K-map for LT

K-map for GT
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 12

EQ NE LT GT

Multiplexer/Demultiplexer: Making
Connections
Direct point-to-point connections between gates
Multiplexer: route one of many inputs to a single output
Demultiplexer: route single input to one of many outputs
control

multiplexer

control

demultiplexer

4x4 switch

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 13

Multiplexers/Selectors
Multiplexers/Selectors: general concept
2n data inputs, n control inputs (called "selects"), 1 output
Used to connect 2n points to a single point
Control signal pattern forms binary index of input connected
to output
I
I
A
Z
A
0
1

Z = A' I 0 + A I 1

Z
I0
I1

functional form
logical form
two alternative forms
for a 2:1 Mux truth table
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 14

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
1
0
0
1
1
1

Multiplexers/Selectors (cont'd)
2:1 mux:

Z = A' I0 + A I1

4:1 mux:

Z = A' B' I0 + A' B I1 + A B' I2 + A B I3

8:1 mux:

Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +


AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7

In general, Z =

2 n -1

k=0

(mkIk)

in minterm shorthand form for a 2n:1 Mux

I0
I1

2:1
mux

I0
I1
I2
I3

4:1
mux

I0
I1
I2
I3
I4
I5
I6
I7

A B

8:1
mux

A B C

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 15

Cascading Multiplexers
Large multiplexers implemented by cascading smaller ones
I0
I1
I2
I3
I4
I5
I6
I7

8:1
mux

4:1
mux

2:1
mux

alternative
implementation
Z

4:1
mux

B C

control signals B and C simultaneously choose


one of I0, I1, I2, I3 and one of I4, I5, I6, I7
control signal A chooses which of the
upper or lower mux's output to gate to Z

I0
I1

2:1
mux

I2
I3

2:1
mux

I4
I5

2:1
mux

I6
I7

2:1
mux
C

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 16

8:1
mux

4:1
mux

A B

Multiplexers as Lookup Tables (LUTs)


2n:1 multiplexer implements any function of n variables
With the variables used as control inputs and
Data inputs tied to 0 or 1
In essence, a lookup table

Example:
F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'(C') + A'B(C') + AB'(0) + AB(1)

1
0
1
0
0
0
1
1

0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0
A

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 17

Multiplexers as LUTs (contd)


2n-1:1 mux can implement any function of n variables
With n-1 variables used as control inputs and
Data inputs tied to the last variable or its complement

Example:

F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'(C') + A'B(C') + AB'(0) + AB(1)
1
0
1
0
0
0
1
1

0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0
A

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F
1
0
1
0
0
0
1
1

C'
C'
0
1

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 18

C'
C'
0
1

0
1 4:1 MUX
2
3
S1 S0
A

Multiplexers as LUTs (contd)


Generalization
n-1 mux control
variables

I0

I1

. . . In-1 In

In

In'

single mux data


variable

F
four possible
configurations
of truth table rows
can be expressed
as a function of I n

Example: F(A,B,C,D) implemented by an 8:1 MUX


A

choose A,B,C as control variables


D

multiplexer implementation

1
D
0
1
D
D
D
D

0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 19

Announcements
We took everyone on the wait list into the class
Result is that Tu labs are very crowded!
Th night lab is very light -- think of switching to get more TA face
time!
Send email to pokai@berkeley.edu to request a lab change

First HW due Friday at 2 PM just before Lab Lecture


CS 150 hand-in box outside and just to the right of 125 Cory doors

Second HW on class web site


Use ucb.class.cs150 newsgroup for lab, hw, course questions!

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 20

Demultiplexers/Decoders
Decoders/demultiplexers: general concept
Single data input, n control inputs, 2n outputs
Control inputs (called selects (S)) represent binary index of
output to which the input is connected
Data input usually called enable (G)
1:2 Decoder:
O0 = G S
O1 = G S
O0
O1
O2
O3

2:4 Decoder:
= G S1
= G S1
= G S1
= G S1

S0
S0
S0
S0

O0
O1
O2
O3
O4
O5
O6
O7

=
=
=
=
=
=
=
=

3:8 Decoder:
G S2 S1 S0
G S2 S1 S0
G S2 S1 S0
G S2 S1 S0
G S2 S1 S0
G S2 S1 S0
G S2 S1 S0
G S2 S1 S0

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 21

Demultiplexers as General-Purpose Logic


n:2n decoder implements any function of n variables
With the variables used as control inputs
Enable inputs tied to 1 and
Appropriate minterms summed to form the function

0
1
2
3
3:8 DEC 4
5
6
7
S2 S1 S0
A

A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC

demultiplexer generates appropriate


minterm based on control signals
(it "decodes" control signals)

C
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 22

Demultiplexers as General-Purpose Logic


(contd)
F1 = A' B C' D + A' B' C D + A B C D
F2 = A B C' D + A B C
F3 = (A' + B' + C' + D')
4:16
DEC

Enable

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

A'B'C'D'
A'B'C'D
A'B'CD'
A'B'CD
A'BC'D'
A'BC'D
A'BCD'
A'BCD
AB'C'D'
AB'C'D
AB'CD'
AB'CD
ABC'D'
ABC'D
ABCD'
ABCD

F1

F2

F3

A B C D
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 23

Cascading Decoders
5:32 decoder
1x2:4 decoder
4x3:8 decoders

0
2:4 DEC 1
2
S1 S0 3
A

0
1
2
3:8 DEC 3
4
5
6
7
S2 S1 S0

0
1
2
3:8 DEC 3
4
5
6
7
S2 S1 S0
C

A'B'C'D'E'

ABCDE

0
1
2
3:8 DEC 3
4
5
6
7
S2 S1 S0

0
1
2
3:8 DEC 3
4
5
6
7
S2 S1 S0
C

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 24

A'BC'DE'

AB'C'D'E'

AB'CDE

Read-only Memories
Two dimensional array of 1s and 0s

word lines (only one


is active decoder is
just right for this)

Entry (row) is called a "word"


Width of row = word-size

Index is called an "address"


Address is input
Selected word is output

n
2 -1

decoder

word[i] = 0011

word[j] = 1010

0
internal organization
0

n-1
Address

bit lines (normally pulled to 1 through


resistor selectively connected to 0
by word line controlled switches)

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 25

ROMs and Combinational Logic


Combinational logic implementation (two-level
canonical form) using a ROM
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

C
0
1
0
1
0
1
0
1

F0
0
1
0
0
1
1
0
0

F1
0
1
1
0
0
0
0
1

F2
1
1
0
0
1
0
0
0

truth table

F3
0
0
0
1
1
0
1
0

ROM
8 words x 4 bits/word

A B C
F0F1F2F3
address
outputs
block diagram

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 26

ROM Structure
Similar to a PLA structure but with a fully decoded
AND array
Completely flexible OR array (unlike PAL)
n address lines

inputs

decoder

2n word
lines

memory
array
(2n words
by m bits)
outputs

m data lines

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 27

ROM vs. PLA


ROM

Design time is short (no need to minimize output functions)


Most input combinations are needed (e.g., code converters)
Little sharing of product terms among output functions
Size doubles for each additional input
Can't exploit don't cares
Cheap (high-volume component)
Can implement any function of n inputs
Medium speed

Design tools are available for multi-output minimization


There are relatively few unique minterm combinations
Many minterms are shared among the output functions
Most complex in design, need more sophisticated tools
Can implement any function up to a product term limit
Slow (two programmable planes)

PLA

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 28

Field-Programmable Gate Arrays


PLAs: 100s of gate equivalents
FPGAs: 1000-10000s gates
Logic blocks
Implement combinational
and sequential logic

Interconnect

Wires to connect inputs and


outputs to logic blocks

I/O blocks

Special logic blocks at


periphery of device for
external connections

Key questions:

How to make logic blocks programmable?


How to connect the wires?
After the chip has been fabbed
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 29

Tradeoffs in FPGAs
Logic block - how are functions implemented: fixed functions
(manipulate inputs) or programmable?
Support complex functions, need fewer blocks, but they are bigger
so less of them on chip
Support simple functions, need more blocks, but they are smaller so
more of them on chip

Interconnect
How are logic blocks arranged?
How many wires will be needed between them?
Are wires evenly distributed across chip?
Programmability slows wires down are some wires specialized to
long distances?
How many inputs/outputs must be routed to/from each logic block?
What utilization are we willing to accept? 50%? 20%? 90%?
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 30

Xilinx 4000 Series Programmable Gate


Arrays
CLB - Configurable Logic Block
5-input, 1 output function

Can be used as memory


Three types of routing

IOB

IOB

IOB

Built-in fast carry logic

IOB

IOB

IOB

or 2 4-input, 1 output functions


optional register on outputs

CLB

direct

CLB

can be reconfigured

IOB

RAM-programmable

IOB

Wiring Channels

general-purpose
long lines of various lengths

CLB

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 31

The Xilinx 4000 CLB

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 32

CLB

Two 4-Input Functions, Registered


Output

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 33

5-Input Function, Combinational


Output

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 34

CLB Used as RAM

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 35

Xilinx 4000 Interconnect

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 36

Xilinx FPGA Combinational Logic Examples


Key: General functions are limited to 5 inputs
(4 even better - 1/2 CLB)
No limitation on function complexity

Example
2-bit comparator:
A B = C D and A B > C D implemented with 1 CLB
(GT) F = A C' + A B D' + B C' D'
(EQ) G = A'B'C'D'+ A'B C'D + A B'C D'+ A B C D

Can implement some functions of > 5 input

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 37

Xilinx FPGA Combinational Logic


Examples
N-input majority function: 1 whenever n/2 or more inputs are 1
N-input parity functions: 5 input/1 CLB; 2 levels yield 25 inputs!
5-input Majority Circuit
9 Input Parity Logic

CLB

CLB
7-input Majority Circuit
CLB
CLB
CLB
CS 150 - Fall 2005 Lec. #3: Programmable Logic - 38

CLB

Xilinx FPGA Adder Example


Example

2-bit binary adder - inputs: A1, A0, B1, B0, CIN


outputs: S0, S1, Cout

A3 B3

A2 B2

A1 B1

CLB

CLB

CLB

Cout

S3

S2

C2

C1

A3 B3 A2 B2

CLB

A0 B0 Cin

Full Adder, 4 CLB delays to


final carry out

CLB

S1

C0

S0

A1 B1 A0 B0 Cin

S2

CLB

S0

S3

2 x Two-bit Adders (3 CLBs


each) yields 2 CLBs to final
carry out

S1

Cout

C2

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 39

Combinational Logic Implementation


Summary
Regular Logic Structures
Programmable Logic Arrays
Programmable connections: AND-OR (NOR-NOR) Arrays

Multiplexers/decoders
Multipoint connections for signal routing
Lookup Tables

ROMs
Truth table in hardware

Field Programmable Gate Arrays (FPGAs)


Programmable logic (LUTs, Truth Tables) and connections

Advantages/disadvantages of each

CS 150 - Fall 2005 Lec. #3: Programmable Logic - 40

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