Vigo University

Department of Electronic Technology

Dissertation submitted for the degree of

European Doctor of
Philosophy in Electrical Engineering

Contributions to Grid-Synchronization
Techniques for Power Electronic Converters

Author: Francisco Daniel Freijedo Fernndez

Director: Jess Doval Gandoy

Vigo, 9 June 2009

Ph.D. Committee Members:

Carlos Martnez Pealver
Carlos Couto
Enrique Acha
Emilio Bueno
Pedro Roncero
Grzegorz Benysek
Marco Liserre
Paolo Mattavelli
Enrique Romero Cadaval
Enrique Barreiro

9 June 2009
University of Vigo
Vigo, Spain

Vita
Francisco Daniel Freijedo Fernndez was born in Ponteareas (Pontevedra), Spain, in
December 1978. He received the M.Sc. in Physics in 2002 from the University of Santiago
de Compostela.
Since 2003 to 2005 he worked as software developer. From February 2005 he is part
time assistant lecturer of the University of Vigo. From June 2008 to October 2008 he
had a research stay at the Power Engineering Group of the University of Glasgow. He
had a research stay at the University of Alcal in February 2009. His research interests
include digital control of Power Electronics Converters, specially for Power Quality and
renewable energy applications.
He has authored or coauthored about 20 technical papers in the field of power electronics, 8 of which are IEEE Transactions grade. He is member of the IEEE since 2007
and also of the IEEE Industrial Electronics and IEEE Power Electronics Societies.

Contributions to Grid-Synchronization Techniques for

Power Electronic Converters
Francisco Daniel Freijedo Fernndez

(Abstract)
Real time grid-synchronization techniques are studied in this dissertation. The synchronization block is a crucial part of the controller in grid-connected power converters.
The phase-angle of the voltage/current vector fundamental component at the point of
common coupling (PCC) should be tracked online in order to control the energy transfer
between the power converter and the ac mains. Synchronization algorithms have been
evolving since the first analog zero-cross detectors to current high performance digital
implementations.
An in-depth review of the state-of-art in grid synchronization is contributed in the
Chapter 2 of this PhD dissertation. In some ways, it could be said that the grid synchronization state-of-art has been evolving to avoid malfunctions due to power quality
phenomena. The Ainsworth proposal of using a voltage controlled oscillator (VCO) inside the control loop of a High Voltage Direct Current (HVDC) successfully dealt with
the novel, at that time, harmonic instability problem. Subsequently, analog phase locked
loops (PLL) were proposed to be used as measurement blocks, which provide frequency
adaptation in motor drives. Since then, controllers using analog and digital PLLs have
been proposed in all kind of applications such as controlled rectifiers, Flexible ac Transmission Systems (FACTS) and power line conditioners. Nowadays, the fields of Distributed
Power Generation Systems (DPGS), power line conditioners and traction applications
have an important demand of optimized synchronization algorithms. Even though the
main part of chapter 2 is only dedicated to synchronization with fundamental component
(and positive-sequence), the issue of harmonic and negative sequences extraction is also
dealt with. The advanced synchronization/extraction methods based on synchronous reference frames (SRFs) and moving average filters (MAFs), which are major contributions
of this PhD dissertation, are introduced in this chapter.
Digital PLLs are the most employed synchronization algorithm, mainly due to their
simple implementation, good frequency adaptation and acceptable filtering versus transient response trade-off. Chapter 3 is devoted to digital PLLs design. In a general way,
PLLs with a low bandwidth (low-gain PLLs) are required when handling with distorted
voltages. It is analytically demonstrated that low-gain PLLs have more trade-offs than
high-gain PLLs (e.g. PLLs for communications): it is not possible to optimize the settling
time for a phase-jump without getting slower the PLL response to frequency variations.
Existing tuning methods do not take into account low-gain features, which may result in
non-optimum designs. An intuitive tuning methodology based on inspection of frequencydomain diagrams is contributed in this chapter. Contrary to the other existing tuning
methods, it takes into account low-gain dynamics. It is assured an optimized performance

in the presence of any kind of disturbances in the grid. In the second part of the chapter,
the DCO based on a RC oscillator is presented: the digital model of a sinusoidal oscillator is implemented, instead of explicit trigonometric functions. This solution reduces
the needed digital resources without reducing the performance, which could be specially
useful for DSP-based control of power converters.
SRF synchronization algorithms based on moving average filters (SRF-MAF), which
have been introduced in chapter 2, provide a quite fast transient response and very good
harmonic cancellation. However, its main drawback with respect of PLLs is its lack of
frequency adaptation working open loop. This problem is also observed in other schemes
based on stochastic filtering. A novel synchronization technique based on filtering in the
SRF provided in chapter 4. The main novelty with respect to previous works is the fact
that it is frequency adaptive working open loop. This is achieved by cascading two kinds
of finite impulse response (FIR) filters: a moving average FIR filter providing an excellent
harmonic cancellation and a predictive filter compensating for the negative phase (delay)
introduced by the first one. The resulting schemes are named Predictive SRF-MAFs.
It is proved that predictive SRF-MAFs have a very high performance under distorted
conditions, specially when compared with PLLs.
Chapter 5 provides a novel approach in the implementation of Proportional+Resonant
(PR) current controllers, specially suitable for active power filters (APFs) compensating
for high order harmonics. The difference equation to implement each resonant controller
has been obtained from the impulse invariant discretization method. An explicit estimation of the grid-frequency deviation, which is obtained from a PLL, is employed to update
online the PR current controller. An excellent frequency adaptation is achieved with this
technique. Technical details of the whole discrete-time controller are provided. A 1 kVA
rated lab prototype has been implemented and tested. Experimental tests show how the
system performs both in steady-state and under different transients. Perfect tracking in
steady-state for a wide range of grid-frequencies is achieved. Regarding transient response,
different tests were programmed such as load transients (change in the load), sudden and
large changes in the ac mains frequency (frequency steps) and strong source voltage faults
(voltage sags with phase-jump). Experimental results prove how the system is robust and
fast responding to all of these possible real operation faults. Even though this chapter is
focused in APF applications, the proposed PR controller is suitable for a vast range of
industrial applications such as power line conditioners (including APFs), DPGS, FACTS,
controlled rectifiers, motor drives, etc.
Chapter 6 is devoted to review all the contributions of this PhD thesis. A brief outline
of the future work is also provided.

Acknowledgments
First of all, I would like to thank my director, Dr. Jess Doval, for his patience,
guidance and support. He introduced me to the interesting field of power electronics, and
more specifically in the issue of grid-synchronization.
Secondly, I would like to express my appreciation to my colleagues of the Electronic
Technology Department of the University of Vigo. Specially, I would like to thank Dr.
Oscar Lpez for the technical feedback, his continuous support and his help with LATEX.
I would like to thank Professor Enrique Acha for giving me the opportunity to be
at the University of Glasgow, and for his invaluable help during the development of this
dissertation.
I would also like to thank University of Vigo for the grant I was given to stay in
Glasgow.
I wish to thank Dr Emilio Bueno for the good moments at IECON 2008, and for
having invited me to the University of Alcala.
I would like to thank the PhD Committee Members for their comments which help to
improve the overall quality of this dissertation.
I wish to thank all the colleagues and students for the good moments we shared.
Especially, I would like to mention Enrique Ortega, Pablo, Jano, Jacobo, Renato and
Alejandro.
I would like to thank Carmenza by her English classes and for the good moments we
shared with Miguel.
Finally, I would like to dedicate this dissertation to my family, specially to my parents
for having encouraged me to study and to Silvinha for her unconditional love.

 mia familia,
Silvinha, Ma Victoria, Bernardo, Marivi, Carmia e Amelia

Contents

Contents

List of Figures

ix

List of Tables

xvii

List of Abbreviations and Acronyms

xix

Nomenclature

xxiii

1 Introduction

1.1

Objectives and Motivation of this Work . . . . . . . . . . . . . . . . . . . .

1.2

Background on Electric Power Definitions . . . . . . . . . . . . . . . . . .

1.2.1

Power Definitions under Sinusoidal Conditions . . . . . . . . . . . .

1.2.1.1

Electrical Variables with Phasor Notation . . . . . . . . .

Power Definitions under Non-Sinusoidal Conditions . . . . . . . . .

1.2.2.1

1.2.2

Power Definitions in the Frequency Domain by Budeanu .

1.2.2.1.1

Apparent Power S: . . . . . . . . . . . . . . . . .

1.2.2.1.2

Active Power P : . . . . . . . . . . . . . . . . . .

1.2.2.1.3

Reactive Power Q: . . . . . . . . . . . . . . . . .

ii

1.2.2.2

1.2.3

1.2.2.1.5

Power Factor . . . . . . . . . . . . . . . . . . .

1.2.2.1.6

Displacement Factor cos () . . . . . . . . . . . .

1.2.2.1.7

Distortion Factor cos() . . . . . . . . . . . . . .

Power Definition in the Time Domain by Fryze . . . . . .

1.2.2.2.1

Active Power Pw . . . . . . . . . . . . . . . . . .

1.2.2.2.2

Apparent Power Ps . . . . . . . . . . . . . . . . .

1.2.2.2.3

Active Power Factor . . . . . . . . . . . . . . .

1.2.2.2.4

Reactive Power . . . . . . . . . . . . . . . . . . .

1.2.2.2.5

Reactive Power Factor q . . . . . . . . . . . . .

1.2.2.2.6

Active Voltage vw and Active Current iw . . . . .

1.2.2.2.7

Reactive Voltage vq and Reactive Current iq

. . 10

1.2.3.1

Power in Balanced Three-phase Systems . . . . . . . . . . 10

1.2.3.2

Analysis under Unbalanced Conditions . . . . . . . . . . . 11

1.2.3.2.1

Per-phase Calculation: . . . . . . . . . . . . . . 11

1.2.3.2.2

Aggregate rms Value Calculation: . . . . . . . 12

Power Definitions and Alternatives in Power Electronic

Converters Control . . . . . . . . . . . . . . . . . . . . . . 12

Background on Symmetrical Components . . . . . . . . . . . . . . . . . . . 12

1.3.1

1.4

Distortion Power D . . . . . . . . . . . . . . . . .

Power Definitions in Three-Phase Systems . . . . . . . . . . . . . . 10

1.2.3.3

1.3

1.2.2.1.4

Alternatives in Implementation . . . . . . . . . . . . . . . . . . . . 16

Background on Power Quality . . . . . . . . . . . . . . . . . . . . . . . . . 16

1.4.1

Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1.1

Impulsive Transient . . . . . . . . . . . . . . . . . . . . . 17

iii
1.4.1.2
1.4.2

1.4.3

1.5

Oscillatory Transients . . . . . . . . . . . . . . . . . . . . 17

Short-duration Variations . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.2.1

Interruptions . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4.2.2

Sags (Dips) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4.2.3

Swells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Long Duration Variations . . . . . . . . . . . . . . . . . . . . . . . 18

1.4.3.1

Over-Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4.3.2

Under-Voltage . . . . . . . . . . . . . . . . . . . . . . . . 19

1.4.3.3

Sustained Interruptions . . . . . . . . . . . . . . . . . . . 19

1.4.4

Voltage Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.4.5

Waveform Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4.5.1

Dc Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.4.5.2

Harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4.5.3

Inter-Harmonics . . . . . . . . . . . . . . . . . . . . . . . 20

1.4.5.4

Notching . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.4.5.5

Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.4.6

Voltage Fluctuations . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.4.7

Power Frequency Variations . . . . . . . . . . . . . . . . . . . . . . 21

Power Electronic Converters and Applications . . . . . . . . . . . . . . . . 22

1.5.1

Thyristor Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.5.1.1

Three-phase Full Rectifier . . . . . . . . . . . . . . . . . . 22

1.5.1.2

Applications of Thyristor Converters . . . . . . . . . . . . 25

1.5.1.2.1

High Voltage dc Transmission . . . . . . . . . . . 25

iv

1.5.2

1.5.1.2.2

Flexible ac Transmission Systems . . . . . . . . . 27

1.5.1.2.3

Ac Motor Drives . . . . . . . . . . . . . . . . . . 27

Pulse-Width-Modulated Converters . . . . . . . . . . . . . . . . . . 28
1.5.2.1

Overview of Modulation Techniques . . . . . . . . . . . . 28

1.5.2.1.1

Sinusoidal PWM . . . . . . . . . . . . . . . . . . 29

1.5.2.2

Voltage Source Converters . . . . . . . . . . . . . . . . . . 30

1.5.2.3

Applications of PWM Converters . . . . . . . . . . . . . . 34

1.5.2.3.1

Ac Motor Drives . . . . . . . . . . . . . . . . . . 34

1.5.2.3.2

Uninterruptible ac power supplies . . . . . . . . . 34

1.5.2.3.3

Power Line Conditioners . . . . . . . . . . . . . . 35

1.5.2.3.4

Flexible ac Transmission Systems . . . . . . . . . 35

1.6

Control of Power Electronic Converters and Synchronization . . . . . . . . 36

1.7

Structure of the Document . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

1.7.1

Chapter 2: State-of-the-Art in Grid Synchronization . . . . . . . . . 41

1.7.2

Chapter 3: Dynamics Study of Low-Gain PLLs . . . . . . . . . . . 41

1.7.3

Chapter 4: Predictive based SRF-MAF Synchronization Algorithms 42

1.7.4

Chapter 5: Frequency Adaptive PR Current Controller for APFs . . 42

1.7.5

Chapter 6: Conclusions and Future Work . . . . . . . . . . . . . . . 43

2 State-of-the-Art in Grid Synchronization

2.1

Methods based on Zero-Cross Detection

2.1.1

45
. . . . . . . . . . . . . . . . . . . 46

The First High-Voltage Direct Current Systems . . . . . . . . . . . 48

2.1.1.1

Constant- Method . . . . . . . . . . . . . . . . . . . . . 48

2.1.1.2

Inverse-Cosine Method . . . . . . . . . . . . . . . . . . . . 49

v
2.1.2

2.2

Drawbacks of Zero-cross Detectors . . . . . . . . . . . . . . . . . . 49

2.1.2.1

Improvements in Zero-cross Detectors . . . . . . . . . . . 50

2.1.2.2

Harmonic Instability of Zero-cross based HVDCs . . . . . 50

Phase-Locked Oscillator Control Systems . . . . . . . . . . . . . . . . . . . 52

2.2.1

PLO Linearization . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2.1.1

2.2.2

2.3

2.4

Design Example . . . . . . . . . . . . . . . . . . . . . . . 56

Other Phase-Locked Oscillator Schemes . . . . . . . . . . . . . . . . 62

2.2.2.1

PLO for Voltage Control . . . . . . . . . . . . . . . . . . . 62

2.2.2.2

PLO for Speed Control of dc Motors . . . . . . . . . . . . 62

Phase Locked Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.1

Charge-Pump PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

2.3.2

Digital SRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
2.3.2.1

SRF-PLL Operation . . . . . . . . . . . . . . . . . . . . . 69

2.3.2.2

Pre-filters for the SRF-PLL . . . . . . . . . . . . . . . . . 70

2.3.2.2.1

All-pass Filters based Sequence Detector . . . . . 71

2.3.2.2.2

Delayed Signal Cancellation in the Frame . . 73

2.3.2.2.3

Generalized Integrators in PLLs . . . . . . . . . . 74

2.3.2.2.4

Extended and Generalized Delayed Signal Cancellation . . . . . . . . . . . . . . . . . . . . . . . 75

2.3.3

Digital Single-phase PLL . . . . . . . . . . . . . . . . . . . . . . . . 76

2.3.4

Single-phase PLLs Vs SRF-PLLs . . . . . . . . . . . . . . . . . . . 78

2.3.5

Amplitude Compensation in Digital PLLs . . . . . . . . . . . . . . 78

2.3.6

Limit Cycles of Digital PLLs . . . . . . . . . . . . . . . . . . . . . . 79

Digital Alternatives to PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 82

vi
2.4.1

2.4.2

2.4.3

Filtering in the Frame . . . . . . . . . . . . . . . . . . . . . . . 82

2.4.1.1

Transformation Angle Detector (LP-TAD) . . . . . . . . . 82

2.4.1.2

Normalised Positive-sequence Synchronous Frame (NPSF)

Filtering in Synchronous Reference Frames . . . . . . . . . . . . . . 85

2.4.2.1

Single-phase SRF Synchronization Algorithms . . . . . . . 85

2.4.2.2

MAF as LPF for SRF based Schemes . . . . . . . . . . . . 87

2.4.2.3

Equivalent Implementations . . . . . . . . . . . . . . . . . 92

2.4.2.4

Three-phase SRF Synchronization Algorithm . . . . . . . 93

2.4.2.5

SRF-MAFs for Harmonics and Negative-sequences Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Stochastic Filtering based Synchronization Schemes . . . . . . . . . 96

2.4.3.1

Kalman Filtering . . . . . . . . . . . . . . . . . . . . . . . 96
2.4.3.1.1

2.4.3.2

2.6

Single-phase Example . . . . . . . . . . . . . . . 96

Weighted Least-Squares Estimation (WLSE) algorithms . 99

2.4.3.2.1

2.5

83

Three-phase WLSE Algorithm . . . . . . . . . . . 99

Frequency Adaptation of Synchronization Algorithms . . . . . . . . . . . . 104

2.5.1

Frequency Adaptation in WLSE Schemes . . . . . . . . . . . . . . . 106

2.5.2

Frequency Adaptive MAFs . . . . . . . . . . . . . . . . . . . . . . . 107

2.5.3

Adaptative Filtering for Frequency Adaptation/Estimation . . . . . 109

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3 Dynamics Study of Low-Gain PLLs

115

3.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.2

Frequency Domain Based Tuning . . . . . . . . . . . . . . . . . . . . . . . 116

vii
3.2.1

Stability Margins and Cut-off Frequency . . . . . . . . . . . . . . . 117

3.2.2

Steady-state Distortion and Bandwidth . . . . . . . . . . . . . . . . 118

3.2.3

Grid Events and Transient Responses . . . . . . . . . . . . . . . . . 119

3.2.3.2

Overdamped Case: > 1 . . . . . . . . . . . . . . . . . . 121

Limitations of Existing Tuning Approaches for Low-gain PLLs . . . 123

3.2.5

Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

3.2.5.1

High Bandwidth SRF-PLL (HB-PLL) . . . . . . . . . . . 124

3.2.5.2

Unbalance/Notch SRF-PLL (UN-PLL) . . . . . . . . . . . 125

3.2.5.3

SRF-PLL with Moving Average Filter (MA-PLL) . . . . . 126

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 127

RC Model of Digitally Controlled Oscillator . . . . . . . . . . . . . . . . . 129

3.3.1

3.4

Underdamped Case: < 1 . . . . . . . . . . . . . . . . . . 121

3.2.4

3.2.6
3.3

3.2.3.1

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.3.1.1

Simulation Results . . . . . . . . . . . . . . . . . . . . . . 131

3.3.1.2

Single-phase PLL Implementation . . . . . . . . . . . . . . 131

3.3.1.3

SRF-PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

4 Predictive based SRF-MAF Synchronization Algorithms

135

4.1

Calculation of Predictive Filters . . . . . . . . . . . . . . . . . . . . . . . . 137

4.2

Design Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.3

4.2.1

Design Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.2.2

Design Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

viii
4.4

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

4.4.1

4.5

Brief Comparative . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

5 Frequency Adaptive PR Current Controller for APFs

153

5.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

5.2

Active Power Filter Prototype . . . . . . . . . . . . . . . . . . . . . . . . . 156

5.3

Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.3.1

5.4

PLL Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

PR Current Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

5.4.1

Resonant Controllers Implementation . . . . . . . . . . . . . . . . . 161

5.4.2

Frequency Adaptive Implementation of Resonant Blocks . . . . . . 162

5.4.2.1

5.4.3

Effect of the Frequency Correction in Dynamics . . . . . . 163

Design and Tuning of C(z) . . . . . . . . . . . . . . . . . . . . . . . 165

5.5

Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

5.6

Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

6 Conclusion and Future Work

173

6.1

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

6.2

Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

6.3

Future Research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

A Matlab Scripts

175

References

183

List of Figures

1.1

Simple electrical system. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Waveforms associated to power concepts in a linear single-phase circuit. . .

1.3

Voltage/current and Power phasors for Fig. 1.2 example. . . . . . . . . . .

1.4

Example of decomposition of an unbalanced three-phase set of fundamental

voltages/currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5

vabc in the SRF established by . . . . . . . . . . . . . . . . . . . . . . . . 15

1.6

6-pulse thyristor based rectifier. . . . . . . . . . . . . . . . . . . . . . . . . 23

1.7

Working points of the thyristor full wave rectifier. . . . . . . . . . . . . . . 25

1.8

Steady-state voltages of the thyristor three-phase full rectifier. . . . . . . . 26

1.9

Simple HVDC diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.10 ac Motor controlled with Thyristor-based inverter and rectifier. . . . . . . . 27

1.11 One leg of a switch mode inverter. . . . . . . . . . . . . . . . . . . . . . . . 29
1.12 Set of S+ firing signal with sinusoidal PWM. . . . . . . . . . . . . . . . . . 30
1.13 va output with sinusoidal PWM. . . . . . . . . . . . . . . . . . . . . . . . . 31
1.14 Fourier Components of va . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.15 VSC connected to an ac source. . . . . . . . . . . . . . . . . . . . . . . . . 32
1.16 Per-phase representation of VSC connected to an ac source. . . . . . . . . 32
1.17 Complex power diagram of grid-connected VSC. . . . . . . . . . . . . . . . 33
ix

x
1.18 P Q diagram. Operation points of grid-connected VSCs. . . . . . . . . . 34
1.19 Control of induction motor by PWM-VSI with diode rectifier . . . . . . . . 34
1.20 Simplified dc-link voltage control loop of VSC. . . . . . . . . . . . . . . . . 37
1.21 VSC operation in steady-state. Effect of phase-error. . . . . . . . . . . . . 38
1.22 VSC operation in steady-state. Effect of ripple in 1 . . . . . . . . . . . . . 39
1.23 VSC operation during a transient. Effect of the re-tracking speed. . . . . . 40
2.1

Zero-cross detector example. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

2.2

OA based zero-cross detector example. . . . . . . . . . . . . . . . . . . . . 47

2.3

Simple HVDC diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2.4

Constant- vs Inverse-Cosine HVDCs. . . . . . . . . . . . . . . . . . . . . 49

2.5

Main drawbacks of zero-cross detectors. . . . . . . . . . . . . . . . . . . . . 51

2.6

Weak Grid. Short circuit ratio Xr /Xs 3 6. . . . . . . . . . . . . . . . . 52

2.7

Scheme of the PLO controller for the HVDC rectifier proposed in [1]. . . . 53

2.8

Equivalent block diagram of PLO circuit and control. . . . . . . . . . . . . 55

2.9

Equivalent block diagram of PLO circuit and controller for firing maximum
delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.10 PLO equivalent model at different values. . . . . . . . . . . . . . . . . . 57

2.11 Start-up simulation of PLO for different idc (dotted), idc is the blue line. . . 58
2.12 Steady-state system voltages for Figs. 2.12. . . . . . . . . . . . . . . . . . . 59
2.13 PLO tested under a very unbalanced system of voltages. . . . . . . . . . . 59
2.14 PLO tested in the presence of an unbalanced and polluted with harmonics
system of voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.15 PLO transient test: sudden change in zL . . . . . . . . . . . . . . . . . . . . 61
2.16 PLO tested under a sudden change in the input frequency at 10 s. . . . . . 61

xi
2.17 Control scheme of a dc motor in a single-phase grid. . . . . . . . . . . . . . 63
2.18 Basic conceptual models of PLLs. . . . . . . . . . . . . . . . . . . . . . . . 64
2.19 Block diagram of an analog CP-PLL. . . . . . . . . . . . . . . . . . . . . . 65
2.20 Key diagrams for the EXOR-Charge Pump Phase Detector . . . . . . . . . 66
2.21 Time domain simulation results from the CP-PLL model at f = 49 Hz. . . 67
2.22 SRF-PLL block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.23 SRF-PLL with Fortescue operator based pre-filter. . . . . . . . . . . . . . . 71
2.24 Matlab Simulink model and all-pass filter features. . . . . . . . . . . . . . . 72
2.25 Positive-sequence estimation with all-pass filters (f1 = 50 Hz). . . . . . . . 72
2.26 SRF-PLL with pre-filters in the frame. . . . . . . . . . . . . . . . . . . 73
2.27 Comparative of the dynamics of A(z) and D(z) (fs = 10 kHz, so n = 50 in D(z)). 74
2.28 Hd (s) and Hq (s) dynamic response. . . . . . . . . . . . . . . . . . . . . . . 76
2.29 Single-phase PLL with multiplier as PD. . . . . . . . . . . . . . . . . . . . 77
2.30 ALL-PLL compensation block. . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.31 Key figures of the ALL-PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . 80
2.32 Phase-plane portraits of a SRF-PLL implementation. The curves are obtained through different initial conditions (color legends indicate the initial
1 ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.33 LP-TAD scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2.34 Significant simulation results for LP-TAD: fault and unbalance conditions.

84

2.35 v1 in the single-phase SRF. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.36 Single-phase SRF synchronization algorithm: srf = 1 to decouple v1 . . . 86
2.37 Time and frequency responses of H(z)1 implemented at fs = 10 kHz and
n = 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
2.38 Simulation results for SRF-MAF1 working open loop (srf = 1 = 1n ). . . 91

xii
2.39 DCT based implementation figures. . . . . . . . . . . . . . . . . . . . . . . 92
+
. . 93
2.40 Three-phase SRF synchronization algorithm; srf = 1 to decouple vabc
1

2.41 Simulation results for SRF-MAF3 working in open loop (srf = 1 = 1n ).

95

2.42 Single-phase Kalman based synchronization algorithm. . . . . . . . . . . . 98

2.43 WLSE experimental results for different s. . . . . . . . . . . . . . . . . . 102
2.44 WLSE experimental results. Effect of adding extra sequences to H. . . . . 103
2.45 Frequency adaptive MAFs. . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.46 Adaptive filter scheme of SRF-MAF1 with frequency adaptation/estimation.110
2.47 Adaptive SRF-MAF1 Vs open loop SRF-MAF1 during the start-up and
steady-state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
2.48 Frequency estimation with Adaptive SRF-MAF3. . . . . . . . . . . . . . . 113
3.1

Studied linear model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.2

Frequency response of different filters for canceling harmonics. . . . . . . . 119

3.3

Comparative between underdamped and overdamped cases. . . . . . . . . . 123

3.4

Frequency response of H(z) for the HB-PLL (L(s)HBP LL was discretized

using the zoh method). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.5

Frequency response of H(z) for the UN-PLL (L(s)U N P LL was discretized

using the zoh method). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

3.6

Frequency response of H(z) for the MA-PLL (PI filter was discretized using
the zoh method). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

3.7

Experimental results for different SRF-PLLs: Ch1 (black) is the Va input in

p.u./V, Ch4 is the instantaneous phase-angle measurement (100 mV/rad),
Ch2 is the error signal vq in p.u./V (1 p.u. = /2 deg of phase error), Ch3
is o (10 mV/(rad/s)). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

3.8

RC Oscillator features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

3.9

P1+ generation from the oscillator signals. . . . . . . . . . . . . . . . . . . . 131

xiii
3.10 Simulation results for single-phase PLL (1 = 250.3 rad/s). . . . . . . . . 132
3.11 Experimental results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
4.1

Filtering blocks of the design examples. . . . . . . . . . . . . . . . . . . . . 139

4.2

Design example 1: time and frequency responses of H1 (z) H2 (z). . . . . . 140

4.3

Design example 2: Frequency and Step responses of H1 (z) H1 (z) H2 (z). . 142

4.4

S1: Test to show predictive filters action. . . . . . . . . . . . . . . . . . . . 143

4.5

S1 response to a big frequency step at 0.2 s. Unbalanced (va1

= 0.1
max
+
va1max ) input wave. Frequency step (up), phase error (center) and frequency error (down). Zero steady state error and transient duration of
0.01 s are achieved. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

4.6

S1 tested under a distorted set of input waves rotating at 49.5 Hz. At 1 s,

a 1 p.u. to 0.2 p.u. sag with +45 deg phase jump has been programmed. . . 145

4.7

S1: steady state error for a balanced set of inputs oscillating at 48 Hz. . . . 146

4.8

+
S1: Steady state error for an unbalanced (va1
= 0.1 va1
) set of inputs
max
max
oscillating at 51 Hz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

4.9

S1: Transient response for a sag with 45 deg phase jump. . . . . . . . . . 148

4.10 S1: steady-state phase measurement at 48 Hz. Ch1 is 1 , Ch2 is va , Ch3 is

vb , Ch4 is vc (phase in 2 rad, voltages in p.u.). The measurement does
not have ripple. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
+
4.11 Comparative between S1 and S2 in terms of noise rejection. Ch1 is va1
,
max
Ch2 is va , Ch3 is vb , Ch4 is vc (voltages in p.u., 1 = 2 49.75 rad/s). . . 150
+
4.12 S1 Vs S2 in terms of transient response. Ch1 is va1
, Ch2 is va , Ch3 is
max
vb , Ch4 is vc (voltages in p.u., 1 = 2 49 rad/s). . . . . . . . . . . . . . . 150

5.1

APF prototype and controller. . . . . . . . . . . . . . . . . . . . . . . . . . 157

5.2

Experimental set-up features. . . . . . . . . . . . . . . . . . . . . . . . . . 158

5.3

Phase locked loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

5.4

Open loop PLL Bode diagram.

. . . . . . . . . . . . . . . . . . . . . . . . 160

xiv
5.5

Two integrators based implementations, as proposed in [2]. . . . . . . . . . 161

5.6

Comparative of the error induced by different implementations (fs = 10 kHz).163

5.7

Frequency adaptive resonant block implementation. . . . . . . . . . . . . . 163

5.8

Accuracy of the resonant controllers (fs = 10 kHz). . . . . . . . . . . . . . 164

5.9

Frequency response of C(z) P (z) around 150 Hz. When

1 > 0 the peak
moves to higher frequencies and vice versa. . . . . . . . . . . . . . . . . . 164

5.10 Current control block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 165

5.11 PR block (C(z)). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.12 Bode diagram of C(z) P (z).

. . . . . . . . . . . . . . . . . . . . . . . . . 167

5.13 Steady-state currents and vP CC for different input frequencies. Ch1 is iL ,

Ch2 is iF , Ch3 is iS and Ch4 is vP CC . . . . . . . . . . . . . . . . . . . . . . 168
5.14 Transient response when there is a load change. Ch1 is iL , Ch2 is iF , Ch3
is iS and Ch4 is vP CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.15 Transient response when there is a frequency step in f1 from 48 Hz to 52 Hz.
Ch1 is iL , Ch2 is iF , Ch3 is iS and Ch4 is vP CC . . . . . . . . . . . . . . . . 169
5.16 Transient response when there is a frequency step in f1 : from 52 Hz to
48 Hz. Ch1 is iL , Ch2 is
1 (scale at 23 rad/div), Ch3 is iS and Ch4
is vP CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
5.17 Transient response when there is a frequency step in f1 from 48 Hz to
52 Hz. Effect of ripple of 1 Hz in
1 . Ch1 is iL , Ch2 is 1 (scale at
23 rad/div), Ch3 is iS and Ch4 is vP CC . . . . . . . . . . . . . . . . . . . 170
5.18 Steady state figures when error in estimation of
1 is considered.
1 =
0 rad/s and 1 = 4 rad/s (f1 = 48 Hz). Ch1 is iL , Ch2 is 1 (scale
at 23 rad/div), Ch3 is iS and Ch4 is vP CC . . . . . . . . . . . . . . . . . 171
5.19 Transient response when there is a voltage sag (1 p.u. 0.8 p.u.) with
phase-angle jump of +45 deg in vP CC (vS ). Ch1 is iL , Ch2 is 1 (scale at
23 rad/div), Ch3 is iS and Ch4 is vP CC . . . . . . . . . . . . . . . . . . . 171
A.1 PLO system Matlab script. Main file. . . . . . . . . . . . . . . . . . . . . . 176
A.2 PLO system Matlab script. Function file (page 1 of 2). . . . . . . . . . . . 177

xv
A.3 PLO system Matlab script. Function file (page 2 of 2). . . . . . . . . . . . 178
A.4 Matlab script to depict SRF-PLL trajectories in the Phase-plane. . . . . . 179
A.5 Matlab script of the Kalman Filter Single-phase synchronization example. . 180
A.6 Matlab script of the WLSE syncrhonization example. . . . . . . . . . . . . 181
A.7 Matlab script of the single-phase PLL with RC-Oscillator based DCO. . . . 182

xvi

List of Tables

1.1

States of diode full rectifier depending of 1 . . . . . . . . . . . . . . . . . . 24

1.2

State of controlled rectifier depending of 1 and . . . . . . . . . . . . . . . 24

1.3

VSC based Rectifier Values. . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.1

HVDC values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

2.2

Controller Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

2.3

Controller Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

2.4

Look-up table: control of n depending on

1 . . . . . . . . . . . . . . . . . 107

2.5

Adaptive algorithm values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.1

Significant parameters of HB-PLL . . . . . . . . . . . . . . . . . . . . . . . 124

3.2

Significant parameters of UN-PLL . . . . . . . . . . . . . . . . . . . . . . . 125

3.3

Significant parameters of MA-PLL . . . . . . . . . . . . . . . . . . . . . . 126

4.1

Design Example 1 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

4.2

Design Example 2 Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

4.3

Brief comparative among significant systems with good unbalance rejection 148

5.1

Significant values of the power circuit. . . . . . . . . . . . . . . . . . . . . 156

5.2

Values of PLL parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

xvii

xviii
5.3

Values of parameters of the PR controller. . . . . . . . . . . . . . . . . . . 166

List of Abbreviations and Acronyms

ac

Alternate current.

ADC

Analog-to-digital converter.

ADALINE

Adaptive Linear Combiner.

APF

Active Power Filter.

CP

Charge-Pump (PLL).

dc

Direct current.

DCO

Digitally Controlled Oscillator.

DCT

Discrete Cosine Transform.

DFT

Discrete Fourier Transform.

DPGS

Distributed Power Generation System.

DSP

Digital Signal Processor.

DSRF

Double SRF. Applied to a PLL (DSRF-PLL).

DST

Discrete Sine Transform.

EXOR

Exclusive OR.

EKF-TAD

Enhanced Kalman Filter-TAD (Synchronization Algorithm).

FACTS

Flexible ac Transmission Systems.

FIR

Finite Impulse Response (filter).

FPGA

field-programmable gate array.

GI

Generalized integrator.

GTO

gate turn-off thyristor.

HVDC

High-Voltage Direct Current.

xix

xx
IC

Integrated Circuit.

IEEE

Institute of Electrical and Electronics Engineers.

IIR

Infinite Impulse Response (filter).

IGBT

insulated-gate bipolar transistor.

IGCT

integrated gate-commutated thyristor.

LF

Loop filter (PLL).

LPF

Low pass filter.

LP-TAD

Low pass-TAD (Synchronization Algorithm).

MAF

Moving average Filter.

MSRF

Multiple Synchronous Reference Frame.

NPSF

Normalised Positive-sequence Synchronous Frame.

OA

Operational Amplifier.

PCC

Point of common coupling.

PD

Phase detector (PLL).

PI

Proportional Integrator (filter).

PLL

Phase locked loop.

PLO

Phase locked oscillator (control system).

PM

Phase margin.

PQ

Power Quality.

PR

Proportional+Resonant (current controller).

PWM

Pulse Width Modulation.

RDFT

Recursive DFT.

SRF

Synchronous Reference Frame.

SSSC

Static Synchronous Series Compensator.

SRF-MAF

Synchronization algorithm based on SRF and MAFs.

STATCOM

static compensator.

SVC

static VAr compensator.

SVF-TAD

Space Vector Filter-TAD (Synchronization Algorithm).

xxi
TAD

Transformation angle detector.

THD

Total Harmonic Distortion.

UPFC

unified power-flow controller.

VCO

Voltage Controlled Oscillator (IC).

VSC

voltage-source controller.

VSI

voltage-source inverter.

WLSE

Weighted Least Squares Estimation (Synchronization Algorithms).

xxii

Nomenclature

Firing angle in thyristor based converters.

Angle transformation from an rotating frame to a dq frame.

Clarke transformation from an abc rotating frame to an equivalent frame.

Small perturbation in .

Duty cycle of PWM converters..

Optimization parameter of predictive filters.

Frequency in Hz..

f1n

Nominal fundamental frequency (e.g. 50 Hz in Europe).

fs

Sampling frequency of a discrete model.

Relative phase-angle between i(t) and v(t).

Offset phase-angle.

Single-phase current.

Vector of currents in a multiphase system or reference frame.

Imaginary Unit.

Modulating/control signal of PWM converters.

Set the order of a filter.

xxiii

xxiv
N1

Set the order of a MAF (chapter 4).

N2

Set the order of a predictive filter (chapter 4).

Active Power.

Park transformation from an abc rotating frame to a dq static frame.

Reactive Power.

Resistance.

Apparent Power.

Fortescue matrix.

Time, in seconds.

= 1/f . Time cycle.

Very short instant, in seconds.

Instantaneous rotating phase-angle.

Single-phase voltage.

Vector of voltages in a multiphase system or reference frame.

= 2f . Angular frequency or pulsation.

Impedance.
Subscript

Fundamental component.

abc

Voltage/current vector in the abc frame.

Phase a in the abc frame.

Phase b in the abc frame.

xxv
c

Phase c in the abc frame.

co

Relative to controlled oscillator (voltage).

cp

Relative to charge-pump (voltage).

Voltage/current vector in the frame.

Component in the frame.

Component in the frame.

Relative to d component in a srf .

dc

Voltages/currents in a DC bus.

Relative to the error between real and estimated value.

Input value.

Relative to jittering of synchronization algorithms (phase).

ll

Line to line (voltage).

LP F

Low pass filter.

max

Maximum. Peak value referred to voltages/currents.

min

Minimum.

Nominal value, e.g. f1n = 50 Hz nominal fundamental frequency.

Output value.

Relative to q component in a srf .

rms

Root-mean square.

Relative to sampling (f and T ).

Relative to settling time.

srf

Relative to SRF.

xxvi
Superscript

Positive sequence.

Negative sequence.

Zero sequence.

Transpose of a matrix.

(1)

Inverse of a matrix.

Reference value.
Accents

Average value of x.

Estimated value of x.

x vector of voltages/currents in phasor notation.

Chapter 1
Introduction
1.1

Objectives and Motivation of this Work

This work approaches an in-depth study of synchronization algorithms employed in

the control of grid-connected power electronics converters. The goal of this research is to
supply an added knowledge to all the researchers and engineers working in this field.
Due to the high amount of recent proposals and applications, an in-depth review of the
state-of-art in grid synchronization seems to be necessary. Active fields of research such
as Flexible ac Transmission Systems (FACTs), Distributed Power Generation Systems
(DPGS), Power Conditioning and Traction Systems claim for an ever-increasing performance of synchronization algorithms. This works provides a study of existing schemes and
implementation techniques and also provides novel high performance algorithms. Special
emphasis is devoted to take advantage of digital implementation.
It is also a goal of this work to show how a good knowledge in the synchronization field
permits to improve other blocks employed in the controllers of power electronic converters.
A novel discrete-time implementation of the Proportional+Resonant (PR) controllers is
contributed in chapter 5. The added value of this implementation is the manner how each
resonant controller is made frequency adaptive using a phase locked loop (PLL). This
provides robustness in the presence of grid frequency deviations.

1.2

Background on Electric Power Definitions

Some concepts should be defined before the analysis of power systems. These concepts
and definitions of electric power for sinusoidal ac systems are well stated and accepted
nowadays when considering ideal conditions. However, under distorted conditions, several
1

Chapter 1 Introduction

Ideal AC
Source

Linear Load
v

= 2 f
Figure 1.1: Simple electrical system.

and different power definitions and theories are still in use [3].

1.2.1

Power Definitions under Sinusoidal Conditions

The simple single-phase electrical systems depicted in Fig. 1.1 is considered. The ideal
ac source generates a sinusoidal voltage rotating at the the angular frequency, also named
frequency pulsation . The frequency of oscillation in [ Hz] is obtained as f = /(2).
The ac source is connected to a linear load. The instantaneous voltage and current can
be analytically represented by

v(t) =

2 vrms sin (t + v ),

(1.1)

where v is a constant offset phase-angle, and

i(t) =

2 vrms sin (t + i ),

(1.2)

where i is also a constant offset phase-angle. The relative angle between v(t) and i(t)
() is given by

= v i .

(1.3)

is set by the load reactance: > 0 (the current lags the voltage) for inductive loads,
and < 0 (the current leads the voltage) for capacitive loads. The value of in Fig. 1.1
is limited in the range [90 deg 90 deg]. The instantaneous active power p(t) is

1.2 Background on Electric Power Definitions

given by the product of the instantaneous voltage and current:

p(t) = v(t) i(t) = P [1 cos (21 t)] Q sin (21 t),

(1.4)

P = vrms irms cos ()

(1.5)

where

is named active power, for which the measurement unit is the Watt [ W].

Q = vrms irms sin ()

(1.6)

is named reactive power, which is measured in volt-ampere reactive [ VAr] .

From (1.4) to (1.6), p(t) is not constant, since it has an oscillating component rotating
at 2. P represents an unidirectional power flow from the ac source to the load. Therefore,
it could be said that P gives a measurement of the averaged energy supplied in any time
interval from the ac source to the load.
The term associated to Q is an oscillating at 2 component and its average value
is equal to zero. Q is commonly associated as the oscillating power, since the total
energy transfered to the load over an entire cycle is zero. For this reason, Q is commonly
associated to a parasitic or non desired effect.
The apparent power S is defined as:

S = vrms irms .

(1.7)

The unit of S is the Volt-Ampere [ VA] .

The power factor (PF) is defined as cos (), which is obtained as:

cos () =

P
.
S

(1.8)

The physical meaning of S is clear from (1.7) and (1.8). S represents the maximum
reachable active power P at unity power factor.
A PF of one, or unity power factor, is the goal of any electric utility company, since,
if the power factor is less than one, they have to supply more current to the user for a
given amount of power consumption. In so doing, they incur more line losses. They also
must have larger capacity equipment in place than would be otherwise necessary. As a
result, an industrial facility will be charged a penalty if its PF is much different from 1.

Chapter 1 Introduction

The scheme of Fig. 1.1 has been simulated in the time domain through PSPICE in
order to supply the waveforms shown in Fig. 1.2. The linear load is form of a resistor in
series with an inductance with a XL /R = 0.6/0.8 ratio, which results in 36 deg (XL
is the inductance impedance at ). The values of the components have been arranged so
rms values of v(t) and i(t) are 1 p.u..
The above figures show both v(t) and i(t) and the time delay 2 ms associated to .
The figure below shows p(t) and its average value P . As expected, P = V I cos() = 0.8 p.u..
In some points of time, p(t) is negative, which corresponds with an instantaneous power
flow from the load to the source. However, the area highlighted with A, corresponding
with a positive power flow from the source to the load, is higher than the area highlighted
with B, corresponding with the flow from the load to the source. By inspection of (1.4)
it is clear that a higher weight of the inductance (XL ) in the load results in a higher B
area, which means a higher Q. If there was no resistive component would be equal to
90 deg, and hence, area B and area A would be the same; Q would be maximum and
P = 0. The sign of Q depends on the kind of load: inductive load ( > 0) results in a
positive Q and a capacitive load ( < 0) results in a negative Q.

1.2.1.1

Electrical Variables with Phasor Notation

A powerful tool in the analysis of power systems is the use of the so-called phasor notation instead of analytical expressions in the time domain. The phasor notation approach
is detailed as follows.
Any sinusoidal time function (f (t)) rotating at an angular frequency can be represented as the real part of a complex number:

f (t) = A cos (t + ) = <{A ei(t+) } = <{A ejt ej }.

(1.9)

Assuming steady-state and known frequency, f (t) can be represented by the complex
number F :

F = A ej = A.

(1.10)

A voltage phasor v and a current phasor i can be represented by complex numbers

both in polar and Cartesian notation:

V = vmax v = vmax cos (v ) + j vmax sin (v )

I = imax i = imax cos (i ) + j imax sin (i ).

(1.11)

1.2 Background on Electric Power Definitions

1.41
1

0.5

-0.5

-1

-1.5

0.04

0.045

0.05

0.055

0.04

0.045

0.05

0.055

0.06 0.062 0.065

0.07

0.075

0.065

0.07

0.075

0.08

1.5

0.8
0.5

0.06

0.08

Figure 1.2: Waveforms associated to power concepts in a linear single-phase circuit.

Chapter 1 Introduction

V&

I&

= 36

(a) Voltage and current phasor representation for

Fig. 1.2.

jQ

= 36

(b) Graphical representation of the

complex power for Fig. 1.2.

Figure 1.3: Voltage/current and Power phasors for Fig. 1.2 example.

Usually, the phase-angle of one variable, (e.g. t + v ) is chosen to be zero, so the

phasor diagram could be represented as function of a relative angle (e.g. ).
Fig. 1.3a shows the phasor notation for the example depicted in Fig. 1.2. As in the
time domain representation, the current lags the voltage, since there is an inductive load.
The phasor notation can be extended to the power definitions. The complex apparent
power S is defined as the product of the voltage and current phasors:

S = V I = vmax imax cos () + jvmax imax sin () = P + jQ.

(1.12)

S can be depicted in the complex plane as function of P , Q and PF. Fig. 1.3b shows
this complex power representation for the Fig. 1.2 example. The sign of the reactive
power is positive because of the inductive behavior of the load. A negative Q would refer
to a capacitive reactive part of the load.

1.2.2

Power Definitions under Non-Sinusoidal Conditions

When the system voltages and currents contain components of non fundamental frequency, it is said that there is distortion. The origin of this distortion can be in the origin
or in the consumer (non-linear loads).
The assessment of power definitions under distorted conditions is not a trivial task
at all. Two different theories have been provided: the power definitions based on the
frequency domain, proposed by Budeanu [4], and the power definitions in the time domain
by Fryze [5].

1.2 Background on Electric Power Definitions

There is so much discussion concerning which one of that strategies is more suitable
for the control of power converters. For example, Czarnecki proved that some of the
Budeanu definitions do not have physical meaning [6]. Moreover, there are quite a lot
difficulties with frequency domain power definitions applied to three-phase and four-wire
systems [3].

1.2.2.1

Power Definitions in the Frequency Domain by Budeanu

A set of power definitions set by Budeanu [4] is still very useful for the analysis of
power systems in the frequency domain. These definitions are valid for generic currents
and voltages in steady-state. However, they are not suitable to analyze transients.
A periodic ac single-phase wave, as voltages and currents, can be decomposed in a
Fourier series. Then, the corresponding phasor for each harmonic can be calculated. The
Budeanu definitions are:

1.2.2.1.1

Apparent Power S:
S = vrms irms ,

(1.13)

where vrms and irms are voltage and current rms values These rms values can be calculated
as function of each hth (h = 1, 2, ...) order harmonic component:

vrms =

irms =

u1 X
1ZT 2
v (t)dt = t
v2
T 0
T h=1 rmsh
v

u1 X
1ZT 2
i (t)dt = t
i2
T 0
T h=1 rmsh

(1.14)

where vrmsh and irmsh are the rms values of each harmonic component, and T the fundamental component period.

1.2.2.1.2

Active Power P :
P =

X
h=1

Ph =

vrmsh irmsh cos (h ),

(1.15)

h=1

where the displacement angle of each pair of hth order harmonic voltage and current
components is represented as h .

Chapter 1 Introduction

1.2.2.1.3

Reactive Power Q:
Q=

Qh =

h=1

vrmsh irmsh sin (h )

(1.16)

h=1

This Q definition tried to quantify the amount of power that does not realize work
in steady-state. However, this per-component approach does not take into account other
interactions such as cross products between voltages and currents at different frequencies.
For this reason, Budeanu also defined the distortion power D to quantify the loss of power
quality due to harmonic distortion:

1.2.2.1.4

Distortion Power D
D=

S 2 P 2 Q2 .

(1.17)

The physical meaning of P is clear, since it represents the average value of the instantaneous power p(t), that is, the average ratio of energy transfered between two systems.
However, both Q and D are just mathematical expressions without a clear physical meaning. Another drawback of Budeanus approach is its poor applicability in practical cases
of power quality assessment [3]. Other definitions by Budeanu are:

1.2.2.1.5

Power Factor
=

1.2.2.1.6

P
.
S

Displacement Factor cos ()

P
.
+ Q2

(1.19)

P 2 + Q2
.
S

(1.20)

cos () =

1.2.2.1.7

(1.18)

P2

Distortion Factor cos()

cos () =

The following relation is valid

P
= cos () cos ().
S

(1.21)

1.2 Background on Electric Power Definitions

1.2.2.2

Power Definition in the Time Domain by Fryze

The main definition for power components in the time domain have been presented
by Fryze:

1.2.2.2.1

Active Power Pw
1ZT
1ZT
p(t) =
v(t) i(t) = vrms iw = vw irms .
Pw =
T 0
T 0

(1.22)

where vrms and irms are voltage and current rms values, and vw and iw are the active
voltage and active current defined below.

1.2.2.2.2

Apparent Power Ps
Ps = vrms irms .

1.2.2.2.3

Active Power Factor

=

1.2.2.2.4

(1.23)

Pw
.
Ps

(1.24)

Reactive Power
Pq =

Ps2 Pw2 = vq irms = vrms iq .

(1.25)

where vq and iq are the reactive voltage and current defined below.

1.2.2.2.5

Reactive Power Factor q

q =

1.2.2.2.6

1 2 .

(1.26)

Active Voltage vw and Active Current iw

vw = vrms
iw = irms .

(1.27)

10

Chapter 1 Introduction

1.2.2.2.7

Reactive Voltage vq and Reactive Current iq

vq = q vrms
iq = q irms .

1.2.3

(1.28)

Power Definitions in Three-Phase Systems

The extension of the power definitions from a single-phase to a three-phase systems

is not a trivial task. Any three-phase system could have some properties not present in
single-phase systems:

The presence of a fourth wire: if a three-phase system is grounded in more than one
point there is an additional path for current circulation. In other systems, a fourth
wire connected to the neutral is presented.
Balance/Unbalance among phases: this feature refers to a set of three-phase voltages
(or currents). If their amplitudes are the same and the displacement angles between
the phase is 2/3 the system is balanced. If not, the system is unbalanced.

1.2.3.1

Power in Balanced Three-phase Systems

Considering a balanced system of voltages and currents:

ib

va

vb

vc

2 vrms sin(t + v )

2 vrms sin(t + v

2 vrms sin(t + v +

2
)
3
2
)
3

(1.29)

and

ia
ic

2 irms sin (t + i )
i

2 irms sin (t +

2 irms sin (t + i +

2
)
3
2
)
3

(1.30)

For a three-phase system the instantaneous active power p3 (t) describing the energy
flow per time unit transfered between two systems is given by:

p3 (t) = va (t)ia (t) + vb (t)ib (t) + vc (t)ic (t) = pa (t) + pb (t) + pc (t).

(1.31)

11

1.2 Background on Electric Power Definitions

Substituting (1.29) and (1.30) in (1.29): (1.29) and (1.30) in (1.29):

p3 (t) = 3 vrms irms cos v i = 3P.

(1.32)

Equation (1.32) shows the different behavior with respect to single-phase systems:
p3 (t) is constant and does not have a second harmonic oscillating term. This constant
component defines the active power (P3 ), which is three times the single-phase active
power.
The three-phase apparent power (S3 ) is:

S3 (t) = 3S = 3 varms iarms ,

(1.33)

so S3 is also three times the single-phase apparent power.

The definition of three-phase reactive power (Q3 ) is:

Q3 (t) = 3 varms iarms sin(v1 i ) = 3Q.

(1.34)

However, Q3 does not have the same physical meaning that the reactive power has
in single-phase systems. In fact, a balanced three-phase system feeding a three-phase
balanced load does not cause power oscillations [3].

1.2.3.2

Analysis under Unbalanced Conditions

The traditional concepts of apparent power and reactive power are not suitable for
unbalanced three-phase systems. As example, in an unbalanced system the fact that
the line currents are proportional to system voltages does not assure maximum average
(active) power transfer between systems [3].
Based on rms values of voltages and currents, two different definitions of apparent
power have been proposed:

1.2.3.2.1

Per-phase Calculation:
S3 =

X
k

Sk =

X
k

Vk Ik ,

k = (a, b, c).

(1.35)

12

Chapter 1 Introduction

1.2.3.2.2

Aggregate rms Value Calculation:

SP =

sX
k

Vk2

sX

Ik2 ,

k = (a, b, c).

(1.36)

It has been proved that under unbalanced and distorted conditions SP S3 . SP

have been used by some authors as the maximum reachable active power at unity power
factor [7].
However, the physical meaning of these definitions is not universally accepted, and
some authors state that they are only mathematical expressions. For example, Akagi
et al only consider the instantaneous active power as universal concept in three-phase
systems [3].

1.2.3.3

Power Definitions and Alternatives in Power Electronic Converters

Control

Power definitions are employed in the control of power converters, specially in power
line conditioners [3, 810], since Akagi et al presented their instantaneous active power
theory [11]. However, dealing with power magnitudes in real-time has some drawbacks,
specially in three-phase and four-wires systems [3, 12].
As an alternative to instantaneous reactive power theory, Bhattacharya et al proposed the synchronous reference frame (SRF) theory, in which specific voltage/currents
components/sequences to compensate are extracted by digital signal processing [1216].
Equivalent SRF approaches for single-phase systems were proposed in the literature [17
19]. Nowadays, with the suitability of powerful digital devices and the advance in the
state-of-art in digital signal processing, working directly with voltages/currents is a very
widespread option.

1.3

Background on Symmetrical Components

One fundamental theory in the analysis of multi-phase system is the symmetrical

components decomposition discovered by Fortescue [20]. The theory of symmetrical components allows to handle with sequences instead of independently per-phase.
From direct application to a three-phase system of the brilliant analysis by Fortescue,
any unbalanced three-phase system of voltages/currents (V a , V b , V c ) can be represented by
other three phasors: a positive-sequence phasor V + , a negative-sequence phasor V and a

13

1.3 Background on Symmetrical Components

vbmax
ab

bc

vc

vcmax

Positive Sequence

va max vb max vcmax

ab bc ca

va

vabc 0

120 va +
120
vc -

Negative Sequence

Zero Sequence

va max =vb max= vc-max

va 0max =vb 0max= vc0max

+
max =vb max= vc max
+

vb -

120 va +
+ 120
120

= 120

vamax

ca

vb +

(a) Phasor diagram of an unbalanced system.

Va
Vb
Vc
0.46

0.47

0.48

0.49

0.5

Negative-sequence

0.15

0.5

0.08

0.1
0.05

-0.05

-0.5

-0.5

-1
0.45

Amplitude (p.u.)

Amplitude (p.u.)

0.5

Positive-sequence

Amplitude (p.u.)

Amplitude (p.u.)

Three-Phase Unbalanced system

-1
0.45

Time (s)

Va+
Vb+
Vc+
0.46

0.47

0.48

0.49

VaVbVc-

-0.1

0.5

0.45

0.46

0.47

0.48

0.49

0.06
0.04
0.02
0
-0.02
-0.04

Va0
Vb0
Vc0

-0.06
0.5

Time (s)

Time (s)

Zero-sequence

-0.08
0.45

0.46

0.47

0.48

0.49

0.5

Time (s)

(b) Time domain decomposition.

Figure 1.4: Example of decomposition of an unbalanced three-phase set of fundamental

voltages/currents.
zero-sequence phasor V 0 [21]. The Fortescue transformation by means of the S matrix is:

V 0
1 1 1

1
+

V = 1 a a2

3
V
1 a2 a
|

{z
S

V a

,
V b

V c

(1.37)

where a is a complex number also called Fortescue operator:

j(2/3)

a = 1120 deg = e

1
3
=
+j
.
2
2

(1.38)

Fig. 1.4a shows an example of decomposition of an unbalanced three-system of voltages (vabc = [va , vb , vc ]) in a balanced system rotating at () which is the positivesequence (V + ) plus a balanced system rotating at () which is the negative-sequence
(V ) plus a zero-sequence (V 0 ). Fig. 1.4 shows the equivalent time domain vectors:

+
0
vabc
= [va+ , vb+ , vc+ ], vabc
= [va , vb , vc ] and vabc
= [va0 , vb0 , vc0 ]. The superscripts +,
and 0 refer to positive, negative and zero sequences, respectively. The superscript 1
refer to the fundamental component: e.g. 1 is the fundamental frequency.

14

Chapter 1 Introduction

The real time implementation of S is approached in some works; the imaginary unit
j is implemented by means of digital filters with a 90 deg delay at 1 [22]. However, this
approach have some limitations, as shown in chapter 2.
Clarke and Park transformations [23, 24], also based on the symmetrical components
theory, offer a much higher versatility, specially for real-time implementations such as
power converter controllers, monitoring systems, etc.
The Clarke transform C converts a three-phase system vabc to an equivalent two-phase
system v :

{z

va

2 1 0.5 0.5

vb ,

3
3

3 0
2
2
vc
|
{z
}
C

{z

vabc

(1.39)

where v and v are two orthogonal waves rotating at the same frequency that vabc , which
have information of both positive and negative sequences; zero-sequences do not appear
in v [21]. The Clarke transformation is employed in several controllers such as the ones
implementing the Space Vector Modulation (SVM) technique [16, 25]. It is also widely
employed in grid synchronization.
Real-time implementation of Park transformations allow to decouple positive from
negative sequences, since they are moved to different frequencies, including dc. In fact,
the possibility of dealing with oscillating waves as dc values is the most interesting feature
of the Park transformations. The most widely employed Park transformation is the P+
matrix to decouple the positive-sequence. Considering an input vector of voltages as
+
(1.29), but with only positive-sequence, vabc
rotating at , a vector of two dc components
+
(vdq
) is obtained as follows:

vd+

vq+

{z

v+
dq

va+

) sin( + 2
)
2 sin() sin( 2
3
3

vb+

3 cos() cos( 2 ) cos( + 2 )

3
3
vc+
|
{z
}
P+

{z

vabc

(1.40)

where =
t+, being an offset constant. When referring to (1.40) implementation,
it is usually said that vabc is transformed to the synchronous reference frame (SRF) stated
by . Fig. 1.5 shows the graphical representation of vabc in the SRF established by .

In (1.40) negative-sequence rotating at is not considered to recall the fact that

positive-sequence components are moved to dc. However, it should be known that

P+ vabc
results in a vector whose components rotate at 2 [26]. On the other hand, any
other sequence (positive or negative), rotating at 0 not equal to , results in components

15

1.3 Background on Symmetrical Components

vq+

v dq

vd+

Figure 1.5: vabc in the SRF established by .

of frequency 0 1 and + 0 [27]. For this reason, Park transformations used to
be implemented together with low pass filters or Proportional Integrator (PI) controllers
[1216].
The Park transformation for negative-sequence (P ) is also implemented, specially in
power line conditioners dealing with unbalance [26].

P =

sin () sin ( +

2
3 cos () cos ( +

2
)
3
2
)
3

sin (
cos (

2
)
3
2
)
3

(1.41)

where =
t + . Through P the negative-sequence rotating at are transformed to dc components and other sequences are moved to different frequencies. When
representing sequences in the SRF of P , the sense of rotation is clock-wise.

0
Regarding to zero-sequences of any frequency, it should be noticed that P vabc
=0

0
and P vabc = 0. Therefore, zero-sequences are neglected when working with SRF based
approaches.

In this section, P+ and P have been defined for a generic frequency (). However,
it should be noticed that electric power applications usually deal with signals containing
sequences (positive and/or negative) of more than one frequency: a fundamental component rotating at fundamental frequency and its harmonics components. Starting from
this point, the subscript 1 is also added both to P+ and P to refer to the fundamental
component and subscripts h, where h = 2, 3, 4, 5, ... to harmonic components. E.g. P+
1
refers to the Park transformation for the fundamental positive-frequency.
1

Negative frequencies implies a change in the kind of sequence (e.g. from negative to positive).

16

Chapter 1 Introduction

1.3.1

Alternatives in Implementation

It is common to find some of these transformations expressed in a different

way or
q
+
with different constants, as the so-called constant power P which uses 3/2 instead of
2/3 [25]. In this work, the constants have been chosen so the amplitude of the vectors
involved is kept constant, since amplitudes could be also estimated by synchronization
algorithms.
On the other hand, the Park transformation can be considered as the combination of
the Clarke transformation and the so-called angle transformations B+ and B [21]:

B+ =

B =

cos ()

sin ()

sin () cos ()

cos() sin()
sin()

cos()

(1.42)

(1.43)

So

P+ = B+ C =

cos()

2
)
3
2
)
3

cos(

2
3 sin() sin(

2
)
3
+ 2
)
3

cos( +
sin(

(1.44)

and

)
cos( 2
)
cos()
cos( + 2
2
3
3
.
P = B C =
3 sin() sin( + 2 ) sin( 2 )
3
3

(1.45)

Apparently, Park transformations (1.40) and (1.41) could seem different from (1.44)
and (1.45). However, they are totally equivalent, the difference is in how to express the
vabc vector, either as cosine waves [24, 28] or as sine waves [29, 30]. Anyway, both
approaches lead to the same final results and equivalent intermediate analysis.

1.4

Background on Power Quality

As stated in [31], the term power quality refers to a wide variety of electromagnetic
phenomena that characterize the voltage and current at a given time and location on

1.4 Background on Power Quality

17

the power system. This section summarizes the terminology to describe the most common events. location on the power system. This section summarizes the terminology to
describe the most common events.

1.4.1

Transients

It refers to very short duration undesirable events in the voltages, currents or power in
an electric circuit. Depending on the wave-shape of the transient, there are two categories
of transients:

1.4.1.1

Impulsive Transient

It is a sudden, non-power frequency change in the steady-state condition of voltage/current, that is unidirectional polarity. It is characterized by the rise and decay
times. The most common cause of impulsive transients is lighting. Due to the high frequencies involved, impulsive transients are damped quickly by resistive circuit components
and are not conduced far from their source.

1.4.1.2

Oscillatory Transients

An oscillatory transient is a voltage/current whose instantaneous values change polarity rapidly. It is described by its predominant frequency, duration and magnitude.
Power electronics devices produce oscillatory voltage transients as a result of commutation and RLC snubbers. They are in the high kHz range and last only a few cycles of
that frequency.
Back to back capacitor energization gives rise to current oscillatory transients in the
tens of kHz.
Low frequency oscillatory transients (< 5 kHz) are present both in sub-transmission
and distribution systems mainly due to capacitor bank and transformers energization.

1.4.2

Short-duration Variations

They last more than transients: between 0.5 cycles of the fundamental frequency
(50 or 60 Hz) and 1 minute. They are mainly caused by fault conditions, energization
of large loads and intermittent loose connections in power wiring. These faults could

18

Chapter 1 Introduction

result in voltage rises (swells), voltage drops (sags) and even a complete loss of voltage
(interruptions).

1.4.2.1

Interruptions

It occurs when the supply voltage/current decreases to below 0.1 p.u.. The causes of
interruptions are power system faults, equipment failures and control malfunctions.

1.4.2.2

Sags (Dips)

As said, the term sag refers to a voltage drop. They are characterized by their magnitude and duration. The terminology recommended by [31] to refer to voltage sags is a
sag to 20 %, which means that the line voltage is reduced to a 20%.
The main causes of sags are power system faults, switching of heavy loads or starting
of large motors. A very detailed work about kind of sags and causes is shown in [32].

1.4.2.3

Swells

It is an increase on the rms voltage or current at the nominal frequency. They are
also associated with system fault conditions but they are much less common than sags.
They are characterized by their magnitude and duration. Typical magnitudes are in the
range 1.1 p.u. and 1.8 p.u..

1.4.3

Long Duration Variations

Long duration variations are rms deviations lasting for more than 1 minute. They
can be either over-voltages and under-voltages, depending on the cause of the variations.
They are caused by load variations on the system and switching operations. They are
characterized by plots voltage versus time.

1.4.3.1

Over-Voltage

Over-voltages may be result of load switching (e.g. switching off a large load) or
variations in the reactive compensations of a power system (e.g. switching on a capacitor
bank). Poor system voltage regulation capabilities or controls result in over-voltages.

1.4 Background on Power Quality

1.4.3.2

19

Under-Voltage

Their causes are the opposite to over-voltage ones: e.g. a big load switching on or a
capacitor bank switching off. Overloaded circuits may lead to under-voltage, too.

1.4.3.3

Sustained Interruptions

A decrease to zero of the supply voltage for a period of time longer than 1 minute
is a sustained interruptions. They are often permanent in nature and require manual
intervention to restoration.

1.4.4

Voltage Imbalance

Voltage imbalance or unbalance is defined as the ratio of the negative or zero sequence
component to the positive-sequence component. They main causes of these zero and negative sequences are unbalanced loads causing which results in a flow of zero and negative
sequence currents.
Imbalance is estimated (expressed as %) using the expression:

voltage imbalance =

maximum deviation f rom average voltage

100%.
average voltage

(1.46)

The main source of smooth voltage imbalance (less than 2%) is the single-phase loads
(unbalanced by definition) in three-phase circuits. Severe voltage imbalances (greater
than 5%) can result from single-phasing conditions.

1.4.5

Waveform Distortion

Waveform distortion is steady-state deviation from the ideal sinusoidal wave of fundamental frequency. It is well characterized by the spectral content. They are five primary
types of waveform distortion:

1.4.5.1

Dc Offset

It is the presence of a dc voltage or current in an ac power system. Geomagnetic

disturbances and effects of half-wave rectification may lead to dc offset. Direct current in

20

Chapter 1 Introduction

ac systems has some damaging effects such as an increase in the transformer saturation,
additional stressing of insulation and others.

1.4.5.2

Harmonics

Harmonics are sinusoidal voltages or currents having frequencies that are integer multiples of the fundamental (50 or 60 Hz). Harmonics combine with the fundamental voltage
or current, and produce distortion.
The cause of harmonics is the non-linearity of devices and loads which produce current
harmonics. These current harmonic also produces voltage harmonics because of the voltage drops in the power system impedances. Harmonic distortion is a growing concern for
many customers and for the overall power system due to increasing application of power
electronics equipment.
Harmonic distortion levels can be characterized by the complete harmonic spectrum
(magnitudes and phases). It is also common to use to use the total harmonic distortion
(THD) [33]:

T HD =

sum of all squares of amplitude of all wave harmonics

100% =
square of the amplitude of the f undamental component

qP

h=2 Vh

V1

1.4.5.3

(1.47)

100%.

Inter-Harmonics

Inter-harmonics are voltage or current components with a frequency that is a nonintegral multiple of the fundamental frequency. They can appear as discrete frequencies
or as a wide-band spectrum. The main sources of inter-harmonics are static frequency
converters, cyclo-converters, induction motors and arcing devices. Their effects are still
not well studied, but it is known that they produce visual flicker in display devices and
also affect to power line carrier signaling. Inter-harmonics are harmonic components at
non multiple

1.4.5.4

Notching

It is a periodic voltage disturbance caused by the normal operation of power electronics devices when there is commutation. Since notching occurs continuously it can
be characterized through the frequency spectrum; however, typical notching frequencies

1.4 Background on Power Quality

21

are high and therefore difficult to measure accurately with normal equipment. As shown
in the next chapter, notching can cause severe faults in power electronics converters for
which the control algorithm uses zero-cross detection circuits.

1.4.5.5

Noise

Noise is unwanted electrical signals with broadband spectral content lower than 200 kHz
superimposed over the power system voltages or currents. It is caused by power electronics
devices, control circuits, arcing equipment, non-linear loads and switching power supplies.
Noise phenomena is also very related with grounding. Basically, noise is any unwanted
distortion that cannot be classified as harmonics or transient.

1.4.6

Voltage Fluctuations

Voltage fluctuations are systematic variations of the voltage envelope for which the
voltage range does not exceed the range 0.95 1.05 p.u..
Any load with continuous and significant current variations, specially in the reactive
components, may cause voltage fluctuations. Arc furnaces are the most common cause of
voltage variations on the transmission and distribution systems. Voltage fluctuations are
defined by their rms magnitude expressed as a percent of the fundamental.

1.4.7

Power Frequency Variations

The power system frequency is directly related to the rotational speed of the generators
on the power system. At any instant, the frequency depends on the balance between
the load and the generation. When this dynamic balance changes, small changes in
frequency occur. The size of the frequency variations 2 and its duration depends on the
load characteristics and the response of the generation system to load changes.
Frequency deviations outside accepted limits for normal steady-state operation can
be caused by faults on the bulk power transmission system, a disconnection of a large
load or a disconnection of a large source of generation. Frequency variation affecting to
equipment also appear in systems powered by isolated generators.
2

The term power frequency deviations is also employed.

22

Chapter 1 Introduction

1.5

Power Electronic Converters and Applications

This section dealts with power electronic converters connected to an ac mains 3 . The
main devices, architectures, and applications are summarized in this section. A special
emphasis is put in the importance of synchronization and extraction algorithms in their
controllers.

1.5.1

Thyristor Converters

The thyristor is one of the most important types of power semiconductor devices. It
is suitable for circuits where high currents and voltages are involved. It is a four-layer
semiconductor device with three pn-juntions and three terminals: anode, cathode and
gate.
When the anode voltage is positive with respect to the cathode voltage the thyristor is
said to be in off-state condition. It can be turned on by applying a positive voltage between
gate and cathode. When the thyristor is turned on, it goes on conducting while the anode
to cathode current is above the so-called holding current; there is no influence of the gate
signal during the on-state. When the anode to cathode voltage is negative, the thyristor
behaves like a reverse biased diode: there is not current through them (independently of
the gate signal).
Even though the thyristor characteristics show that it is a semi-controlled device, it
can be assumed as ideal switch for many applications such as the thyristor rectifiers.
A rectifier is a power circuit which convert ac input power to dc output power. A
thyristor rectifier uses thyristor as switches. With respect to diode rectifiers, a thyristor
rectifier allows to control the output voltage, that is the power flow from the ac side to
the dc side, by controlling the firing instants of the thyristors gate.

1.5.1.1

Three-phase Full Rectifier

Fig. 1.6 shows a 6-pulse thyristor full rectifier with linear load (zL ). The average
current through the transmission cable (idc ) directly depends on the average voltage across
the dc side terminals (
vdc ). The active power in the dc bus is Pdc = vdc idc .
A balanced set of input voltages can be expressed as function of the line-to-line voltage
3

Even though dc-dc conversion is a very important branch of power electronics, it is approached neither
in this section nor in this Ph.D. dissertation.

23
Mercury-Arc
base
Power Electronics

1.5 Power Electronic Converters and Applications

va

Ls

vb

Ls

vc

Ls

S1

S3

idc

S5

AC
Side

vdc
zL

S2

S4

S6

3 Phase
AC
Source

Figure 1.6: 6-pulse thyristor based rectifier.

vllmax as:
vll
vll
va = max sin(1 t) = max sin(1 )
3
3
vllmax
2
)
vb = sin(1
3
3
vll
2
vc = max sin(1 +
),
3
3

(1.48)

where 1 = 1 dt is the phase-angle oscillating at 1 (1 = 0).

In normal operation, one upper and one lower thyristor of different branches are conducing. Hence, The total number of combinations, or states, is 6. The notation used to
show in which state is the rectifier is Sij , where i refers to the upper branch and j the
lower branch. For example, the state Sab refers to thyristor T 1 and T 4 conducing.
The switch between states is set by the firing of the thyristor. The normal operation
sequence is Scb Sab Sac Sbc Sba Sca Scb Sab ... and so on.
From (1.48), va is the highest of the three in the range [30, 150] deg, vb in the range
[150, 270] deg and vc in the range [270, 390 (30)] deg. Moreover, va is the lowest of the
three in the range [210, 330] deg, vb in the range [330, 450 (90)] deg and vc in the range
[90, 210] deg.
If diodes are used instead of thyristor, the switching time are not controlled: each
diode starts conducting when its anode to cathode voltage is positive. Table 1.1 shows
the state dependence with respect to the line phase-angle.
However, if thyristors are used, their conduction could be delayed by choosing the
desired firing angle, named ; the angle can be set in the range 0 deg < < 180 deg,

24

Chapter 1 Introduction
Table 1.1
States of diode full rectifier depending of 1 .

Range of 1

State

[0, 30] deg

Scb

[30, 90] deg

Sab

[90, 150] deg

Sac

[150, 210] deg

Sbc

[210, 270] deg

Sba

[270, 330] deg

Sca

[330, 360] deg

Scb

Table 1.2
State of controlled rectifier depending of 1 and .

Range of 1

State

[0 + , 30 + ] deg

Scb

[30 + , 90 + ] deg

Sab

[90 + , 150 + ] deg

Sac

[150 + , 210 + ] deg

Sbc

[210 + , 270 + ] deg

Sba

[270 + , 330 + ] deg

Sca

[330 + , 360 + ] deg

Scb

that is when the thyristors anode to cathode voltage is positive. The switching times as
function of are the shown in table 1.2.
vdc can be expressed as function of and vllmax :
Z +pi/6
1 Z
3
vdc = [
vc vb +
va vb + ....] = vllmax cos ().
T 0

(1.49)

As expected, the maximum value of vdc corresponds with diode operation, that is
= 0 deg. The average current idc depends on vdc and the resistive component of zf
(zf ( = 0)):

idc =

vdc
.
zf ( = 0)

(1.50)

The operation of the rectifier is not linear: vdc has ripple components over vdc . This

25

1.5 Power Electronic Converters and Applications

vdc

=0 deg.

=90 deg.

idc

=180 deg.

Figure 1.7: Working points of the thyristor full wave rectifier.

ripple is composed of even harmonic components and also affects to idc . Therefore, this
rectifier is producing reactive power for any .
Fig. 1.8 shows the rectifier working in different points. The firing instant are the
points where the switching state changes are highlighted as discontinuous lines. It is clear
the non-linear behavior of this converter and its inherent reactive power consumption for
any zf . The ripple is higher as lower is the module of vdc .

1.5.1.2

Applications of Thyristor Converters

Nowadays, with the suitability of better controllable switching devices, the use of
thyristors is in three-phase and high-power applications.

1.5.1.2.1 High Voltage dc Transmission Electrical plants generate power in the

form of ac voltages and currents. This power is transmitted to the load centers on threephase ac transmission lines. However, for a given quantity of power transmitted, specially
over long distances, dc transmission is more efficient [34].
Fig. 1.9 shows a simple scheme of a HVDC. In order to minimize the losses in the
transmission line due to parasitic reactances the origin ac voltages are transformed into
high dc voltages. A power converter working as rectifier to convert the origin ac signal
to dc is employed. Another power converter is placed in the destination point to convert
the dc voltage to ac (inverter).

26

Chapter 1 Introduction

(a) Three-phase rectifier working at = 0 deg (Diode mode).

0.8

0.6

0.4

0.2

-0.2

-0.4

-0.6

Scb

Sab

-0.8
1.955

Sbc

Sac
1.965

Sba

1.97

Sca

Scb

1.975

(b) Three-phase rectifier working at = 30 deg.

=30 deg.
0.6

0.4

0.2

-0.2

-0.4

-0.6

Sbc

Sba

Sca

Scb

Sac

Sab

Sbc

Sba

-1
1.95

1.955

1.965

1.97

1.975

(c) Three-phase =120

rectifier
deg. working at = 120 deg.

Figure 1.8: Steady-state voltages of the thyristor three-phase full rectifier.

27

1.5 Power Electronic Converters and Applications

idc

Origin ac System

Destination ac System

Rectifier

Inverter

Figure 1.9: Simple HVDC diagram.

Ldc
ac

dc
ac
Motor
Rectifier

Inverter

Figure 1.10: ac Motor controlled with Thyristor-based inverter and rectifier.

VAC

AC Voltage Sensor

PLL

1meas

1.5.1.2.2 Flexible ac Transmission Systems A Flexible Alternating Current Trans ref

Main
Order
mission System (FACTS) is a power electronic based system and other static equipment
Control
that provide control of one or more ac transmission system parameters to enhance controllability and increase power transfer capability [35]. Thyristor based devices are a very
important part of the FACTS family.
Static VAR Compensators (SVC) provide fast-acting reactive power compensation on
high-voltage electricity transmission networks: Thyristor Controlled Reactors (TCR), and
Thyristor Switched Capacitors (TSC) are shunt-connected devices controlled with thyristor which absorb/provide reactive power. SVCs are used both on bulk power transmission
circuits to regulate voltage and contribute to steady-state stability; they also are useful
when placed near high and rapidly varying loads, such as arc furnaces.
There are also series devices such as Thyristor Controlled Series Capacitors (TCSC),
Thyristor Controlled Series Reactances (TCSR), etc citeHingorani2000.

1.5.1.2.3 Ac Motor Drives Induction motors with squirrel cage rotors are very suitable for industry because of their low cost and robustness. When operated from the line
voltage as input, they work at constant speed and torque. However, by means of power
electronics converters, it is possible to control speed, torque and even position.
Fig. 1.10 shows a scheme used for the speed control of an ac induction motor using two
thyristor converter, one as rectifier and another one as inverter. This scheme is employed
in very large power rating applications, where a very fast dynamic response is not needed.

28

Chapter 1 Introduction

The rectifier converter controls the dc voltage, and the inverter controls the ac voltage
in the input of the ac motor. Varying this ac input voltage, the point of operation of the
motor (speed and torque) is controlled.

1.5.2

Pulse-Width-Modulated Converters

Pulse Width Modulation (PWM) is the more widespread technique to set both the on
and off firing signals of power converter switches.
The use of thyristors in PWM converters requires a forced commutation scheme. However, there are some other devices, which allow a better on-off switching control and are
suitable from lower to medium-high power rated applications: Insulated Gate Bipolar
Transistors (IGBTs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs),
Bipolar Junction Transistors (BJTs), etc. The main advantage of these devices with respect to Thyristor is the fact that they are bidirectional in current. However, they only
block voltage in one way (unidirectional in voltage).
In general, PWM converters are suitable to work in four quadrant operation under the
power flow point of view. Owing to this flexibility, PWM power converters are employed
in vast range of applications.

1.5.2.1

Overview of Modulation Techniques

A brief explanation of PWM operation is shown in this section. Lets suppose the
one-leg switch inverter of Fig 1.11. Ideal switches are considered instead of real power
electronic devices (S+ and S ). Each switch has a control signal, which set if the switch
is in conducting (on state, boolean 1) or not (off state, boolean 0). Only one switch per
phase can be in on state, else the dc link would be short-circuited. The instantaneous
value of the voltage in the point a (va ) depends on which switch is on: vdc /2 or vdc /2.
The rate of commutation for the switches sets the switching frequency (fs ). The maximum
value of fs is limited by the real devices (e.g. around 20 kHz for IGBTs). The average
value of va , averaged each commutation cycle, defined as va will depend on the time each
switch in on. The duty cycle (d) is defined as the ration of time per commutation cycle
the switch is on per total commutation cycle. So:

va = d

vdc
vdc
+ (1 d)
.
2
2

(1.51)

Therefore setting d for each commutation cycle accordingly, the output voltage in a
can be controlled in real time. Equation 1.51 can also be expressed by the PWM control

29

1.5 Power Electronic Converters and Applications

vdc
-

vdc
2
vdc
2

S+

+
-

S-

+
-

van

n
Figure 1.11: One leg of a switch mode inverter.

or modulating signal (m) (1 < m < 1):

va = m

vdc
.
2

(1.52)

1.5.2.1.1 Sinusoidal PWM Sinusoidal PWM is one of the most employed technique
to generate the control signals of the power switches. An example applied to the branch
of Fig. 1.11 is provided as follows.
The firing signals of the switches are obtained by comparing a triangular wave (vtri )
of amplitude 1 and switching frequency (fs ) with a control signal m. The switching rules
are:

vdc
2
vdc
ON va =
.
2

m > vtri S+ ON, S OF F va =

m < vtri S+ OF F, S

(1.53)

Fig. 1.12 shows the firing signal of S+ obtained with these switching rules (S is
the opposite to S+ ). m rotates at 50 Hz, a frequency much lower than vtri frequency,
fs = 10 kHz.
Using these switching rules, the va , averaged each switching cycle, is:

va = m

vdc
.
2

(1.54)

30

Chapter 1 Introduction

0.8

vtri

0.6

0.4
0.2

-0.2
-0.4
-0.6
-0.8

1.1

1.2

1.3

1.4

1.5

Figure 1.12: Set of S+ firing signal with sinusoidal PWM.

Fig. 1.13 shows the output of instantaneous and filtered va .

Fig. 1.14 shows Fourier coefficients of va . It is shown how, even though the control
signal has only a 50 Hz component, va has much more spectrum components. There are
relative high components around the switching frequency (and its harmonics), and, in
general, a continuous non-zero spectrum.
There are several modulation techniques for power electronic converters. E.g. SVM
algorithms, which result in different switching sequences and spectrum contents.

1.5.2.2

Voltage Source Converters

Voltage-source converters (VSC) with PWM modulation are, by far, the most popular
converters for ac power supplies up to a few megawatts [36]. Fig. 1.15 shows the topology
of a three-phase VSC; ei (i = a, b, c) is the per-phase output voltage of the VSC. The
average value of ei (
ei ), averaged each commutation cycle (fs ), can be set through the
PWM or SVM techniques [16, 25].
Considering only the fundamental component of each ei , the power flow between the
ac mains and the dc side of the VSC, both active and reactive, can be controlled. This is
called four quadrant operation.

31

1.5 Power Electronic Converters and Applications

0.8
0.6

0.4
0.2

-0.2

vtri

-0.4
-0.6
-0.8

0.08

0.082

0.084

0.086

0.088

0.09

0.092

0.094

0.096

0.098

0.082

0.084

0.086

0.088

0.09

0.092

0.094

0.096

0.098

vdc/2

-vdc/2

Figure 1.13: va output with sinusoidal PWM.

Figure 1.14: Fourier Components of va .

0.1

Mercury-Arc based 6-pul

Chapter 1 Introduction
Power Electronics Rectif

32

S3

S1

va

La

vb

Lb

vc

Lc

id

S5

AC
Side

ea
eb

vd
ec

S2

S6

S4

Cd
3 Phase
AC
Source

Figure 1.15: VSC connected to an ac source.

vi

ii

Li

ei

Figure 1.16: Per-phase representation of VSC connected to an ac source.

Fig. 1.16 is the per-phase representation of the VSC, where i means a, b or c phase, and
vi refers only to the supply fundamental component. The system is considered rotating
at 1 .
From Fig. 1.16 results clear that the current through Li (ii ) depends on vi and ei . In
phasor notation this can be expressed as:
V i E i
Ii =
= imax 1 ,
j1 Li

(1.55)

where V i = vmax 0 and E i = emax 1 ; 1 being the phase-angle offset between vi and ei
4
.
From power definitions:

S = 3 vrms irms
P = 3 vrms irms cos(1 )
Q = 3 vrms irms sin(1 )
4

It should be noticed that the angle references can be set with respect to V i .

(1.56)

DC
Side

33

1.5 Power Electronic Converters and Applications

=Q
Quadrant I
Quadrant II
VSC absorbs active power from the grid.
VSC supplies active power to the grid.
VSC absorbs reactive power from the grid. VSC absorbs reactive power from the grid.

=P
Region III
VSC supplies active power to the grid.
VSC supplies reactive power to the grid.

Region III
VSC absorbs active power from the grid.
VSC supplies reactive power from the grid.

Figure 1.17: Complex power diagram of grid-connected VSC.

where rms values are easily obtained from the peak values as:

vmax
vrms =
2
imax
irms = .
2

(1.57)

Therefore, by assessing emax and 1 accordingly, the energy transfer between the ac
side and dc side of the VSC can be controlled. Fig. 1.17 shows the complex plane to
represent the four quadrant operation of the VSC connected to the ac grid.
These complex power can also be represented using P and Q as axis (P Q diagram).
Fig. 1.18 shows the different operation points of the VSC connected to the ac mains. It
is clear that the VSC is a very flexible device when connected to the grid: from the point
of view of the fundamental components, it is possible to absorb and supply active power,
but also positive and negative reactive power. It is typical to refer to the VSC as Voltage
Source Inverter (VSI) when it is working suppling active power to the ac grid, that is
dc-ac conversion.
VSCs can handle components rotating at higher frequencies than 1 , e.g. harmonics.
The maximum frequency that a VSC is able to control in steady-state is related to the
controller bandwidth. Generally, it is assumed that the VSC bandwidth is the tenth (or
eleventh) part of the PWM frequency. For example, an IGBT based VSC commutating
at 10 kHz can handle with harmonics around the 20 one (1 kHz) [37, 38]. VSCs can be
connected in series, between the ac mains and another electrical system.

34

Chapter 1 Introduction
V&i

I&Lsi

E& i

V&Lsi

V&i

Lsi

I&Lsi
1

E& i
Q

E& i
1

V&i

I&Lsi

V&Lsi
Q

V&i
E& i

E& i
V&

V&i

V&i

V&Lsi

I&Lsi

V&i

I&Lsi

E& i
I&Lsi

V&Lsi

1
1

V&Lsi
V&

E& i
I&Lsi

V&Lsi

E& i

I&Lsi

V&Lsi

Figure 1.18: P Q diagram. Operation points of grid-connected VSCs.

ac

dc
ac
Motor
Rectifier

Inverter
AC Voltage Sensor

Figure 1.19: Control of induction motor by PWM-VSI with diode rectifier

1.5.2.3

Applications of PWM Converters

VAC
Order

PWM converters are employed in a vast range of applications.

PLL
Main
Control

1.5.2.3.1 Ac Motor Drives As said, VSC and other PWM converter topologies used
as inverter can control both frequency and magnitude of their outputs. On the other hand,
the speed of rotation of ac motors depends on the frequency of the stator voltage and the
torque on the magnitude. Therefore, it is possible to control both torque and speed of
an induction motor by means of, for example, a PWM converter as depicted in Fig. 1.19.
The ac line voltage is rectified by means of an uncontrolled diode rectifier and the inverter
feeds the stator with a voltage which controls its torque and rotation speed.

1.5.2.3.2 Uninterruptible ac power supplies An uninterruptible power supply

(UPS) is a device which maintains a continuous supply of electric power to connected

1meas
Comparator

ref

1.5 Power Electronic Converters and Applications

35

equipment by supplying power from a separate source when utility power is not available.
A UPS can be used to provide uninterrupted power to equipment for 120 minutes until
a generator can be turned on or utility power is restored.

1.5.2.3.3 Power Line Conditioners A power line conditioner is a device intended

to improve the quality of the power that is delivered to electrical equipment. Power line
conditioners based on PWM converters are employed to prevent power line disturbances
from disrupting the operation of critical loads (medical equipment, industrial processes,
...).
Important power line conditioners are:

Reactive power compensator [3, 11].

Power Factor Correction: a PWM converter can be placed in parallel with the rest
of loads supplying a fundamental current so the power factor from the ac source
remains around 1 [39, 40].
Active Power Filters (APF) for harmonic compensation: the PWM converter can
be placed in series or in parallel with the protected loads, to compensate for voltage
or current harmonics [8, 4145].
Dynamic Voltage Restorer (DVR): the PWM converter is placed in series with a
sensible loads so it is prevented from voltage sags [4650].
UPSs can be considered power line conditioners since they provide protection against
all common power problems [5153].

1.5.2.3.4 Flexible ac Transmission Systems Due to the ever-increasing power

rating of PWM converters they were proposed as FACTs devices [35]. The most significant
applications are

Static Synchronous Compensators (STATCOM). A STATCOM operates as a shuntconnected static var compensator whose capacitive or inductive output current can
be controlled.
Static Synchronous Series Compensators (SSSC). A SSSC operates without any
external electric energy source as a series compensator whose output voltage is in
quadrature with, and controllable independently of, the line current for the purpose
of increasing or decreasing the overall reactive voltage drop across the line and
thereby controlling the transmitted electric power. The SSSC may include energy
storage to enhance the dynamic behavior of the power system.

36

Chapter 1 Introduction
Universal Power Flow Controllers (UPFC). An UPFC is a combination of a STATCOM and a SSSC which are coupled via a common dc-link, to allow bi-directional
flow of active power between the series output terminals of the SSSC and the shunt
output terminals of the STATCOM, and are controlled to provide concurrent real
and reactive series line compensation without any external energy source.

1.6

Control of Power Electronic Converters and Synchronization

Even though analog control circuits are still being proposed and used, the clear trend
is the implementation of the control algorithms in digital devices. Current devices such as
Digital Signal Processors (DSP), Field Programmable Gate Arrays (FPGA) and Microcontrollers allow the digital implementation of controllers for power electronics converters
[5456]. Digital implementation offers quite a lot of advantages with respect to analog
circuits, above all its flexibility in the design, implementation and maintenance.
It said, the P-Q operation point of a grid-connected VSC depends on 1 . In general,
the controllers of power electronic converters implement synchronization algorithms to
assess exchanges of electrical energy. Measurements at the point of common coupling
(PCC) are made in order to estimate voltage/current absolute phase-angles (1v and/or
1i ). In this work, the estimated values have a hat: e.g. the estimated value of 1v is
expressed as 1v . Estimated values are employed to assess 1 and hence, the P-Q operation
point.
Fig. 1.20 shows a simplified scheme of dc-link voltage (vdc ) feedback controller using a
PI filter and SRFs obtained through the Park transformation (P1+ ). The phase-angle for
P1+ generation is obtained from a synchronization block (1v ). Assuming perfect tracking
(1v = 1v ) the grid current (iabc ) is in-phase with the grid voltage (vabc ), so there is only
active power flow from the PCC to the dc-link.
Dc-link voltage controllers are implemented in a wide range of applications, where
capacitors are employed as energy storage device; e.g.:
Power Line Conditioners [16, 4144].
Controlled Rectifiers with a high power factor [16, 26, 5759].
Motor Drives [60].
FACTs devices [35].
Using the values of table 1.3, the dc controller has been simulated in order to show
the role of the synchronization algorithm.

37

1.6 Control of Power Electronic Converters and Synchronization

PCC

vabc

Lr

iabc

ac
Side

Current
Sensors

dc
Side

vdc

Cdc

ZL

VSC
Firing
Signals

iabc
iq1+

ac Voltage
Sensors

vabc

P1+

iq1+*=0

SRF

Current
id1+ Regulator

id1+*

)v

Synch.

Voltage
Sensor

PI

vdc

vdc*
Digital Controller

Figure 1.20: Simplified dc-link voltage control loop of VSC.

Table 1.3
VSC based Rectifier Values.

vmax

1 p.u.

vdc

1.5 p.u.

Cdc

3 p.u. at 50 Hz

ZL (resistive)

1 p.u.

Voltage Regulator

50 Hz

Bandwidth
Current Regulator
Bandwidth

Varia
Dela

Contr
Exter
refere

38

Chapter 1 Introduction

0.5

-0.5

-1
5.01

5.02

5.03

5.04

5.06

5.07

5.08

5.09

5.1

5.01

5.02

5.03

5.04

5.06

5.07

5.08

5.09

5.1

0.5

-0.5

-1

-1.5

Figure 1.21: VSC operation in steady-state. Effect of phase-error.

Fig. 1.21 shows steady-state voltages/currents of the power system for perfect tracking
(dotted) and when there is a constant steady-state phase error (1e = 1v 1v ) of
14 deg (solid). The effect of non-zero phase-error is a displacement power factor cos(1 )
reduction, both for single-phase and three-phase systems. A cos(1 ) 6= 1 results in Q 6= 0,
so higher rated currents are needed to maintain the bus voltage at the reference value

(vdc
). Therefore, average steady state phase error (1e ) 5 should be canceled to get an
optimized real-time controller.
Fig. 1.22 shows steady-state voltages/currents when there is ripple of 2th harmonic
over the phase estimation. As shown, ripple in the measurement infers also ripple in iabc
and vdc 6 . Therefore, noise in phase estimation reduces the whole performance of the
5

Even though in PWM/SVM the average values are averaged each cycle of fs , in synchronization the
averaging is related to f1 .
6
The frequency of vdc ripple is 41 , not 21 .

39

1.6 Control of Power Electronic Converters and Synchronization

1.501
1.5008
1.5006
1.5004
1.5002

1.5
1.4998
1.4996
1.4994

1
1.4992

1.499
5.01

5.02

5.03

5.04

5.06

5.07

5.08

5.09

5.1

Figure 1.22: VSC operation in steady-state. Effect of ripple in 1 .

dc-link controller.
A comparative between a relatively fast and a slow synchronization block is provided
in Fig. 1.23. As expected, the system with a faster estimation recovers first the steady

state, and the vdc

maximum deviation from its nominal or reference value (vdc
) is minor.
This second point may be critical in some systems, since power electronic converters
experiment malfunctions when the dc-link voltage is lower than a threshold value.
From this significant examples, it results clear the important role of synchronization
in the control of grid-connected power electronic converters. The performance of the
synchronization block is critical in very fast responding applications as well as for high
power rated systems.

40

Chapter 1 Introduction

0.8

a
b

0.6
0.4
0.2

-0.2
-0.4
-0.6

-0.8
-1
13.98

13.985

13.99

13.995

14.005

14.01

14.015

14.025

14.03

50

1
1

30

20

10

-10

-20
13.9

14.1

14.2

14.3

14.4

14.6

14.7

14.8

1.6
1.55

1.45

1.4

1.35

dc
1.3

13.9

dc

14.1

14.2

14.3

14.4

14.6

14.7

14.8

Figure 1.23: VSC operation during a transient. Effect of the re-tracking speed.

1.7 Structure of the Document

1.7

41

Structure of the Document

This work is organized as follows.

1.7.1

Chapter 2: State-of-the-Art in Grid Synchronization

This chapter provides an in-depth study of the state-of-art in grid synchronization.

The most significant proposals in the field are analyzed, making special emphasis in pros
and cons of each one. The study starts with the most simple strategies such as the zerocross detectors and their big limitation dealing with power quality phenomena. Next, the
proposal of using a VCO inside the controller of a power converter (PLO system) proposed
for the first HVDC systems is deeply analyzed. The PLO based HVDC successfully
handle with the harmonic instability problem. Subsequently, the study of different PLLs
is provided, making special emphasis in the PLLs implemented in digital devices such
as the SRF-PLL. In the following section, some interesting alternatives to PLLs, such
as the use of FIR and stochastic filters in SRFs, are analyzed. Finally, the frequency
adaptability is studied for each synchronization technique. Besides this deep State-of-art
study, some sections of this chapter are novel contributions of this dissertation. More
specifically, the schemes based on SRFs and Moving Average Filters (MAFs), as well as
frequency adaptation techniques.

1.7.2

Chapter 3: Dynamics Study of Low-Gain PLLs

Chapter 3 is devoted to digital PLLs design. In a general way, PLLs with a low
bandwidth (low-gain PLLs) are required when handling with distorted voltages. It is
analytically demonstrated that low-gain PLLs have more trade-offs than high-gain PLLs
(e.g. PLLs for communications): it is not possible to optimize the settling time for a
phase-jump without getting slower the PLL response to frequency variations. Existing
tuning methods do not take into account low-gain features, which may result in nonoptimum designs. An intuitive tuning methodology based on inspection of frequencydomain diagrams is contributed in this chapter. Contrary to the other existing tuning
methods, it takes into account low-gain dynamics. It is assured an optimized performance
in the presence of any kind of disturbances in the grid. In the second part of the chapter,
the DCO based on a RC oscillator is presented: the digital model of a sinusoidal oscillator
is implemented, instead of explicit trigonometric functions. This solution reduces the
needed digital resources without reducing the performance, which could be specially useful
for DSP-based control of power converters.

42

1.7.3

Chapter 1 Introduction

Chapter 4: Predictive based SRF-MAF Synchronization

Algorithms

Chapter 4 presents a novel open-loop synchronization system, designed from SRFMAF schemes. Accurate measurements of phase, frequency and amplitude are carried
out in real-time.
Previous works establish that the fundamental positive-sequence vector of a set of
utility voltage/current vectors can be decoupled using Park transformations and low pass
filters. However, the filtering process introduces delays that impair the system performance. More specifically, when there is grid frequency deviations, a non zero average
steady-state phase error appears in the measurements.
To overcome such limitations, a suitable combination of predictive and moving average FIR filters is proposed to achieve a robust synchronization system for all input
frequencies. MAFs are linear phase FIR filters which have a constant time delay at low
frequencies. A characteristic which is exploited to good effect to design a predictive filter
which compensates such time delays, enabling zero steady-state phase errors for shifted
input frequencies.
In summary, the main attributes of the new system are its good frequency adaptation,
good filtering/transient response trade-off and the fact that its dynamics is independent of
the input vector amplitude. Comprehensive experimental results validate the theoretical
approach and the high performance of the proposed synchronization algorithm.

1.7.4

Chapter 5: Frequency Adaptive PR Current Controller

for APFs

Chapter 5 shows experimental results of an Active Power Filter implementation. A

feedforward control scheme has been implemented, where the main parts are the SRFMAFs extraction algorithms working together a proportional-resonant (PR) based current
regulator which assures perfect tracking at the selected harmonics. The resonant blocks
are tuned using frequency domain techniques. In order to get frequency adaptation, that
is, perfect tracking for any input frequency, the difference equation implementing each
resonant block depends explicitly on the frequency deviation. This frequency deviation
is estimated from a PLL. An in-depth study of the optimized implementation and practical considerations about the resonant controllers are contributed. Experimental results
obtained from a 1 kVA rated laboratory prototype prove the accuracy of the theoretical
approaches and the feasibility for industrial applications such as power line conditioners
and distributed power generation.

1.7 Structure of the Document

1.7.5

43

Chapter 6: Conclusions and Future Work

The main contributions of this work are reviewed in the last chapter. An outline of
programmed future works is also provided.

44

Chapter 1 Introduction

Chapter 2
State-of-the-Art in Grid
Synchronization
Abstract
The control of the power flow between a grid-connected power converter and the ac-mains
requires an online tracking of the fundamental component voltage (or current) phase-angle.
The very first synchronization schemes were based on an open loop estimation of the phaseangle from the observation of zero-crosses. However, the presence of power quality phenomena,
specially in weak-grids, led to malfunctions in zero-cross based controllers. The introduction
of voltage controlled oscillators (VCOs) resulted in more robust controllers such as the Phase
Locked Oscillator (PLO) system and the Charge-Pump Phase Locked Loops (CP-PLL).
With the suitability of discrete devices such as micro-controllers the number of synchronization algorithms and filtering techniques has grown drastically, in parallel with the appearance of
high performance applications (high bandwidth) and new technical requirements in fields such as
renewable energy applications, traction systems and power line conditioners. Digital Phase locked
Loops (PLL) and algorithms implementing stochastic and/or FIR filters are clear examples of
the high performance offered by digital implementation.
However, the research in the synchronization field cannot be considered complete at all. The
appearance of new applications and/or technical requirements of existing ones would need the
development of specific solutions. A review in synchronization strategies for power converters is
contributed in this chapter.
Even though the main part of this chapter is devoted to synchronization with fundamental component vectors, the issues of harmonics and negative-sequences extraction are also approached, since to synchronize with those components is required in several applications.
It should be noticed that, even though this chapter may seem to be presented in a temporal-line
manner, many of the approaches have coexisted since their proposal to nowadays.

45

46

Chapter 2 State-of-the-Art in Grid Synchronization

Input
VAC1

VAC2

D1

D3

Dgen

Dgen

R3

Q1

1k

D2

VOFF = 0
VAMPL = 25
FREQ = 50
V1 = 0
V2 = -30
TD = 0.0015
TR = 1u
TF = 1u
PW = 0.0001
PER = 0.02
V1 = 0
V2 = 30
TD = 0.0115
TR = 1u
TF = 1u
PW
= 0.0001
VOFF
=0
PER
= 0.02
VAMPL
= 25
FREQ = 50

QgenN

R1
100k

Dgen

VAMPL = 21.2V
FREQ = 50Hz

1k

C1
1000u

R2

Output

(a) Simple analog zero-cross detector circuit.

25
V(output)

20
15
10
Voltage (V)

VOFF = 0
VAMPL0= 25
FREQ = 50
-5

VOFF-10
=0
VAMPL = 5
-15
FREQ = 250
-20

D9

Dbreak

Dbreak

R6
C2
1000u

V+

V9

0
V10

V8
D11

Dbrea

1k

V
V-

V5

R5

Q4

V(input)

1k

QbreakN

V4

VOFF = 0 -25
VAMPL = 25 0
FREQ = 50
V6
VOFF = 0
VAMPL = 5
FREQ = 250

V2

D7

V7

0.01

0.02

0.03
Time (s)

0.04

R4
100k

0.05

(b) Key waves for a sinusoidal input wave.

D8

0.06

Figure 2.1: Zero-cross

detector example.
Dbreak
Title

2.1

V-

Methods based on Zero-Cross Detection

4
3
A zero-cross 5detector is a circuit which detects
the transition of a signal waveform
from negative and positive, and vice versa, providing a narrow pulse that coincides with
the zero voltage condition.

When using with ac networks, zero-cross detectors obtain the information of the phaseangle: 0 deg and 180 deg coincide with the pulses at the outputs.
In Fig. 2.1 an example of analog zero-cross detector connected to the utility grid is
shown. The input wave is supposed to be obtained from the secondary of a 220/15 V and
50 Hz transformer. The transistor Q1 is polarized in the active zone except during the
zero crosses. Under such a situation Q1 is in cut-off. As there is no current through Q1,
the voltage in the output is a bit lower than the peak value of the input voltage.
Fig. 2.1b shows the result of a time domain simulation, obtained with PSPICE, when
the input wave is ideal. As expected, the output has pulses during the zeros crosses.

Size
A
Date:

47

2.1 Methods based on Zero-Cross Detection

Input

U1
+

VAC1

Output

R1
1k

OUT
-

OPAMP

R2
1k

VAMPL = 21.2V
FREQ = 50Hz

(a) Simple analog zero-cross detector circuit.

25
20
15

Voltage (V)

10
5

V(output)

0
-5
-10
-15
-20
-25
0

V(input)
0.01

0.02

0.03
Time (s)

0.04

0.05

0.06

(b) Key waves for a sinusoidal input wave.

Figure 2.2: OA based zero-cross detector example.

Title
Size
A
Date:

Moreover, as the input4 wave frequency is just 50 Hz, the phase3 between zero crosses can
be extrapolated by means a multi-vibrator delay circuit or a digital counter [61].
The zero-cross detector circuit works per-phase. In three-phase systems it is common
to use one zero-cross circuit per-phase. A simpler solution is to use the phase-angle
extrapolated from one phase to set the zero crosses of the other phases, assuming balanced
conditions. The circuit of Fig. 2.1a can be easily adapted to obtain separate signals for
the zero-crosses at 0 deg and 180 deg; another transistor is needed.
The operational amplifier (OA) has been widely used for zero-cross detection. Fig. 2.2a
shows a simple circuit of zero-cross detection using an OA. Fig. 2.2b shows the result of
the time domain PSPICE simulation. When the input signal is sinusoidal, a square wave
in-phase with the input signal is obtained.

<Title

Docu
<Doc

48

Chapter 2 State-of-the-Art in Grid Synchronization

idc

Origin ac System

Rectifier

Destination ac System

Inverter

Figure 2.3: Simple HVDC diagram.

2.1.1

The First High-Voltage Direct Current Systems

The first implementation of power converters handling high power flows can be placed
in time with the high-voltage direct current systems (HVDC). HVDCs were initially used
to transmit large amounts of power between two ac systems over long distances. The
first commercial HVDC was developed between 1950 and 1954 in Sweden connecting the
Swedish island of Gotland with mainland. At that time, silicon devices were not suitable
for such a high power, so power converters were based on mercury-arc valves [62]. The
firing of these mercury-arc valves were equivalent to thyristor firing.
Fig. 2.3 shows a simple scheme of a HVDC. In order to minimize the losses in the
transmission line due to parasitic reactances, the origin ac voltages are transformed into
high dc voltages. A power converter is used working as rectifier to convert the origin ac
signal to dc. Another power converter is placed in the destination point to convert the dc
voltage to ac (inverter).
The control of a HVDC system is quite complex and requires many controllers including steady-state operation and protection against transients; this subsection is focused in
the steady-state operation.
The most widely method employed to control the average 1 power flow from the origin
ac side to the dc bus is the so-called constant current (CC). The average value of the
rectifier current (idc ) is controlled through the firing angle .

2.1.1.1

Constant- Method

These first rectifier controllers were based on the so-called constant- and inversecosine methods. Fig. 2.4a shows a simplified scheme of the constant- method.
The control scheme is a circuit which implements a zero-cross detector and a variable
1

averaged each cycle of the fundamental f1 .

49

2.1 Methods based on Zero-Cross Detection

Mercury-Arc based 6-pulse

Power Electronics Rectifier

Mercury-Arc based 6-pulse

Power Electronics Rectifier

DC v
dc
Side

AC
Side

Ld

idc

idc*

(external ref)

idc

Per-phase
AC Voltage
Sensors

Per-phase
AC Voltage
Sensors
Per-valve
Zero-cross
detection
circuits

DC v
dc
Side

AC
Side

Controlled
variable
delay
circuits

Firing
circuits

idc*

(external ref)

Controller circuit

(a) Constant- rectifier control scheme.

Per-valve
phase-lag
network
and
comparator

Per-valve
Zero-cross
detection
circuits

Firing
circuits

Controller circuit

(b) Inverse-cosine rectifier control scheme.

Figure 2.4: Constant- vs Inverse-Cosine HVDCs.

delay circuit per valve. The zero-cross detection circuits should detect separately 0 deg
and 180 deg zero crosses: 0 deg cross for upper valves and 180 deg for the lower ones. The
angle is controlled externally (angle reference) which controls the delay of the variable
delay circuits.

2.1.1.2

Inverse-Cosine Method

The basic principle is that the delay angle can be obtained from the crossing point of
an associated cosine-wave with a control reference voltage at a comparator. The cosinewave is obtained from a phase-lag network so the output of that network has a peak at
the delay angle () equal to zero [63]. The firing pulse is generated at the point at which
the cosine-wave is equal to the control voltage (vr ), which is directly proportional to idc .
emax being the peak of the cosine-wave, the firing condition is set by the equation:

cos() = vr /emax .

(2.1)

Fig. 2.4b shows a simplified scheme of the constant- method. The main advantage
of this method is the fact that vdc varies linearly with vr .

2.1.2

Drawbacks of Zero-cross Detectors

Even though this circuit obtains good results for a lot of applications, the growing up
concern about power quality problems have led to consider other high performance solutions. The main problems of zero-cross detectors are well summarized in [64]: harmonics
and noise.

50

Chapter 2 State-of-the-Art in Grid Synchronization

Fig. 2.5a shows the results of the time domain SPICE simulation when the input
wave has a 20% of 5th harmonic over the fundamental. As said, this harmonic changes
the zero-cross detection points, so there is non zero average phase error in steady-state.
With regard to the control of power converters, this error could easily lead to instability
and malfunction [65].
Fig. 2.5b shows the results of the time domain SPICE simulation when the input wave
contains notches. There are misleading zero-cross detections due to the notching, which
result in very high phase error.
Another drawback appears when considering input wave transients. Zero-cross detectors only estimate the phase-angle one or two times per cycle, so when a phase-angle
jump occurs is not detected until the next zero-cross. Moreover, zero-cross detectors do
not provide frequency estimation or adaptation, which could lead to malfunctions in the
presence of frequency deviations.

2.1.2.1

Improvements in Zero-cross Detectors

In order to improve the performance in the zero-cross detection, some simple but
practical actions have been proposed, e.g.:
In three-phase circuits a common practice has been to filter the b phase and
extrapolate the a phase from the filtered signal [66].
In order to deal with frequency variation in applications of motor control, some
enhanced zero-cross detector circuits have been contributed [67, 68].
With the suitability of digital devices implementing discrete operation, the possibility of digital filtering resulted in a vast range of filtering alternatives. e.g. in [69]
the fundamental component is reconstructed from a notching wave, assuming that
the short-circuit parameters are known; in [70] an 11th order FIR filter is proposed
to cancel out harmonics.

However, digital implementation makes suitable the implementation of algorithms with

a much higher performance than these based on zero-cross detectors. The suitability of
implementing trigonometric functions, multipliers, IIR and FIR filters, etc, gives much
more versatility than analog integrated circuits (ICs), as shown below.

2.1.2.2

Harmonic Instability of Zero-cross based HVDCs

Nowadays, it is well known that zero-cross detectors implementation in systems containing harmonics could lead to malfunctions. It was in a work published by J. D.

51

2.1 Methods based on Zero-Cross Detection

30
20

Detected
Zero cross
Real
Zero cross

Voltage (V)

10
0
-10
Fundamental
of V(input)

-20

V(input)
-30
0

0.01

0.02

0.03
Time (s)

0.04

0.05

0.06

(a) Key figures under harmonic contaminated input.

25

Good
zero-cross
detection

20
15

Voltage (V)

10
Misleading
zero-cross
detection

5
0
-5
-10
-15
-20
-25
0

V(input)
0.01

0.02

0.03
Time (s)

0.04

0.05

(b) Key waves for a input wave with notches.

Figure 2.5: Main drawbacks of zero-cross detectors.

0.06

52

Chapter 2 State-of-the-Art in Grid Synchronization

Xs

Xr
AC
Side

AC
Source

DC
Side

Thyristor or Mercury-arc valves

Controlled Power Electronics Converter

Figure 2.6: Weak Grid. Short circuit ratio Xr /Xs 3 6.

Ainsworth in 1967 [65], when a problem called harmonic instability was reported 2 .
Harmonic instability occurs when the rectifier was connected to a weak system, a
system for which the short-circuit ratio (Xr /Xs ) is low: e.g. in the range 3 to 6 [71].
The harmonic instability is a problem that is characterized by magnification of noncharacteristic harmonics (6= 5, 7, 11, 13) in steady-state. This is due to the fact that any
distortion in the ac side such as unbalance and harmonics affects to the firing instants.
This leads to a situation where the firing instants are not equidistant in steady-state
and to the generation of non-characteristic harmonics. The problem of generation of
non-characteristic harmonics could be even aggravated if some of that harmonics are in
parallel resonance with the circuit [34, 65].
In order to overcome the problem of harmonic instability, passive filters were proposed,
but it was an insufficient alternative [34]. The real milestone in the control of the HVDC,
and indeed in the control of power electronic converters was the Ainsworth proposal of [1]:
the firing instants are independent from voltage zero-crosses through a voltage controlled
oscillator (VCO) inside the control loop. This proposal is deeply analyzed in section 2.2.

2.2

Phase-Locked Oscillator Control Systems

A surprising novel scheme for the control of power converters was contributed by J.
D. Ainsworth in [1]: the phase-locked oscillator (PLO) control system. The work of
Ainsworth is related with the need of a robust controller for HVDC systems connected to
weak ac grids, a problem he had posed in his previous paper [65].
The first PLO was a control system for the HVDC rectifier. Under ideal operation
conditions and during steady-state, this converter produces 5th , 7th , 11th , 13th , etc harmonics in the ac side and 6th , 12th , etc in the dc side. Moreover, other harmonics may
2

Harmonic instability does not mean instability in a feedback control system.

Thyristor or Mercury-arc valves

Controlled Power Electronics Converter

53

2.2 Phase-Locked Oscillator Control Systems

Xs

Xr

Ld
DC
Side

AC
Side

Current
Sensor

C2

a
VCO

vdc zL

C1

Firing
Signals

idc

vco

R1

idc*

Figure 2.7: Scheme of the PLO controller for the HVDC rectifier proposed in [1].

also appear if unbalance and timing errors in the control systems are considered. The
presence of voltage harmonics in the ac side is higher as higher is the impedance between
the power converter and the generation (weak system) [65, 71]. The problem of those
converters working in a weak grid is the dependence of the control from the measurement of the ac voltages, which could result in harmonic instability. Ainsworth proposed
a closed-loop controller containing a voltage controlled oscillator (VCO) in order to reject
the harmonics effect.
Fig. 2.7 depicts a PLO simplified scheme. The inductance current (idc ) is controlled in
a closed loop; idc being its reference value. An analog filter is placed after the comparator;
the output of this filter is the input voltage of the VCO (vco ). The VCO generates
output pulses at a repetition frequency six times the system voltages/currents fundamental
frequency; the frequency of the VCO output signal implicitly represents the estimated
fundamental frequency (
1 ). The output pulses, generated through a ring counter, are
employed to fire the thyristors/valves. When there is a positive difference in the output of
the comparator, the vco voltage tends to rise and, therefore,
1 increases, so is reduced.
For negative difference, the behavior is the opposite one.

2.2.1

PLO Linearization

Even though Fig. 2.7 represents a quite simplified model of the PLO system, it has
a very non-linear behavior. This subsection describes a linearization of the PLO system.
The linearization of the PLO was made by Ekstrom and Liss in [72], and, even though
Ainsworth was skeptical with this procedure (see discussion of [72]), nowadays it is clear
that linearization is a powerful tool to describe non-linear systems.
The average value of the voltage in the dc link (
vdc ) is function of the line to line peak

54

Chapter 2 State-of-the-Art in Grid Synchronization

voltage (vllmax ) and the firing angle :

3
vllmax cos() = vdcmax cos(),

vdc =
where vdcmax =

(2.2)

vllmax .

Lets suppose a perturbation in the firing angle << 1, a small change in vdc (vdc )
is supposed. By introducing and vdc in (2.2)

vdc = vdcmax sin() sin(),

(2.3)

which can be approximated to

vdc = vdcmax sin() .

(2.4)

is function of the difference between 1 and

1 , during a time t:

= (
1 1 ) t = 1 t,

(2.5)

and, in the Laplace domain,

1
.
s

(2.6)

Therefore,

vdc = vdcmax sin()

1
,
s

(2.7)

which goes on being a non linear equivalence.

The relation between vdc and idc depends on the inductance Ld and the load impedance
(zL ):

idc =

vdc
.
Ld s + zL

(2.8)

Linking (2.4) and (2.8),

idc =

vdcmax sin()
Ld s + zL

1
s

(2.9)

55

2.2 Phase-Locked Oscillator Control Systems

PLANT

CONTROLLER
*
idc

+-

idc

1
C2 R1 s + 1
s C1 C2 R1 s + (C1 + C2 )
Analog filter

K vco g ( t ) t
e
s

VCO and Firing Circuit

vd max sin( )
Ld s + z L
Rectifier circuit

Figure 2.8: Equivalent block diagram of PLO circuit and control.

1 has a linear relation with the input of the VCO:

1 = Kvco vco ,

(2.10)

vdcmax sin() Kvcosvco

.
Ld s + zL

(2.11)

so

idc =

Ainsworth designed a controller for the plant set by (2.11). This equation is non linear;
the plant depends on the firing angle through sin(). Another source of non linearity is
due to the fact that the controller only acts at 60 deg intervals, that is, there is a time
dependent delay function, which should be considered in the design of a controller.
The controller proposed by Ainsworth was:

C(s) =

Kc
C2 R1 s + 1

C2 C1 R1 s + (C2 + C1 ) s

(2.12)

Kc being a constant. Fig. 2.8 shows the control block diagram of the PLO.
In order to study the dynamics of the system, this model should be evaluated in all
the range of possible values of . In [1] the minimum was 5 deg. It is clear that, the
lower , the lower the gain of the loop.
As pointed by Ainsworth the circuit in steady state is always in the range [0, 180] deg.
This implies in practice that
1 1 so

g(t)

1
.
6 f1n

(2.13)

Therefore, the firing delay can be modeled taken into account the worst case: the
delay is maximum ( 6f11n ) (Fig. 2.9).

56

Chapter 2 State-of-the-Art in Grid Synchronization

PLANT

CONTROLLER
*
idc

+-

idc

Kc
C2 R1 s + 1
s C1 C2 R1 s + (C1 + C2 )

K vco
e
s

Analog filter

1
t
6 f1n

VCO and Firing Circuit

vd max sin( )
Ld s + z L
Rectifier circuit

Figure 2.9: Equivalent block diagram of PLO circuit and controller for firing maximum
delay.
Table 2.1
HVDC values.

vdcmax

1 p.u.

zL (Resistive)

1 p.u.

Ld

1/(10 ) p.u.

The tuning of the PLO controller presents several difficulties. In sum:

The plant changes with sin().

It has two poles at the origin. The phase versus frequency response is 180 deg at
dc.
The introduced delay tends to lag the phase, reducing the phase margin (PM).
There are another two poles: one at (C1 + C2 )/C1 C2 R1 rad/s due to the controller and another at zL /Ld rad/s due to the plant.
There is only a zero due to the controller in 1/(C2 R1 ) rad/s.
In order to avoid a negative phase margin for very low frequencies and, therefore, to
have an unstable system, the controller should have its zero very near to the origin. The
bandwidth of the system is limited by the second pole of the controller.

2.2.1.1

Design Example

A more in-depth study of a model would require the knowledge of the practical system values employed by Ainsworth. In this section, an example of the PLO system is
contributed in order to show its performance 3 .
The most important data of this table is the relation between zL and the equivalent
inductance Ld , because this relation sets a pole in the plant. The controller parameters
of the example are shown in table 2.2.

57

2.2 Phase-Locked Oscillator Control Systems

Table 2.2
Controller Values.

R1

100 k

C1

100 pF

C2

100 F

range

[5, 90] deg

Kc

105

Kvco

100 rad/V

300

300

Total
Total

200

100

Amplitude (dB)

Magnitude (dB)

200

Controller

0
Delay

-100

Controller
100
Plant
0
Delay
-100

Plant

-200 -3
10

-2

-1

10

10

10

-200 -3
10

10

10

10

Delay
Controller

10

10

Controller

-50
Plant

-100
Plant

Total

-150

Phase (deg)

Phase (deg)

-1

10

Delay
-50

-180
-200
-250
-300 -3
10

-2

10

-100
-150

Total

-180
-200
-250

-2

10

-1

10

10
Frequency (Hz)

10

10

-300 -3
10

-2

10

-1

10

10
Frequency (Hz)

10

10

(a) Equivalent linearized model for = 5 deg. (b) Equivalent linearized model for = 90 deg.
P M = 66.5 deg, at 1.35 Hz.
P M = 19.92 deg, at 8.25 Hz.

Figure 2.10: PLO equivalent model at different values.

58

Chapter 2 State-of-the-Art in Grid Synchronization

0.75

0.65

0.94

0.6

0.93

0.55

0.92

0.91

0.45

0.89

0.5

1.5

(a) PLO Start-up.

0.95 p.u..

2.5

3.5

4.5

1.5

2.5

3.5

4.5

Step in idc from 0.9 p.u. to (b) PLO Start-up. Step in idc from 0.55 p.u. to
0.5 p.u..

Figure 2.11: Start-up simulation of PLO for different idc (dotted), idc is the blue line.
As shown in Figs. 2.10 it is possible to tune a controller stable for all the range. As
pointed by Ekstrom in [72], for higher values the system is difficult to stabilize. In fact,
the PM for = 90 deg is very small. But, on the other hand, as pointed by Ainsworth
in the discussion of [72], it is also true that for lower values the tuning becomes more
concerning since the bandwidth becomes very small and the system could easily go out
from normal operation.
From Figs. 2.10 an important feature of the PLO is observed. The magnitude gain
decreases very fast with the frequency, so it is expected a good current harmonic cancellation.
The simplified scheme of Fig. 2.7 with the parameters and component values of
table 2.2 has been simulated through the PLO Matlab scripts of appendix (from A.1
to A.3).
Fig. 2.11 shows the start-up for a the PLO working in different points (). After the
initial transient the current reference is perfectly tracked. Fig. 2.11a shows the startup when is 18.2 deg. In such a situation, the output current in steady-state should
be 0.95 p.u.. Fig. 2.11b shows the start-up when is 60 deg, so the output current in
steady-state should be 0.5 p.u.. A comparative between both figures shows how for lower
the overshoot is lower, since the PM is higher. Higher results in a shorter rise time
but with a higher overshoot, since the PM is shorter. These results are expected from
Figs. 2.10.
Figs. 2.12 show the system voltages when steady-state is reached for both cases shown
in Fig. 2.11. As zL has been chosen to be 1 p.u. pure resistive, vdc should be equal to idc .
Figs. 2.13 show the results of a simulation when the voltages system is unbalanced
both in amplitudes and angles. Specifically the phase to neutral voltages of the test have
3

Component values and tests made in this section may differ from first PLO tests.

59

2.2 Phase-Locked Oscillator Control Systems

1
0.95

0.8

0.8

Vdc

Vdc

Vdc

Vdc

0.6

0.6

0.5
0.4

0.4

0.2

0.2

0
-0.2

Vc

Vb

Va

-0.2

-0.6

Va

Vb

Vc

-0.4

-0.4

5.95

5.955

5.96

5.965

5.97

5.975

5.98

5.985

5.99

5.995

-0.6

5.95

(a) Steady state voltages for Fig. 2.11a.

5.955

5.96

5.965

5.97

5.975

5.98

5.985

5.99

5.995

(b) Steady state voltages for Fig. 2.11b.

Figure 2.12: Steady-state system voltages for Figs. 2.12.

1

Vdc

Vdc

0.8

0.78

0.7
0.6

0.76

0.4
0.74

0.2
0.72

0
Va

-0.2
0.68

0.66

Vb

Vc

-0.4

1.5

2.5

3.5

4.5

(a) PLO Start-up for an unbalanced set of voltages.

Step in idc (dotted) from 0.8 p.u. to 0.7 p.u., idc is
the blue line.

-0.6

5.95

5.955

5.96

5.965

5.97

5.975

5.98

5.985

5.99

5.995

(b) Steady state voltages for Fig. 2.12b.

Figure 2.13: PLO tested under a very unbalanced system of voltages.

the expression

va = 1 sin(1n t)
vb = 0.8 sin(1n t (2 pi/3 + 0.1))
vc = 0.9 sin(1n t + (2 pi/3 + 0.1)).

(2.14)

Perfect tracking under unbalanced conditions is observed; the PLO rejects voltage
unbalance effects.
Figs. 2.14 show the results of a simulation when the voltages system is unbalanced
both in amplitudes and angles and also very distorted by harmonics. Specifically, the
phase to neutral voltages of the test have been:

60

Chapter 2 State-of-the-Art in Grid Synchronization

1.2

0.84

Vdc
0.82

Vdc

0.8

0.6
0.78

0.4
0.76

0.2
0.74

0.72

Vb

Va

-0.2

Vc

-0.4

0.68

-0.6

1.5

2.5

3.5

4.5

(a) PLO Start-up for an unbalanced set of voltages.

Step in idc (dotted) from 0.8 p.u. to 0.7 p.u., idc is
the blue line.

-0.8

5.955

5.96

5.965

5.97

5.975

5.98

5.985

5.99

5.995

(b) Steady state voltages for Fig. 2.14a.

Figure 2.14: PLO tested in the presence of an unbalanced and polluted with harmonics
system of voltages.

va = 1 sin(1n t) + 0.1 sin(51n t) + 0.1 sin(71n t)

vb = 0.8 sin(1n t (2 pi/3 + 0.1)) + 0.1 sin(51n t + 0.1) + 0.1 sin(71n t 1)
vc = 0.9 sin(1n t + (2 pi/3 + 0.1)) + 0.1 sin(51n t + 0.9) + 0.1 sin(71n t 0.7).
(2.15)

Perfect tracking under unbalance and harmonics is observed. In this way, the problem
of harmonic instability in weak grids was overcome with the PLO.
Figs. 2.15 show the results of a simulation when the voltages system is very distorted
and there is a load transient: at 2.5 s a change from 1 p.u. to 1.1 p.u. has been programmed.
The PLO system retracks perfectly after the transient, so it could be said that the PLO
is robust in the presence of load transients.
Figs. 2.16 show the results of a simulation when the input frequency has a step change
and how the VCO frequency estimation (f1 ) follows its reference f1 . Therefore, another
important feature of the PLO is its good frequency adaptation.
In sum, the PLO does not only fix the harmonic adaptation problem. The proposal
of using a VCO circuit inside the controller of a power converter also resulted in a very
effective tool to overcome other problems such as unbalance, frequency adaptation and
noise cancellation.

61

2.2 Phase-Locked Oscillator Control Systems

0.84

1.2

Vdc
0.82

Vdc
0.78

0.6

0.76

0.4

0.74

0.2

0.72

0.68

Vb

Va

-0.2

Vc

-0.4

0.66

-0.6

0.64

1.5

3.5

4.5

-0.8

(a) Ainsworth model Start-up and transient at

2.5 s for a distorted set of voltages. The reference
current is 0.7 p.u., idc is the blue line.

5.955

5.96

5.965

5.97

5.975

5.98

5.985

5.99

5.995

(b) Steady state voltages for Fig. 2.15a.

Figure 2.15: PLO transient test: sudden change in zL .

0.85

50.7

50.6

50.4

0.75

50.3

50.2

50.1

12

14

16

18

12

14

16

18

(a) PLO current response. idc (dotted) is 0.7 p.u., (b) Grid (f1 ) VS VCO (f1 ) Frequencies for Fig.
idc is the blue line.
2.16a.

Figure 2.16: PLO tested under a sudden change in the input frequency at 10 s.

62

2.2.2

Chapter 2 State-of-the-Art in Grid Synchronization

Other Phase-Locked Oscillator Schemes

The PLO system was also proposed with other schemes. Some of the most significant
ones are detailed below.

2.2.2.1

PLO for Voltage Control

An alternative to the Ainsworth controller has been posed in [73]. In this scheme a
thyristor based controller is controlled in a closed loop with a VCO inside. The difference
of this scheme with respect to the Ainsworth one is the fact that the controlled variable
was the dc link voltage, so in practice, the second pole of the plant disappeared. This
allowed to Skjellnes et al to develop a closed loop with a bandwidth of 100 Hz, so
the transient response is highly enhanced with respect to the Ainsworth PLO. The main
limitation of this scheme is due to the fact that most of the practical applications require
a current control loop.

2.2.2.2

PLO for Speed Control of dc Motors

The PLO scheme has been adapted to the speed control of dc motors [63, 74, 75]. A
speed encoder and a phase comparator circuit are implemented in order to obtain the error
signal which controls the VCO frequency and, hence, the firing of the thyristor converter.
Based on this scheme, a frequency adaptive system with an acceptable transient response (around one cycle of 1n ) is achieved in [74].

2.3

Phase Locked Loops

As shown in the previous section, the Ainsworth proposal of using a VCO inside the
contro loop of a power converter provides harmonics/unbalance rejection and frequency
adaptation. However, the PLO system is very difficult to tune, and extra controllers
monitoring correct operation are needed [1].
An alternative use of the VCO is in phase locked loops (PLLs) tracking the fundamental phase-angle, as proposed in [76, 77]. PLLs had been used in other fields, specially
communications, since the 40s [78, 79]. The works of [76, 77] extended the applicability
of PLLs to the control of power electronic converters.
The main novelty of the PLL proposal is the fact that the VCO is not a part of the
main control algorithm; the VCO is employed inside a measurement circuit (estimation).

63

2.3 Phase Locked Loops

vd

ac

dc Motor
ac Voltage Sensor

va

PLL

vd*

Main
Control

Comparator

ref

PWM
Circuit

Controller Circuit

Figure 2.17: Control scheme of a dc motor in a single-phase grid.

Fig. 2.17 shows the scheme proposed in [76] for the control of a thyristor controlled
rectifier in a single-phase motor drive application.
Even though the application is simpler than the HVDC rectifier of [1], it is clear that
the use of the PLL as a measurement circuit liberates the main controller of two poles
at the origin, which tend to make the system unstable.

) is set
The schemes of [76, 77] are very simple because the main control reference (vdc
open loop (Fig. 2.17). However, as shown below, the kind of PLLs employed in [76, 77]
has more limitations considering power quality phenomena than PLO systems. Even so,
it is clear that the proposal of using PLLs inside the controllers is, without any doubt, a
milestone in the field of synchronization and power electronics control in general.

Fig. 2.18a shows a simplified PLL scheme. A PLL is a non-linear circuit which
synchronizes its output signal (vo ) with a reference or input signal (vi ) in frequency as
well as in phase.
The
fundamental frequency and phase-angle of vi are 1 and 1 ; they are related by
R
1 = 1 t + 1 where 1 is an offset dc constant. In the same way, the output signal
vo parameters are the estimated values of vi :
1 , 1 and 1 . In steady-state it is expected
that estimated and real values are the same.
The PLL scheme is composed by the three basic functional blocks: the phase detector
(PD), the loop filter (LF) and the voltage controlled oscillator (VCO). The role of each
block could be summarized as follows:
The PD is a circuit for which the average value of its output, averaged each cycle

64

Chapter 2 State-of-the-Art in Grid Synchronization

vi

Phase
Detector
vo

ve

Loop
Filter

Voltage
Controlled
Oscillator
1 = 1n + K vco vco

1 = 1t + 1

vco

(a) Block diagram of a PLL.

PD
+-

1e

Loop
Filter

1 = 1t + 1

VCO (DCO)

1n

+ +

(b) Linear model of a PLL.

Figure 2.18: Basic conceptual models of PLLs.

of the fundamental component of the input, is zero only when the input signals are
in-phase, that is, they are synchronized in phase and frequency.
The LF supplies a filtered control signal (vco ) to the VCO.
The VCO generates a signal of frequency
1 from its central frequency, which, in
grid applications, should be adapted to 1n and vc . The estimated frequency is

1 = 1n + Kvco vc , where Kvco is the VCO constant. Later, in digital PLLs, the
term Digitally Controlled Oscillator (DCO) is employed instead of VCO (integrated
circuit).

PLLs should be linearized in order to study its dynamics and tuning the LF. This
process is done assuming that the PLL is near locked state, that is, 1 =
1 and i 1
[78, 79]. Under such a situation, the equivalent system is the linear PLL (LPLL) of Fig.
2.18b.
The LPLL is a typical closed loop servo system. The instantaneous phase-angle error
at the fundamental component is 1e = 1 1 . The LF path provides a frequency
correction around the nominal (central) frequency (
1 ). When designing a PLL, its
most important features are:

1. Stability: the LPLL model should have high enough stability margins in order to
assure the stability of the PLL.
2. The type of the PLL: it is set by the number of origin poles of the equivalent
LPLL. A type 2 PLL (two origin poles) is necessary to assure 1e = 0 when frequency
deviations are considered [78, 79].
3. The LPLL bandwidth sets
the transients response. The higher the bandwidth, the faster the PLL retracks
the phase-angle after a transient.

PD
++

o t + o

65

2.3 Phase Locked Loops

D

if( (V(%IN1)>0.9 & V(%IN2)<0.1) |

U7

Raux2
100k

OPAMP

0
VAMPL = 21.2V
FREQ = 49

OUT

U5

(V(%IN2)>0.9 & V(%IN1)<0.1),-5,5)

+
Raux
1k

VAC2

2
V

Vcp

Vc

R1

IN

1k

C1
10u

Phase Detector & Charge Pump

OUT

VCO_sqr

0
V

U8 2.19: Block diagram of an analog CP-PLL.

Figure
+
VAC3

Raux1
1k

OUT
-

OPAMP

if( (V(%IN1)>0.9 & V(%IN2)<0.1) |

(V(%IN2)>0.9 & V(%IN1)<0.1),-5,5)
1

3
the harmonic/noise filtering. The2 presence of
noise and harmonics in the inputs
0
Phase Detector
& Charge
Pump
affects the PLL measurements. The
term
phase
jittering is employed by
Best and GardnerU9
to
refer
to
the
effect
of
noise
in
the
phaseRaux4
estimation: phase
100k
+
jittering
(Raux3
in the value of 1e during zero crosses
due to noise 4 .
VAC4
1ej ) is the error
OUT
0
1k
2
2
In a general way,- the
average value of 1ej
(1ej
) is inversely proportional to
OPAMP
0
the
PLL bandwidth [78, 79].

VAMPL = 1V
FREQ = 50

VAMPL = 1V
FREQ = 50

2.3.1

Charge-Pump PLLs

Title

<Title>

As said, the schemes implemented in [76, 77] are pioneer in power electronics, and
gave rise to much more development in the PLL technique during
the
end
Saturday,
July 05,of
2008 70s and
Date:
Sheet
early 80s [80, 81].
Size
A

Document Number
<Doc>
2

PLLs proposed in [76, 77, 81] are Charge-Pump PLLs (CP-PLLs) [79, 82]. CP-PLLs
have a sequential-logic PD working together with a charge pump. The purpose of the
charge pump is to convert the logic states of the PD into analog signals suitable for
controlling the VCO. The main advantage of the charge pump is the chance of using
analog filters.
Fig. 2.19 shows the PSPICE model of a simple CP-PLL using an EXOR gate as PD.
The main characteristic of the CP-PLL using an EXOR gate is that, in tracking state,
the output leads the input signal 90 deg (cosine-wave).
The parts of this model are explained as follows:

A comparator with zero is placed in order to generate a digital signal for which the
logic value changes occur synchronized with the ac grid zero crosses.
The input and feedback signals from the VCO are the inputs of an EXOR gate.
The output of the EXOR gate controls a Charge Pump. The output of the EXORCharge Pump system is an analog wave (vcp ) for which the average value, averaged
each cycle of the fundamental, depends on the relative phase between the two digital

of
1

66

Chapter 2 State-of-the-Art in Grid Synchronization

0.015

0.02

0.025

Charge-Pump Output (V)

0.01

Input 2
Feedback

EXOR inputs

Input 2
Feedback

0.03
Time (s)

0.035

0.04

0.045

0.01

0.05

0.015

Averaged

0.02

0.025

0.03
Time (s)

0.035

0.04

0.045

0.05

0.04

0.045

0.05

Averaged

Charge Pump Output (V)

EXOR inputs

Input 2
1 (Feedback)
(AC Comp.)
Input 1
AC Comp

Input 1
AC Comp

Instantaneous

Instantaneous
0.01

0.015

0.02

0.025

0.03
Time (s)

0.035

0.04

0.045

0.05

0.01

0.015

0.02

0.025

0
(a) Key diagrams for 1e = /2 rad (1e
= 0 rad). (b) Key diagrams
0
(1e
= pi/4 rad).

0.03
Time (s)

for

0.035

1e

/4 rad

Figure 2.20: Key diagrams for the EXOR-Charge Pump Phase Detector
0
= 1e pi/2:
input signals. Through defining 1e

vcp =

2vcpmax 0
0
1e = Kd 1e
.

(2.16)

Fig. 2.20 shows the outputs of the EXOR-Charge-Pump PD.

0
Considering vcp vco , from eq. (2.16) a negative 1e
results in a negative vco , so the

VCO frequency (f1 ) decreases. As the feedback signal has a lower frequency than
0
the input one, 1e
tends to decrease, and therefore, the system tends to retrack the
0
the behavior is opposite.
phase. For positive 1e

The role of the LF is to cancel the ripple in the output signal of the PD. As shown
in Fig. 2.20, the output of the PD has a fundamental component (
vcp ) but also
harmonics, which affect to the VCO dynamics. For this reason, the LF should be a
low pass filter (LPF). In the model a first order LPF with cut-off frequency equal
to 100 rad/s has been implemented.
Fig. 2.21 shows time domain simulation results for the CP-PLL of Fig. 2.19. The
values of table 2.3 were employed. The system tracks the input phase and frequency in
around 3 cycles of the fundamental (f1n = 50 Hz).
The PD detector of this simulation is of EXOR type. However, the so called phasefrequency detectors (PFDs) providing a feedback signal in-phase with the input (no 90 deg

67

2.3 Phase Locked Loops

25
20
15
AC input (V)

10
5
0
-5
-10
-15
-20
-25

0.05

0.1
Time (s)

0.15

Input 2 (VCO)

Input 2 (VCO)
1

EXOR inputs

0.8
0.6
0.4
0.2
0
0

Input 1 (AC)

0.05

Time (s)

0.1

Input 1 (AC)

0.15

VCO input, averaged value (Averaged each 20.4 ms)

Voltage (V)

VCO input

-0.1V

-5
0

VCO input

0.05

0.1
Time (s)

Charge-Pump output

0.15

Figure 2.21: Time domain simulation results from the CP-PLL model at f = 49 Hz.

68

Chapter 2 State-of-the-Art in Grid Synchronization

Table 2.3
Controller Values.

Kd

3.18 rad/V

100

10 F

Kvco

10 V/Hz

shift) have been the most widely employed in power converters [75].
On the other hand, even though some current works implement CP-PLL [83], the use
of these kind of solutions are being abandoned by digital implementations. The limitations
of CP-PLL are:
Most of the classical VCOs such as the ICs 8038, 4044, 4046, and Siemens TCA
780-785, etc are becoming obsolete components [84]. Digital implementation is
definitively a current trend.
The PD is based on zero-cross detection and therefore, could introduce phase error.
In three-phase systems, as they work per phase, they cannot detect the fundamental
positive-sequence.

2.3.2

Digital SRF-PLL

Fig. 2.22 shows the Synchronous Reference Frame PLL (SRF-PLL or dq-PLL). The
main feature of the SRF-PLL is that it estimates the phase-angle of the fundamental
+
+
positive-sequence (vabc
): therefore, the estimated phase-angle (1 ) corresponds with va1
1
+
+
phase-angle. If vabc waves are considered sine-waves, P1 of (1.40) is implemented, but
most of the authors usually present the SRF-PLL with the Park transformation obtained
+
as in (1.44), which implies that vabc
components are considered cosine-waves. Anyway,
both approaches are totally equivalent.
The SRF-PLL structure was proposed by Gole et al in some simulation models of
rectifiers and Static var compensators [85, 86]. On the other hand, the SRF-PLL real
time implementation in a digital device was presented by Kaura and Blasko in [28], even
though a similar implementation had been previously proposed by Blasko et al in [87].
SRF-PLLs are very suitable to work together with other SRF controllers: the phase+
angle of va1
sets the origin of the positive-sequence SRF, so that a SRF-PLL assures an
accurate power flow control. This fact was crucial in the success of the SRF-PLL, since
SRF-based current controllers have been employed in all kind of high performance power
converters applications, such as:

69

2.3 Phase Locked Loops

PD

va
vb

vd+1 + f (h1 )

P1+

vc

vq+1 + f (h1 )

LOOP
FILTER

1 = 1t + 1

1n

+ +

DCO

Figure 2.22: SRF-PLL block diagram.

Motor drives [60, 8890].
Controlled rectifiers [26, 58, 59, 91, 92].
Power Line Conditioners [8, 27, 4143, 93].
DPGSs and Grid Monitoring [94, 95].
UPS [51, 53, 96, 97].

The field of application of the SRF-PLL is very wide and, hence, its optimization has
been approached in several works [22, 28, 46, 94, 98114]. The feasibility of powerful
digital devices and novel implementation techniques have led to more and more enhanced
implementations.

2.3.2.1

SRF-PLL Operation

+
Considering vabc
a set of phase to neutral sine-waves, the Park transformation (2.17)
+
acts as phase detector and the quadrature component (vq1
) as phase error signal (1e ), so
+
that vq1 1e .

vd1+

vq1+

{z

v+
dq

va

= P+
v ,
1
b
vc
}
|

{z

vabc

(2.17)

where

) sin(1 + 2
)
2 sin(1 ) sin(1 2
3
3
.
P+
=
1
3 cos(1 ) cos(1 2 ) cos(1 + 2 )
3
3

(2.18)

70

Chapter 2 State-of-the-Art in Grid Synchronization

The estimated phase-angle 1 is employed to generate P+

1 . The SRF-PLL is implemented in a digital device; a digital controlled oscillator (DCO) substitutes the VCO
circuit. The DCO is an integrator and a feed-forward constant with the nominal frequency so the central frequency of the PLL is 1n . The LF path provides a correction
value (
1 ) around 1n .
For the SRF-PLL linearization, the system is considered around the tracking point,
that is, 1 =
1 and 1 1 , and also balanced inputs [28]. Under such a situation

vd1+

vq1+

{z

v+
dq1

+
va1max cos(1 1 ) va1
max

=
+

va1max sin(i 1 ) va1max (i 1 ) = va1max 1e

(2.19)

+
+
+
+
where va1
(= vb1
= vc1
) should be rearranged so that va1
= 1 p.u.. It is
max
max
max
max
+

expected that vq1+ , which represents 1e , to be zero in steady-state and, therefore, vd1
=
+
va1max . If amplitude measurement is not employed, only the q component of the P+
1 is
generated (less needed resources).
+
It should be noticed that, the zero-sequence of vabc
is eliminated in the PD. In fact,
several three-phase and three-wire systems could not have a physical neutral connection.
This is not a problem, but an advantage: phase to phase voltages can be employed in
order to reduce the number of voltage sensors (from 3 to 2) and components of P+
1 matrix.
Eq. (2.17) can be rewritten as

vd1+

vq1+

{z

v+
dq

va vc

vb vc

vc vc = 0

{z

= P+
1

(2.20)

Line to line voltages

being the discrete implementation optimized accordingly.

2.3.2.2

Pre-filters for the SRF-PLL

From PLL theory, the level of distortion in the input signal should be taken into
account to tune PLLs, which is approached in detail for the SRF-PLL in the next chapter.
However, it should be highlighted here that a significant bandwidth reduction may lead
to a very slow transient response.
In order to improve the whole dynamics of the SRF-PLL some authors have proposed
the use of pre-filters, which act in a rotating reference frame (vabc or v ). In this
manner, the input of the SRF-PLL is cleaner and therefore it can be tuned with a higher
bandwidth. Some interesting proposals are summarized below:

71

2.3 Phase Locked Loops

PD

va
vb
vc

vd+1 + f (h1 )

va+1 + f (h1 )

S+

vb+1 + f (h1 )

P1+

v + f (h1 )
+
c1

vq+1 + f (h1 )
LOOP
FILTER

1 = 1t + 1

DCO

1n

+ +

Figure 2.23: SRF-PLL with Fortescue operator based pre-filter.

2.3.2.2.1 All-pass Filters based Sequence Detector A sequence detector to prefilter the negative-sequence component and feed the SRF-PLL only with positive-sequence
was proposed by Lee et al in [22].
Considering only components at fundamental frequency, the positive-sequence can be
expressed by means of the Fortescue matrix (S+ ):

+
va1

+
=
vb1

+
vc1

1
2

+j

3
2

1
2
a
1
3
a a2
|

where a =

{z

S+

a2

va1

v ,
a
b1
1
vc1

(2.21)

or a = ej 3 .

The imaginary term j corresponds with a delay of 90 deg in a real signal, so digital
implementation of (2.21) is possible by means of all-pass filters delaying 90 deg the components rotating at 1 (phase at f1 ). Another important feature of all-pass filters is the
unitary gain for all frequencies.
Fig. 2.24 shows the Matlab/Simulink model of a sequence detector using an all-pass
filter (A(z)) of the form 5 :

A(z) =

0.967z + 1
,
z 0.967

(2.22)

in the Z-domain, implemented at fs = 10 kHz. The frequency and transient response of

A(z) are also shown. A phase of exactly 90 deg at 1n is achieved.
Fig. 2.25 shows simulation results obtained from the model of Fig. 2.24: the input
signal is unbalanced but the output has only the (estimated) positive-sequence.
This technique is also suitable when there are harmonics in the inputs. As shown
below, some harmonic sequences are canceled with this implementation. However, the
5

It seems that there is not any specific detail of the original A(z) employed in [22].

72

Chapter 2 State-of-the-Art in Grid Synchronization

-0.967 z+1

1/3*(u(1)-0.5*u(3)-0.5*sqrt(3)*u(4)-0.5*u(5)+0.5*sqrt(3)*u(6))

z-0.967
Va

Vap

All -pass

Vb

-0.967 z+1

1/3*(-0.5*u(1)+0.5*sqrt(3)*u(2)+u(3)-0.5*u(5)-0.5*sqrt(3)*u(6))

z-0.967

Vbp

Scope 1

All pass
1/3*(-0.5*u(1)-0.5*sqrt(3)*u(2)-0.5*u(3)+0.5*sqrt(3)*u(4)+u(5))
-0.967 z+1
Vcp

z-0.967
Vc

All pass

Frequency Response

1
0

-5
-75

Phase (deg)

Step Response

1.5

Amplitude (p.u.)

Magnitude (dB)

-80
-85

0.5

0
-0.5

-90
-1

-95
-100
-105
40

42

44

46

48
52
50
Frequency (Hz)

54

56

58

60

-1.5
0.018

0.02

0.022

0.024

0.026

0.028

Time (s)

0.03

0.032

0.034

Figure 2.24: Matlab Simulink model and all-pass filter features.

0.8
0.6
0.4
0.2

-0.2
-0.4
-0.6
-0.8
-1
0.01

0.02

0.03

0.04

0.05

0.01

0.02

0.03

0.04

0.05

0.8
0.6
0.4
0.2

-0.2
-0.4
-0.6
-0.8
-1

Figure 2.25: Positive-sequence estimation with all-pass filters (f1 = 50 Hz).

73

2.3 Phase Locked Loops

va
vb
vc

PD

Q+

v+

vd+1 + f (h1 )

B+

v+

vq+1 + f (h1 )
LOOP
FILTER

1 = 1t + 1

1n

+ +

DCO

Figure 2.26: SRF-PLL with pre-filters in the frame.

SRF-PLL should filter the non canceled sequences.

2.3.2.2.2 Delayed Signal Cancellation in the Frame Fig. 2.26 shows a

method for negative-sequence cancellation in the frame [115, 116] applied to the SRFPLL [102, 117]. It is quite remarkable the fact that working in the frame reduces the
number of filters from 3 to 2.
The input signal vabc is expressed in the frame by means of the Clarke Transform:

{z

va

2 1 0.5 0.5

vb .
3
3

3 0
2
2
vc
|
{z
}
C

{z

vabc

(2.23)

The fundamental positive-sequence is obtained through the Q+ matrix as

v+

v+

where q = ej

{z

Q+

(2.24)

Finally the angle transformation (B+ )

+
vd1

+
vq1

B+ C = P+ .

+
is employed to get vdq

cos(1 ) sin(1 )
v+
=
.
sin(1 ) cos(1 )
v+
|

1 1 q v
=

,
2 q 1
v

{z

B+

(2.25)

74
Frequency Response

Step Response
1.5

D(z)
D(z)

A(z)

Amplitude (p.u.)

Phase (deg) Magnitude (dB)

Chapter 2 State-of-the-Art in Grid Synchronization

-5

-84

-86

D(z)

-88

-90

1
A(z)

0.5

0
-0.5

A(z)
-1

-92
-94

-96 47

48

49

50

51

52

53

-1.5
0.018

Frequency (Hz)

Figure
2.27:
Comparative
(fs = 10 kHz, so n = 50 in D(z)).

of

the

0.02

0.022

dynamics

0.024

0.026

0.028

Time (s)

of

A(z)

0.03

0.032

and

0.034

D(z)

As shown in Fig. 2.26, the pre-filtering is at the real time generation of Q+ . A 90 deg
delay at f1n is applied to get the implementation of (2.24). This delay is obtained as a
FIR filter of the form

D(z) =

1
zn

(2.26)

n being the order of the filter, which is so that D(z) has 90 deg of delay at f1n . D(z)
has unitary gain for all the frequencies and linear phase, so it can also be considered an
all-pass filter.
Fig. 2.27 shows a comparison between D(z) and A(z). It is expected a faster transient
response of DSC method, but a worse frequency adaptation.

2.3.2.2.3 Generalized Integrators in PLLs Generalized Integrators (GIs) have

been employed in the control of power converters because they have a very high gain
at a desired harmonic frequencies; e.g. their implementation in Proportional+Resonant
(PR) current controllers [44, 88, 118122]. The use of damped GIs have been proposed
by Rodriguez et al as SRF-PLL pre-filters in the frame [123].
The generic form of a GI is:

G(s) =

N um(s)
.
s2 + k 0 s + 0 2
0

(2.27)

From (2.27), G(s) has a maximum at (s2 + = 0). When k 6= 0 the GI is said
to be damped. The numerator of G(s) (N um(s)) is set so that the frequency response,
0
specially at , is the expected. Two GI filters were proposed in [123]: a direct GI (Hd (s))

75

2.3 Phase Locked Loops

and a quadrature (Hq (s))

Hd (s) =

k1n s
,
2
+ k1n s + 1n

(2.28)

2
k1n
,
2
s2 + k1n s + 1n

(2.29)

s2

with a 0 deg phase at f1n = 50 Hz, and

Hq (s) =
with a 90 deg phase at f 1n = 50 Hz.

So Q+ is implemented in real time (even though expressed in the S-domain) as:

Q+ =

Hd (s) Hq (s)
Hq (s)

Hd (s)

(2.30)

Fig. 2.28a shows the frequency response of both filters. At f1 = 50 Hz both filters
have unitary gain; in terms of phase, Hd (s) = 0 deg and Hq (s) = 90 deg at 50 Hz; Hq (s)
has a better harmonic filtering response since it decays 40 dB/dec. The settling times (ts )
of both filters last around one fundamental cycle, what lags the transient considerably.

2.3.2.2.4 Extended and Generalized Delayed Signal Cancellation As shown,

the real time generation of the Fortescue operator (S+ ) is obtained from delayed signals:
the complex operator i is implemented by delaying 90 deg the fundamental component of
the input signal.
However, when digital delays of the form (2.26) are implemented, the equivalent phase
at harmonic frequencies is different. Indeed, these are linear-phase filters. Therefore, at
some harmonic frequencies and sequences the implementation of S+ results in harmonic
cancellation [124].
On the other hand, the real time generation of S+ with delayed signals is not unique.
Taking advantage of this feature, different combinations of the fundamental component
positive-sequence reconstruction can be linked in order to cancel some harmonic sequences
in the frame [124].
The proposal of [124] has been generalized by Bradaschia et al in [111]. Through
mathematical operations in the frame, they prove that any sequence (positive or
negative) at any harmonic of the fundamental frequency (odd and even) can be canceled
choosing the correct S implementation and/or link of some of them.

76

Chapter 2 State-of-the-Art in Grid Synchronization

Magnitude (dB)

10

0
-10
-20
-30
-40

Phase (deg)

-50
90

0
-90
-180
0
10

10

50
Frequency (Hz)

10

(a) Hd (s) and Hq (s) frequency response (k =

10

2).

500

300

200

100

-100
0

0.005

0.01

0.015

0.025

(b) Hd (s) and Hq (s) impulse (transient) response (k =

0.03

2).

Figure 2.28: Hd (s) and Hq (s) dynamic response.

2.3.3

Digital Single-phase PLL

The suitability of digital implementation allows to implement PDs with a higher performance than the CP-PLLs ones, which are based on zero-cross detection. From PLL
theory [78, 79], the linear multiplier PD seems to be the most intuitive option [112, 125
128]. Fig. 2.29 shows a simple single-phase PLL scheme based on linear multiplier as PD.
For the linearization, the input signal of equation (2.31) is considered:

v = v1max sin(1 t + 1 ) + f (3i , 5i , 7i , ...) p.u..

|

{z
1

(2.31)

77

2.3 Phase Locked Loops

va ( p.u.)

PD

1e

LOOP FILTER

1n

+ +

DCO

cos(1 )
sin(1 )

cos(u)

sin(u)

Figure 2.29: Single-phase PLL with multiplier as PD.

The wave at the PD output is

cos(1 )
| {z }

v1max
(sin(1 1 ) + sin(1 + 1 )) + f (2i , 4i , 6i , ...).
2

(2.32)

F eedback wave

Again, assuming that the PLL is locked in steady-state 1 =

1 and 1 1 [78, 79],

v cos(1 )

v1max
sin(1 1 ) +
| 2
{z
}
1
1 =1e

v1
+ max sin(21 t + 21 ) + f (21 , 41 , 61 , ...) .
|
{z
}
| 2
{z
}
Generated second harmonic

(2.33)

Other harmonics

Equation (2.33) shows that in steady-state the wave has a small dc signal with the
phase error information (1e ), a high second harmonic and other even harmonic components. Assuming that all the harmonic components are canceled in the LF, the linearized
model is also valid for single-phase PLLs.
Other alternatives for single-phase PLL implementation have been proposed, such as:
The adaptation of the SRF-PLL to single-phase systems [129133].
The implementation of a more complex PD such as the one of the Enhanced PLL
(EPLL) of [134], or the one based on the Coullon Oscillator [135]7 .
However, all single-phase PLLs for grid applications need of a drastic bandwidth reduction due to the PD non-linearities, more specifically the internal generation of harmonics
7

Even though the title could be misleading, [135] proposes a single-phase PLL

78

Chapter 2 State-of-the-Art in Grid Synchronization

at 21 . Therefore, grid-connected single-phase PLLs should not be considered fast, so

that they are low-gain PLLs. In fact, their typical settling times are not lower than 1
cycle of 1n [112, 126, 127, 133136].

2.3.4

Single-phase PLLs Vs SRF-PLLs

+
. On
As said, in a three-phase system the SRF-PLL estimates the phase-angle of va1
the other hand, a single-phase PLL connected in the a-phase tracks the phase-angle of va1 .
Therefore, it seems that SRF-PLLs are more reliable when SRF controllers are employed.
That is, the use of single-phase PLLs in the presence of negative/zero sequences may
result in 1e 6= 0 when tracking the positive-sequence, which may lead to a non efficient
energy transfer control. Some works have proposed the use of single-phase PLLs instead
of SRF-PLLs, since a SRF-PLL cannot detect individual phases [126, 135]. Even though
this assessment could be right, SRF controllers do not seem the most suitable to work
together with single-phase PLLs. This point should have been clarified by those authors.
It could be said that single-phase PLLs are more suitable for single-phase circuits and
three-phase circuits with per-phase controllers.

Other authors suggest a per-phase estimation of va1 , vb1 and vc1 phase-angles and
+
amplitudes in order to calculate the phase-angle of va1
[134]. Even though this is feasible,
there is no apparent reason to use individual single-phase PLLs, since the phase-detector
+
of the SRF-PLL (P+
1 ) totally decouples the positive-sequence: the dc value of vdq1 only
+
depends on vabc1 .

2.3.5

Amplitude Compensation in Digital PLLs

When considering amplitude variations such as voltage sags and swells, the drawback
of amplitude dependence in PLLs appears: from (2.19) and (2.33), it is clear that the
dynamics of digital PLLs depends on the amplitude of the tracked signal. In fact, the
amplitude is considered a proportional gain, which is normalized to 1 p.u. in order to
make easier the tuning process.
The amplitude dependence may lead to instability when the PLL phase margin is too
low. However, in practice, the most reported problem is due to the slow dynamics in the
presence of voltage sags [126, 127, 137].
This amplitude dependence can be avoided in part by compensating the PLL input
with an amplitude estimation. In single-phase PLLs, some works propose an extra loop
tracking the amplitude, which could be named amplitude locked loop (ALL) [126, 127,
136]. Similar approaches have been proposed for the SRF-PLL [111, 137].
Fig. 2.30 shows the combined ALL-PLL structure proposed in [127]. As a general

Software Phase Locked Loop

79

2.3 Phase Locked Loops

v 1 max

sin(1t + 1 )

Amplitude
Locked
loop.

Phase
Locked
Loop.

v / v 1 max

(a) ALL-PLL global structure.

sin(1t + 1 )
u2

PI

+-

1
X
+

1/u
X

v 1 max

v / v 1 max

(b) ALL block.

Figure 2.30: ALL-PLL compensation block.

rule, the ALL closed loop bandwidth should be lower than the PLL one, because of the
fact that the amplitude measurement also depends on the phase-angle.
Fig. 2.31 shows experimental results from the ALL-PLL structure. When there is a
voltage sag, the dynamics is faster and the amplitude can be estimated in real-time.
However, the range of improvement achieved with this technique could be considered
quite limited. In sum:

In the single-phase case, the dependence between loops limits the response. The
study of the combined dynamics is very difficult [127].
Also in the single-phase case, the bandwidth of the PLL should still consider the
PLL second harmonic [126, 127].
If a division block is implemented, division by zero or low values could result in
instability.

2.3.6

Limit Cycles of Digital PLLs

Digital PLLs are non-linear systems. Their trajectories can be depicted in the so-called
phase plane portraits [138, 139]. The frequency error 1
1 is represented in the Y axis

and the phase error 1 1 in the X axis. During normal operation, it is expected from a

80

Chapter 2 State-of-the-Art in Grid Synchronization

SPLL amplitude during a 0.5 p.u. sag with a +45 deg. phase-angle jump.
1.1

Amplitude (p.u.)

0.9

0.8

0.7

0.6

0.5

0.4
0.1

0.15

0.2

0.25

0.3

0.35

Time (s)

(a) ALL-PLL response to a 0.5 sag with

phase-angle jump of +45 deg. (v gray dashed, v1
black solid).

(b) v1max obtained with the ALL (v gray

dashed, v1 black solid).

Figure 2.31: Key figures of the ALL-PLL.

PLL to converge to the limit cycle (0, 0). Other solutions of the difference equation defined
by the PLL are expected to be unstable limit cycles. If not, a misleading estimation could
lead to malfunctions of the power electronic converter.
Different parameters of the PLL set its phase-plane portrait: the loop filter, the feedforward constant, the word length and other non-linear operations. It should be noticed
that the effect of these parameters cannot be assessed through the PLL linearized model.
Some digital implementations could lead to non desired stable limit cycles (misleading
steady-state estimations). In order to avoid this, the PLL region of operation can be
delimited explicitly.
A study of the phase-plane trajectories of a SRF-PLL is contributed in this section.
The influence of some parameters is shown. Fig. 2.32 shows phase-plane portraits obtained for a SRF-PLL implementation. The Matlab script employed to depict these portraits is in appendix A.4. The different curves are obtained considering different initial
conditions of 1 (color legends). Initially this implementation does not take into account
negative values of
1 , that is, the sign of
1 is obviated in the integration step to get 1 .
This action can be considered attractive under the resources point of view, especially in
a fixed point implementation where the word length is very limited. Fig. 2.32a and 2.32b
show the phase-plane portrait with and without feedforward constant. Some important
results are obtained from these figures:
1. A stable limit cycle appears at (21 , ) when the sign of
1 is obviated. The
outcome of such a wrong estimation in a real time controller could be unpredictable.

81

2.3 Phase Locked Loops

1000

1000

-0.1
/2
/4
0
/2
-+0.6
-+0.1

-500
-4

-3

-2

-1

-0.1
/2
/4
0
/2
-+0.6
-+0.1

-500
-4

-3

-2

-1

(a) Phase-plane portrait of a SRF-PLL obviating (b) Phase-plane portrait of a SRF-PLL obviating

1 sign. Feedforward constant implemented (1n =

1 sign. No feedforward constant (1n = 0).
2 50 rad/s).
1000

1000

-0.1
/2
/4
0
/2
-+0.6
-+0.1

-500
-4

-3

-2

-1

-0.1
/2
/4
0
/2
-+0.6
-+0.1

-500
-4

-3

-2

-1

(c) Phase-plane portrait of a SRF-PLL with

1 sign (d) Phase-plane portrait of a SRF-PLL with
1 sign
information (1n = 2 50 rad/s).
information. The LF path is limited by the word
length (1n = 2 50 rad/s).

Figure 2.32: Phase-plane portraits of a SRF-PLL implementation. The curves are obtained through different initial conditions (color legends indicate the initial 1 ).
2. Thanks to the feedforward constant there are more trajectories converging to the
good limit cycle (0, 0), but the malfunction remains to be quite likely.
Fig. 2.32c shows the phase-plane portrait considering
1 sign. In such a case, (21 , )
is an unstable limit cycle and the SRF-PLL converges to the good estimation. Fig. 2.32d
shows the effect of the word length consideration. The trajectories in the phase-plane
portrait are limited in a smaller region.
Returning to the theoretical approach, a high presence of harmonics may result in a
PLL tracking a harmonic phase. Another real possibility is a non converging PLL. E.g.
a single-phase PLL based on a multiplier may lead to a solution where
1 = 0 (1e = 0)
and, therefore, the X axis is 1 .
It could be said that, in general, the region of operation of the PLL should be limited
in order to avoid non desired stable limit cycles and diverging trajectories. In practice,
the best manner to limit the region of operation is by placing the feedforward constant
and limiting the word length [112].

82

Chapter 2 State-of-the-Art in Grid Synchronization

2.4

Digital Alternatives to PLLs

The main drawback of PLLs is their transient response speed, specially in the presence
of distorted conditions [91, 134, 140]. On the other hand, digital implementation allows
to implement very high performance synchronization algorithms without a DCO inside a
closed-loop (a digital PLL).
Several algorithms have been proposed as an alternative to PLLs. The most significant
approaches are analyzed in this section. It should be highlighted that some of these
proposals are novel contributions of this thesis.

2.4.1

Filtering in the Frame

Some algorithms based on the Clarke transformation are analyzed below.

2.4.1.1

Transformation Angle Detector (LP-TAD)

An open loop system, named low-pass transformation angle detector (LP-TAD), able
to synchronize with the positive-sequence of the fundamental vector of a three-phase
voltages/currents system was presented in [141]. This system was proposed as a digital
alternative to CP-PLLs for VSIs based on vector control, where the performance of zerocross detectors was very poor in the presence of input harmonics.
Fig. 2.33 shows the scheme of LP-TAD. A three-phase system of voltages system
(va , vb , vc ) is transformed to its equivalent Clarke variables v and v :

{z

va

2 1 0.5 0.5

vb .
3
3

3 0
2
2
vc
|
{z
}
C

{z

~vabc

(2.34)

Assuming that there is not negative-sequence at fundamental frequency, the phaseangle of the positive-sequence is estimated from v1 and v1 , obtained by filtering harmonics from ~v , through:

1 = atan2(
v1 , v1 ) [, ],
where atan2 is the four-quadrant inverse tangent [142].

(2.35)

83

2.4 Digital Alternatives to PLLs

v

va
vb
vc

LPF

v 1
2

v 1 + v 1
LPF

norm
x v 1

v
x

v 1

norm
1

(atan2)

Figure 2.33: LP-TAD scheme.

X

As said, LPFs are placed in order to filter higher harmonics;

they should be tuned
DCO
taking into account the trade-off between filtering and transient
response.
Filters delay
+ +
should be compensated at the outputs, which is not a trivial issue considering
frequency
1n

variations [105].

Fig. 2.34 shows some significant simulation results of the LP-TAD. For these simulations an order 1 Butterworth filter with cut-off frequency 15 Hz has been employed.
As shown, the LP-TAD has a good behavior under balanced conditions. However, it
has a very poor performance in the presence of negative-sequence in the inputs. This lack
of sequence decoupling ability is due to fact that the Clarke variables include information
of both positive and negative sequences [21]. The transient response depends only on the
employed LPFs.
The LP-TAD proves that open loop schemes and inverse trigonometric functions
(atan2) could be an alternative to PLLs if a good decoupling and filtering strategy is
carried out.
Also in [141], the dynamic response of the LP-TAD is enhanced by using recursive/stochastic filters, giving rise to the Space Vector Filter-TAD (SVF-TAD) and Enhanced Kalman Filter-TAD (EKF-TAD). Stochastic filtering for synchronization is analyzed below.

2.4.1.2

Normalised Positive-sequence Synchronous Frame (NPSF)

In [143, 144] a scheme to decouple the positive-sequence and then synchronize in the
frame is shown. S+ is implemented using GIs to get 90 deg delay at nominal frequency.
Once decoupled the positive-sequence, open loop estimation is accurate. However, like in
the GI based PLLs, the transient response is not its strongest point.

84

Chapter 2 State-of-the-Art in Grid Synchronization

1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0.47

0.48

0.49

0.51

0.52

0.53

0.54

0.53

0.54

(a) Input waves.

0.8

norm

0.6
0.4

norm

0.2

-0.2

norm

-0.4
-0.6
-0.8
-1
0.47

0.48

0.49

0.51

0.52

(b) Normalized e and v .

-1

-2

-3
0.47

0.48

0.49

0.51

0.52

0.53

0.54

(c) Phase-angle measurement.

Figure 2.34: Significant simulation results for LP-TAD: fault and unbalance conditions.

85

2.4 Digital Alternatives to PLLs

2.4.2

Filtering in Synchronous Reference Frames

Digital devices allow to handle electrical variables in SRFs. The main advantage of
the SRF approach is the suitability of controlling oscillating waves as dc signals. This is a
big advantage under the designer point of view, since low order infinite impulse response
(IIR) filters (Chebishew, Butterworth), moving average FIR filters (MAF), Proportional
Integrator (PI) controllers, lag/lead controllers, etc, perform much better with dc signals
[12, 44, 58, 145].
It is shown in this section how to implement SRF schemes in order to obtain high performance synchronization algorithms. Firstly, algorithms to synchronize with the fundamental components are analyzed, both for single-phase and three-phase systems. Special
emphasis is put on the proposal of using MAFs together with SRF schemes, which is a
major contribution of this thesis [146148]. Later, the issues of harmonics and negativesequences extraction based on SRFs are approached [13, 19, 148151].

2.4.2.1

Single-phase SRF Synchronization Algorithms

It is considered that the input wave (v) is a single-phase wave with multiple harmonics

v = v1max sin(1 t + 1 ) +v3max sin(31 t + 3 ) + v5max sin(51 t + 5 )+

|

{z
v1

(2.36)

+ v7max sin(71 t + 7 ) + ...

v1 is the fundamental component and rotates at 1 ; from Fourier theory, it can be

expressed as the sum of two orthogonal waves also rotating at 1 . These two waves
rotating at a frequency srf = 1 , named d (direct) and q (quadrature), set a single-phase
SRF.

v1 = vd1 sin(1 t + srf ) +vq1 cos(1 t + srf ) .

|

{z
d

{z
q

(2.37)

It is important to note that (2.37) is valid for any srf ; Fig. 2.35 depicts v1 in the
SRF.
Fig. 2.36 shows a generic SRF scheme suitable for reconstruction of v1 . The goal of
the SRF algorithm is to measure v1d and v1q , which are dc values, in order to reconstruct
v1 and estimate its phase-angle (1 ). The frequency of the implemented SRF (srf ) sets

86

Chapter 2 State-of-the-Art in Grid Synchronization

v q1
v1

vd1

Figure 2.35: v1 in the single-phase SRF.

1
srf

sin(u)

srf = srf t + srf

Open Loop Synchronous
Reference Frame generation

f (dc,21 ,41 ,...) f (dc)

cos(u)
q

2H(z)LPF

)
vd 1

2H(z)LPF )

vq1

v1

Figure 2.36: Single-phase SRF synchronization algorithm: srf = 1 to decouple v1 .

the component to reconstruct; as said srf = 1 is set in order to track v1 . The input
wave (v) is multiplied by the d and q, yielding the following results:

1
v sin(srf ) = [v1 cos(1 srf ) + v1 cos(srf + 1 ) + v3 cos(3 srf ) +
{z
} |
{z
}
2|
vd1

rotating at 21

(2.38)

v3 cos(3 srf ) + v5 cos(5 srf ) +...],

|

{z

rotating at 41

1
v cos(srf ) = [v1 sin(1 srf ) + v1 sin(srf + 1 ) + v3 sin(3 srf ) +
{z
} |
{z
}
2|
vq1

rotating at 21

(2.39)

v3 sin(3 srf ) + v5 sin(5 srf ) +...].

|

{z

rotating at 41

From (2.38) and (2.39), it is expected that vd1 and vq1 , which are dc coefficients, can

87

2.4 Digital Alternatives to PLLs

be obtained with no ripple by means of LPFs. After the filtering stage, v1 is reconstructed
using (2.37). The estimated phase-angle of v1 (1 ) is:
1 = srf + atan2(
vq1 , vd1 ),
|

{z

(2.40)

(relative angle)

where is a relative phase-angle in the SRF, which is function of srf . v1max is estimated
by

v1max =

2
2
vd1
+ vq1
.

(2.41)

From Fig. 2.36, it is clear that the dynamics of this system depends only on the LPFs.

2.4.2.2

MAF as LPF for SRF based Schemes

The most important feature of a LPF is its amplitude versus frequency response. In
this particular case, unitary gain for low frequency values and high attenuation at higher
frequencies, specially for harmonics, are wanted. A filter with this frequency response
is relatively easy to design and implement in current digital devices. However, another
important feature of the LPF is its step response. The step response sets the system
response to a transient. In filtering there is a trade-off between the cancellation pattern
and the step-response [152].
MAFs have been implemented in electric power applications because of their excellent
behavior canceling harmonics [153157]. In this work, it is shown how MAFs also offer a
very optimized performance for grid synchronization [146148].
The difference equation which defines how the input signal (x) is related with the
output signal (y) of a FIR filter is:

y(k) = b0 xk + b1 xk1 + .... + bn1 xkn1 =

n1
X

bi xki ,

(2.42)

i=0

where k represents the current number of sample, bi are the filter coefficients and n 1
is the filter order, so n must be an integer number. The window length, or time length,
(tw ) of a FIR filter is set by the number of samples, and the sampling time (1/fs ):

tw = n

1
.
fs

(2.43)

An important feature of some FIR filters is the linear-phase [158]. A FIR filter is

88

Chapter 2 State-of-the-Art in Grid Synchronization

linear-phase if and only if its coefficients are symmetrical around the center coefficient; in
such a condition the delay through the filter (td ) is function of n:

td =

n 1
.
2 fs

(2.44)

As shown in chapter 4, this linear-phase feature is key in the optimization of SRF

based synchronization algorithms.
A particular case of linear-phase FIR filters are MAFs, which implement the average
function over the last n samples. The filter coefficients of the MAFs are found via the
following equation:

b(i)i=0,..,n1 =

1
.
n

(2.45)

Eq. (2.42) can be expressed in the Z domain as

Y (z) = H1 (z) X(z) =


1 
X(z) + X(z)z 1 + .... + X(z)z (n1) =
n

X
1 n1
z i X(z),

n i=0
!

(2.46)

H1 (z) being the Z domain transfer function relating the input and output of the filter.
From (2.46) and through the basic properties of the Z transform, a more suitable for
implementation form of H1 (z) is obtained:

H1 (z) =

1 1 z n
.
n 1 z 1

(2.47)

The magnitude versus frequency response of H1 (z) is mathematically described by the

Fourier transform of a rectangular pulse of amplitude 1/n and duration n samples in the
time domain:

M ag [H1 (f )] = M ag

sin( ffsn )
n sin( f
)
fs

(2.48)

where f is defined in the range [0, fs /2] [159].

In grid applications, a cancellation of the even harmonics of f1 = f1n = 50 Hz is
expected (100, 200, ... Hz). From (2.48), the n value canceling all the even harmonics is

89

2.4 Digital Alternatives to PLLs

derived:

n=

fs
,
2 f1n

(2.49)

n being an integer number, since it sets the order of a digital filter; hence, fs should be
an integer multiple of 2 f1n .
Fig. 2.37 shows the features of a MAF with fs = 10 kHz and n = 100 [146].Fig 2.37a
shows that the even harmonics of f1n are canceled and the gain is also very low around
these frequencies. The linear-phase feature can also be noticed. Figs. 2.37c and 2.37d
show the impulse and step responses set by (2.43), in this case 0.01 s.
Figs. 2.37e and 2.37f show a comparative among different kinds of discrete filters extracted from [148] 8 . As shown, the MAF has a very good cancellation pattern considering
grid applications (odd harmonics) and very good transient response.
Fig. 2.38 shows the very good performance of the SRF and MAF based algorithm,
which is named SRF-MAF1.
These simulations have been carried out considering srf = 1 = 1n . In a practical
environment frequency deviations should be taken into account, as shown in section 2.5.

Butt(2,10 Hz) means: second order filter of type Butterworth, with cut-off frequency equal to 10 Hz.

Chapter 2 State-of-the-Art in Grid Synchronization

1.0002

Magnitude (abs)

1
0.8
0.6

1
0.9998

0.9996

0.4

0.9994

0.2

0
0

0.9992

-45
-90
-135

-180
0

Phase (deg)

Phase (deg)

Magnitude (abs)

90

50

100

150

200

250

300

350

400

450

500

Frequency (Hz)

-1
-2
-3

-4
0

550

(a) Frequency response (in Hz).

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Frequency (Hz)

(b) Fig. 2.37a zoomed around dc (in Hz).

0.01

0.009

Amplitude

Amplitude

0.008
0.007
0.006
0.005

0.8

0.6

0.004

0.4
0.003
0.002

0.2

0.001

0
0

0.002

0.004

0.006

0.008

Time (sec)

0.01

0.012

00

0.014

0.002

0.004

0.01

0.012

0.014

(d) Step response (tw = 0.01 s).

Butt(2,30Hz)

Amplitude (p.u.)

0.9
0.8

Gain

0.008

Time (sec)

(c) Impulse response (tw = 0.01 s).

0.7

0.006

0.8

Butt(2,30Hz)

0.6
0.5

Butt(2,10Hz)

MAF

0.6

Butt(1,10Hz)

0.4
MAF

0.3

1 STEP

Butt(1,30Hz)

0.4

0.2

0.2

0.1
Butt(2,10Hz)
0
0

50

100

150

200

250

300

350

400

0
0.15

0.2

0.25

0.3

0.35

0.4

Time (s)
Frequency (Hz)
(e) Comparative with other filters (Frequency Re- (f) Comparative with other filters (Step/transient
sponse.)
response.)

Figure 2.37: Time and frequency responses of H(z)1 implemented at fs = 10 kHz and
n = 100.

91

2.4 Digital Alternatives to PLLs

1
0.8
0.6
0.4

1
0.2

0
-0.2
-0.4
-0.6
-0.8
-1

0
1

0.01

0.02

0.03

0.04

0.05

0.06

1max

0.8

d1

0.6
0.4
0.2

0
q1

-0.2
-0.4
-0.6
-0.8
-1

0.01

0.02

0.03

0.04

0.05

0.06

0.04

0.05

0.06

3
2

0
-1

-2

-3

0.01

0.02

0.03

Figure 2.38: Simulation results for SRF-MAF1 working open loop (srf = 1 = 1n ).

92

Chapter 2 State-of-the-Art in Grid Synchronization

SRF-MAF1

Taps

a N 1

z 1

.
.
.

a2
a1
a0

Magnitude (dB)

Impulse

10

.
.
.
X

z 1
X

v
HDCT(z) (on-line)

n=100
n=200

-20
-30

-50
180

z 1
X

0
-10

-40

v1

Phase (deg)

FIR generation
(off-line)

90

0
-90
-180
0

50

100

150

200

250

300

Frequency (Hz)

350

400

450

500

(a) Technique to obtain FIR taps from the impulse (b) SRF-MAF1 with n = 100 and n = 200 (=RDFT
response.
of [158]); srf = 1n .

Figure 2.39: DCT based implementation figures.

2.4.2.3

Equivalent Implementations

It should be commented that, even though the theoretical approach proposed by McGrath et al in [158], based on a Recursive Discrete Transfer Function (RDFT) and SRFMAF1 are different, their implemented schemes could be considered equivalent (Fig. 2.36
vs Fig. 2 of [158]). It can be checked analytically that, even though both schemes seem
to be non-linear, they could be also implemented as linear filters based on the Discrete
Cosine Transform (DCT). In this manner:
X
2 n1
cos(1 k Ts )z k .
HDCT (z) =
n k=0

(2.50)

HDCT (z) taps can be also obtained through the impulse response of SRF-MAF1 (or
RDFT-based) as depicted in Fig. 2.39a. Fig. 2.39b shows the frequency response of the
DCT filters obtained from SRF-MAF1 with n = 100 and n = 200, which is equivalent
to the RDFT based scheme of [158]. As expected, the double window length provides a
better filtering at the cost of doubling the transient time.
It is a common practice to neglect even harmonics in system voltages/currents, which
is accurate for the most of practical electric circuits [27, 97, 160165]. Therefore, it could
be said that SRF-MAF with n = 100 seems to be a more efficient alternative. Indeed,
it takes advantage of the potential DCT half-cycle window, which is the main advantage
of the DCT over the DFT [166]. Another advantage of the DCT (half cycle) over DFT
appears when frequency deviations are considered [166]: as can be observed in Fig. 2.39b,
when the input wave is not rotating at nominal frequency DFT (or DCT with n = 200)
phase error doubles the DCT one.

93

2.4 Digital Alternatives to PLLs

f (dc, 2 , 4 ,...)

va

H(z)LPF

vb

P1+

vc

srf

H(z)LPF

vd+1
vq+1 P + (-1)
1

va+1
vb+1
vc+1

srf = srf t + srf

Open Loop Synchronous
Reference Frame Generation

+
.
Figure 2.40: Three-phase SRF synchronization algorithm; srf = 1 to decouple vabc
1

On the other hand, several works in other signal processing fields (image, speech,
communications,...) proved that the IIR equivalent implementation to a DCT are GIs,
as the ones of section 2.3.2.2 [167170]. The main advantage of such IIR over FIR filters
appears mainly when considering very large scale integration (VLSI) implementations;
the transient response does not seem an important issue in those works. However, for
electric power applications, the performance of FIR based implementations results in a
much better filtering versus transient response trade-off, as shown in this dissertation.

2.4.2.4

Three-phase SRF Synchronization Algorithm

A three-phase synchronization in the SRF can be obtained by the Park transformation

matrix P+ for the positive-sequence with a random phase-angle; srf = 1 should be
chosen in order to decouple the fundamental positive-sequence from vabc , so

) sin(1 t + srf + 2
)
2 sin(1 t + srf ) sin(1 t + srf 2
3
3

P+
=
1
2
2
3 cos(1 t + srf ) cos(1 t + srf ) cos(1 t + srf + )
3
3

(2.51)

is implemented.
Fig. 2.40 shows a suitable scheme for three-phase systems. LPFs are employed to
+
+
cancel ripple from the dc coefficients vd1
and vq1
. The inverse of P+ is used to estimate
+
vabc . When using MAFs, the name SRF-MAF3 refers to the algorithm depicted in Fig.
2.40.

94

Chapter 2 State-of-the-Art in Grid Synchronization

+
The phase-angle and amplitude of vabc
are estimated by

+
+
1 = (1n t + srf ) + atan2(
vq1
, vd1
),

{z

srf

{z

(2.52)

(relative angle)

and

+
va1
=
max

+
+
.
vd1
+ vq1

(2.53)

The phase-angle estimation can also me made by using the angle transform B+(1) to
+
and v+ so the offset angle is not needed for 1 assessment [147].
get v1
+
+
, v1
) [, ].
1 = atan2(
v1

(2.54)

Fig. 2.41 shows simulation results of SRF-MAF3 and n = 100. The good performance,
both in steady and transient states is proved when ideal conditions are considered.

2.4.2.5

SRF-MAFs for Harmonics and Negative-sequences Extraction

Previous approaches showed how to decouple the fundamental component of singlephase signals and the fundamental positive-sequence of three-phase systems. In the same
way, higher harmonic components can be decoupled using the expression srf = h1 ,
where h is the order of the selected harmonic. Negative-sequences can be decoupled by
means of P and its inverse. [1215, 19, 148151].
These approaches are specially suitable for power line conditioners. SRF-MAFs have
been successfully implemented as extraction algorithms in [148151].
SRF-MAFs for selective harmonic extraction have been implemented in the APF controller analyzed in chapter 5. Even though the main part of this chapter is devoted to the
PR current controller block, experimental results prove the excellent performance offered
by the SRF-MAF based extraction, both in steady-state and in the presence of input
transients.

95

2.4 Digital Alternatives to PLLs

1.5

Amplitude (p.u.)

Vc

Va

Vb

0.5

-0.5

-1

-1.5

0.01

0.02

0.05
0.04
Time (s)

0.03

^ +
V
a1
^
V

0.8

0.07

0.08

0.06

0.07

0.08

+
b1

0.6

Amplitude (p.u.)

0.06

^ +
V
c1

0.4
0.2

0
-0.2
-0.4
-0.6
-0.8
-1

0.01

0.02

0.05
0.04
Time (s)

0.03

Phase-angle (rad)

1
1

0
-1

-2

-3

0.01

0.02

0.03

0.05
0.04
Time (s)

0.06

0.07

0.08

Figure 2.41: Simulation results for SRF-MAF3 working in open loop (srf = 1 = 1n ).

96

Chapter 2 State-of-the-Art in Grid Synchronization

2.4.3

Stochastic Filtering based Synchronization Schemes

Digital devices allow to implement online recursive filters such as Kalman and adaptive
filters [171, 172]. The problem of synchronization with a polluted wave can be posed as
the linear-quadratic-Gaussian control problem [171] or as the Wiener problem of state
estimation [172]. Quite significant proposals in synchronization and harmonic extraction
based on stochastic filtering are present in technical literature [48, 140, 141, 173181].
The most interesting feature of stochastic filtering based algorithms is their potential
fast transient response, even in the presence of some distorted conditions. For this reason,
they were mainly proposed to work in applications where the transient response is crucial
such as Uninterruptible Power Suppliers (UPSs), Dynamic Voltage Restorers (DVR),
traction systems, relaying protecting and harmonic identification [48, 140, 173178, 182].
A global sight of synchronization algorithms based on stochastic filtering is detailed
as follows, both for single-phase and three-phase systems.

2.4.3.1

Kalman Filtering

The Kalman filter is an efficient recursive filter that estimates the state of a dynamic
system from a series of noisy measurements. Kalman filters in grid applications have
been employed as extraction algorithm in [183] (off-line) and [145, 173, 181, 182, 184]
(real time). Relating to the scheme of Fig. 2.33, the EKF-TAD of [141] obtains v and
v in a recursive manner, rejecting noise and harmonics in v and v .
It should be highlighted here that the EKF-TAD does not decouple negative-sequences,
while the Kalman based SRF schemes of [145] do it. In general, it cannot be asserted
that stochastic filtering schemes proposed novel architectures. It seems more suitable
to say that they provided a novel approach to digital filtering. In fact, MAFs 9 and
IIRs are also recursive filters. Therefore, it could be said that the manner in which
the synchronization or extraction problem is posed is much more important than the
stochastic filter coefficients.

2.4.3.1.1 Single-phase Example A very simple single-phase example to show Kalman

filtering features is provided in this section. The discrete Kalman model with stationary
reference for identification of the fundamental component (v1 , rotating at 1 ) of a singlephase wave (v) can be written as:

x(k + 1) = M x(k) + W(k) (State equation),

9

(2.55)

Even though MAFs are FIR filters, usually they are implemented as IIR structures using (2.47).

97

2.4 Digital Alternatives to PLLs

M being

M=

cos( fs1 )

sin( fs1 )

sin( fs1 ) cos( fs1 )

(2.56)

and

v1 (k) = H x(k) + V(k) (M easurement equation),

(2.57)

H = [0 1].

(2.58)

H being

W (k) and V (k) are the stochastic processes of the system noise and measurement
noise, respectively. System covariance matrices for W (k) and V (k) are assumed as
E[W (k) W (k)T ] = q and E[W (k) W (k)T ] = r. The error covariance matrix (p) is
T ]. The second coefficient of

updated in each step; its initial value is p(0) = E[X(k)

X(k)
x(k) is v1 estimation.
The sequential recursive computation steps for v1 estimation are:

1. Compute of Innovation Matrix (I):

I = v(k) H x(k).

(2.59)

2. Compute of Covariance of Innovation (s):

s = H p(k) HT + r.

(2.60)

K = M p(k) HT s(1) .

(2.61)

x(k + 1) = M x(k) + K I.

(2.62)

3. Compute of Gain Matrix (K):

4. State estimation:

5. Update of the error covariance matrix p:

p(k + 1) = M p(k) MT + q M p(k) HT s(1) H p(k) MT

(2.63)

98

Chapter 2 State-of-the-Art in Grid Synchronization

1
0.8

0.8

1
0.6

0.6

0.4

0.4

0.2

0.2

-0.2

-0.2

-0.4
-0.4

-0.6
-0.6

-0.8
-0.8

-1

-1
0.01

0.02

0.03

0.04

0.06

0.07

0.08

0.01

0.09

0.02

0.03

0.04

0.06

0.07

0.08

0.09

0.06

0.07

0.08

0.09

1
-1

-1

-2

-2

-3

-3
0.01

0.02

0.03

0.04

0.06

0.07

0.08

0.09

(a) Test for an input with noise and 0.5 p.u. sag
with 45 deg phase jump.

0.01

0.02

0.03

0.04

(b) Test for an input with harmonics.

Figure 2.42: Single-phase Kalman based synchronization algorithm.

The filtering pattern and dynamic response of the Kalman process mainly depend on
the initial values of the covariances. Of course, there is a trade-off between filtering and
transient response. The phase-angle of v1 for each k instant is obtained by

1 = atan2(
x1 , x2 ) [, ].

(2.64)

Figs. 2.42a and 2.42b show some significant results for the Kalman filtering synchronization method obtained through the Matlab Script detailed in appendix A.5. These
simulations have been carried out considering
1 = 1 = 1n , which is revised in section
2.5.
These results show that the Kalman filter approach is suitable for grid synchronization, since it can offer an acceptable filtering versus transient response, specially when
comparing with single-phase PLLs.
The dynamics this Kalman based synchronization algorithm can be set in a different
manner by means of the intial parameters which set the system gain K (see appendix
A.5). Furthermore, by introducing higher harmonic components in the M matrix, the
filtering response can be enhanced at the cost of increasing computational burdens [183].

99

2.4 Digital Alternatives to PLLs

2.4.3.2

Weighted Least-Squares Estimation (WLSE) algorithms

Song et al proposed the implementation of a recursive least squares (RLS) adaptive

filter, named Weighted Least-Squares Estimation (WLSE), adapted to the synchronization
problem [140, 176178]. The WLSE algorithms approach the problem of synchronization
in an elegant way, so the dynamics of the system mainly depends on the so-called forgetting
factor .
Firstly, the problem was posed for three-phase systems with negative-sequence [140,
176]: usually, after a voltage sag, there is a phase-jump and unbalance (negative-sequence)
in the grid voltage [32]; therefore, the energy transfer between the ac mains and a gridconnected power converter would not be well controlled while phase-angle error is big, so
the retracking should be as fast as possible. On the other hand, unbalance generates a
second harmonic ripple in the positive SRF [26]. Song et al discarded the use of notch
filters because of their sluggish transient response; they proposed the WLSE algorithm
instead, which indeed offers a surprising almost instantaneous retracking even under unbalanced conditions. Song et al proved the WLSE performance in a DVR. Of course, this
approach is suitable for any other approach where SRF controllers are employed.
It is also remarkable the single-phase version of the WLSE algorithm, which also
achieves almost instantaneous retracking [177, 178]. The single-phase WLSE algorithm
was proposed for a traction system in [178]: when a locomotive changes its voltage source,
the new phase-angle should be retracked as soon as possible in order to avoid malfunctions.

2.4.3.2.1 Three-phase WLSE Algorithm In [140, 176], the problem of phase-angle

estimation of a three-phase input signal (vabc ) is posed relating the SRF with the frame
as follows.
Considering only the fundamental component of vabc , it can be expressed in the
frame

T
v = C vabc
,

(2.65)

where

2 1 12 12

.
C=
3
3
3 0

2
2

(2.66)

v = [v v ] has information of positive and negative sequences: when there is

unbalance (negative-sequence) vmax 6= vmax . In order to decouple negative from positivesequence of the fundamental component the angle transformations are employed: the

100

Chapter 2 State-of-the-Art in Grid Synchronization

+(1)

matrix H is composed of the link of B1

random offset phase. That is:

H=

1 t(k))
cos(

sin(
1 t(k))

{z
|

sin(
1 t(k))

+(1)

and B1

, which rotate at
1 and have a

cos(
1 t(k)) sin(
1 t(k))

sin(
1 t(k)) cos(
1 t(k))
,

cos(
1 t(k))

+(1)

{z

(1)

B1

(2.67)

B1

so

+T
v = H vdq1
,

(2.68)

where

+
vdq1
=

+
+
vd1
vq1
vd1
vq1

(2.69)

+
+
vd1
, vq1
, vd1
and vq1
being the components of vabc1 in the positive and negative SRFs.
+
The sequential recursive computation steps for the WLSE estimation of vdq1
, and
hence the phase-angle from vabc1 are detailed below. The dynamic response depends on
the forgetting factor and initial error covariance (p0 ):

1. Compute of v with eq. (2.65).

2. Update H with the current t(k).
3. Compute of r Matrix:
r = I + H p HT .

(2.70)

K = p(k) H r(1) .

(2.71)

4. Compute of K gain:
5. Update the error covariance matrix p:
p(k) = 1 p(k 1) (1 K H).

(2.72)

+
6. Update the estimation of vdq1
:
+
+
+
dq1
dq1
dq1
v
(k) = v
(k 1) + K (v H v
(k 1)).

(2.73)

The phase-angle of the positive-sequence is obtained using vd+ , vq+ . Owing to the good
decoupling between positive and negative sequences there is not an undesired second
harmonic in estimated values.

2.4 Digital Alternatives to PLLs

101

Fig. 2.43 shows experimental results of the WLSE algorithm. The Matlab script of
appendix A.6 has been employed. It can be noticed that the transient response is very
good and it does not have ripple under unbalanced conditions. The transient response
could be even improved by the covariance reseting technique proposed in [140, 176].
Fig. 2.44 shows experimental results of adding extra sequences to H when dealing
with harmonics in the input: the simple implementation identifies the 5th harmonic as
noise and the should be reduced in order to filter it. The second option is to add positive
and negative sequences of the 5th harmonic to H: positive and negative sequences of 5th
harmonics are decoupled and the is kept. This second option could be more resourceconsuming, but in terms of performance seems to be an interesting one. Of course, in
very polluted practical systems more harmonic sequences in H could be implemented.
Until now, the effect of frequency deviations in stochastic filters has not been considered. However, stochastic filters are very sensitive to them [140, 181]. The frequency
adaptation of stochastic filters, specially the WLSE ones, is revised in the next section.

102

Chapter 2 State-of-the-Art in Grid Synchronization

Vb

Va

Amplitude (p.u.)

Amplitude (p.u.)

Vc
-1
0

0.01

0.02

0.03

0.05
Time (s)

0.04

0.06

0.07

0.08

0.09

0.1

-1

0.01

Amplitude (p.u.)

^
Vq1-

^
Vd10.01

0.02

0.03

0.04

Amplitude (p.u.)

^
Vq1+

0.06

0.05
Time (s)

0.07

0.08

0.09

0.1

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

^
Vq1+

0
^
Vq1-

^
Vd1-

-1

0.01

0.02

0.03

0.04

0.06

0.07

0.08

0.09

0.05 0.06
Time (s)

0.07

0.08

0.09

0.05
Time (s)

0.1

Phase-angle (rad)

Phase-angle (rad)

0.04

^
Vd1+

-0.2

0.03

1.5

^
Vd1+

0.02

^
1

0
-1

^
1

-2

-3
0

0.01

0.02

0.03

0.04

0.05 0.06
Time (s)

0.07

0.08

0.09

0.1

-3
0

0.01

0.02

0.03

0.04

Figure 2.43: WLSE experimental results for different s.

0.1

103

2.4 Digital Alternatives to PLLs

Va

Amplitude (p.u.)

Amplitude (p.u.)

Vb

V
0

Vc
-1
0

0.01

0.02

0.05
Time (s)

0.03

0.04

1.5

0.07

0.08

0.01

+(-1)

0.02

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

0.05 0.06
Time (s)

0.03

+(-1)

0.04

0.07

0.08

0.09

^
Vq1+

0
-0.5

-1.5

0.1

-2

1
0.01

+(-1)

0.02

-(-1)

^
1

0
-1

-2

0.04

-1

^
Vq1-

^
Vd1-

-(-1)

-3

0.03

0.5

Phase-angle (rad)

-1
0

0.02

^
Vd1+

Amplitude (p.u.)

0.01

1.5

^
Vq1+

-0.5

0.5

Phase-angle (rad)

-1

0.1

0.09

^
Vd1+

1
Amplitude (p.u.)

0.06

-(-1)
1

0.03

+(-1)

+(-1)

0.04

0.05 0.06
Time (s)

-(-1)

+(-1)
5

-(-1)
0.07

0.08

0.09

0.08

0.09

0.1

-(-1)

^
1

0
-1

-2

0.01

0.02

0.03

0.04

0.05 0.06
Time (s)

0.07

0.08

0.09

0.1

-3

0.01

0.02

0.03

0.05 0.06
Time (s)

0.04

0.07

0.1

Figure 2.44: WLSE experimental results. Effect of adding extra sequences to H.

104

2.5

Chapter 2 State-of-the-Art in Grid Synchronization

Frequency Adaptation of Synchronization Algorithms

The study of the linearized model of PLLs provides an accurate assessment of dynamics. However, studies of the dynamics provided for other schemes are not as deep and
accurate as the provided by PLL theory.
Section 2.3 revised the criteria followed to assess the performance of PLLs. Following
the same criteria, any synchronization algorithm should have:

1. high stability margins,

2. a fast transient response,
3. zero steady-state average phase error (1e = 0), and
2
),
4. low phase jittering (low 1ej

in order to be considered a high performance one.

As shown in section 2.4, many of the alternative synchronization algorithms have a
better performance on the whole than PLLs when working around nominal frequency
(1 1n ). However, as also pointed in section 2.4, this assertion should be reconsidered
in practical operation. Faults on the bulk power transmission system, a disconnection
of a large load or of a large source of generation cause frequency deviations (from 1n ).
These frequency shifts are larger in equipment powered by isolated generators.
Therefore, when assessing the performance of a synchronization algorithm, it should
be taken into account how it performs in the presence of frequency deviations and, in
some cases, detects this change.
International standards define ranges of normal operation for frequency deviations.

The European Standard UNE-EN 50160, which sets f1n = 50 Hz, establishes limits
in maximum allowable frequency deviations. For interconnected systems the mean
value of f1 , estimated each 10s should not exceed 1% ([49.5, 50.5] Hz) during the
99.5% of a week, but exceptional deviations between +4% and 6% are permited.
For isolated systems, normal operation of 2% and exceptional deviations of 15%
are specified [185].
The IEC-61000 Standard sets the normal limit operation in 2% for interconnected
system and extends these limits for isolated systems [144].

2.5 Frequency Adaptation of Synchronization Algorithms

105

Regarding to distribution generation, and more specifically to the new grid codes
for wind turbines, normal operation of wind turbines allows frequency deviations of
around 3 Hz [94].

When 1 6= 1n , it should be noticed that:

Digital PLLs using a lag/lead filter, as proposed in [46, 100, 105], would not have
1e = 0 (type I PLLs) [78, 79].
Filters employed in the frame as SRF-PLL pre-filters could lead to 1e 6= 0 in
steady-state when 1 6= 1n : some of these filters (e.g. D(z)) do not have the
expected frequency response at f1 6= f1n (e.g. phase response of D(z) in Fig. 2.27).
SRF based schemes, including the stochastic filtering ones, do not have 1e = 0
when srf 6= 1 because of the filtering delay. This phase error is:
1e = (1 srf ) td (f1 ),

(2.74)

where td (f ) is function of the input frequency (phase response), except for linear
phase filters [147, 158]. In the case of stochastic filtering, td is lower as faster is
the system (e.g. in the WLSE algorithms, the lower the faster the system, so the
lower td ).
FIR filters such as numeric delays (e.g. D(z)) and MAFs do not achieve complete
harmonic cancellation, which causes phase jittering. This assertion could be extended to stochastic filters.

Of course, the issue of frequency adaptation has been posed by most of the authors
proposing novel synchronization algorithms. In sum:

The use of PLLs to get frequency adaptation has been proposed to work with TAD
schemes [141] and SRF schemes [148, 186]. These hybrid schemes enhance their
whole performance using the frequency estimation from PLLs to adapt internal
signal and/or filter coefficients.
E.g. in [148] srf is estimated by a single-phase PLL. Then, Fig. 2.36 is implemented
with srf = h
1 for selective harmonic extraction of different harmonic components.
The implementation of an extra frequency loop, instead of a PLL, to estimate 1
and update srf has also been proposed [140, 143, 144, 151, 176, 177].
The update of the sampling rate of the digital device was proposed in the RDFT
algorithm of [158] and also in the single-phase PLL of [128]. Zero steady-state phase
error and low jittering is achieved. However, technical problems could appear, since
the frequency response of discrete filters is changing continuously [158].

106

Chapter 2 State-of-the-Art in Grid Synchronization

An alternative phase-offset correction technique is provided in [158]. In the case of
a PLL, a closed loop system, this limitation seems to be very important and the
PLL should have a very low bandwidth, and hence, a slow transient time, as shown
in Fig. 14 of [128].

GI discrete-time implementation can be updated using

1 as proposed in [119] for
PR current controllers. This has been applied in synchronization algorithms to avoid
phase error and/or jittering [123, 143, 144]. The chapter 5 of this thesis contributes
a novel approach concerning frequency adaptation of PR current controllers, which
can be also applied to synchronization.
Svensson and Bongiorno have studied the frequency adaptation of DSC filters. The
choice of the device sampling rate is very dependant on the grid frequency [187]. In
[188] a very similar technique to the phase-offset correction of [158] is provided for
DSC implementation.
Similarly to the case of DSC filters implementation, the choice of the sampling
frequency when implementing the pre-filters of [111] is not a trivial task. In a general
way, it could be concluded that the most difficult issue in the implementation of
pre-filters is to assure that the input wave is delayed an integer number of samples
[188].

2.5.1

Frequency Adaptation in WLSE Schemes

Dealing again with the WLSE synchronization algorithm, Song et al proposed a PI

based controller to correct the estimated frequency. The input of that PI was the phase
offset error between two consecutive samples. It should be noticed that the frequency
adaptation of the WLSE results in a very slow dynamics ( 2 s) when compared with
phase-jump and amplitude-change transients ( 1 ms) [140, 176, 177]. This problem has
also been reported in [108].
The main reason of this slow response is the very big forgetting factor ( = 0.9999)
employed in the implementation. From Figs. 2.43, a large provides very good filtering
but slow dynamics. Song et al fixed this problem proposing the so-called covariance
resetting technique, which resets the covariances to initial values when a grid fault is
detected. In this manner, it is achieved an excellent transient and steady-state (filtering)
responses. However, this approach has a drawback considering frequency deviations:
even though the WLSE in the form proposed by Song et al has a fast transient response
(when fault condition is correctly detected), in steady-state the WLSE is tuned with slow
dynamics. Frequency deviations do not reset the covariances so the system dynamics
remains very slow.
Therefore, it could be said that the covariance resetting technique does not seem a
good choice when considering considerable frequency deviations.

107

2.5 Frequency Adaptation of Synchronization Algorithms

Table 2.4
Look-up table: control of n depending on
1

2.5.2

Optimized for

1 n + 1

1 n 1

1 = 248.5 rad/s

103

248.8 rad/s

1 = 249 rad/s

102

249.3 rad/s

248.7 rad/s

1 = 249.5 rad/s

101

249.8 rad/s

249.2 rad/s

1 = 250 rad/s

100

250.3 rad/s

249.7 rad/s

1 = 250.5 rad/s

99

250.8 rad/s

250.2 rad/s

1 = 251 rad/s

98

251.3 rad/s

250.7 rad/s

1 = 251.5 rad/s

97

251.2 rad/s

Frequency Adaptive MAFs

This technique has been proposed in [148]. The frequency estimation from a PLL (
1 )
is employed to adjust online the order of the MAFs. Fig. 2.45 shows how the frequency
response for different n. Table 2.4 show the rule of change of the n value: upper and
lower thresholds are different from the center value in order to provide some hysteresis
behavior, avoiding continuous changes due to ripple in
1.

108

Chapter 2 State-of-the-Art in Grid Synchronization

1
Constant2
1
In
50.8-50.7

50.2-50.3

2
w

K Ts
Product

z-1
Discrete-Time
Integrator
1
Out

-98
Z

2*2

frequency
estimation

Integer Delay
49.8-49.7

49.3-49.2

Add

Multiport
Switch

-1
Z

49

Integer Delay1

Constant1
49.5

-1
Z

Constant3

Integer Delay2

50
Constant4

Multiport
Switch1

-1
Z

50.5

Integer Delay3

Constant5
51

-1
Z

Constant6

Integer Delay4

(a) Simulink implementation of MAFs with frequency adaptation.

1
n=98
n=99
n=100
n=101
n=102

0.9
0.05

0.8

(zoom)

0.04

0.7

Gain

Gain

0.6

0.03

0.5

0.02
0.01

0.4

0
97

98

0.3

99
100
101
Frequency (Hz)

102

103

0.2
0.1
0
0

50

100

150
Frequency (Hz)

200

250

(b) Frequency response of MAFs as function of n (fs = 10 kHz).

Figure 2.45: Frequency adaptive MAFs.

300

2.5 Frequency Adaptation of Synchronization Algorithms

2.5.3

109

Adaptative Filtering for Frequency Adaptation/Estimation

Adaptive and stochastic filters have been also proposed for frequency estimation, e.g.
[189, 190]. This section analyzes the frequency adaptation technique proposed in [151] to
enhance the performance of SRF-MAFs.
Fig. 2.46 shows the frequency update algorithm proposed for SRF-MAF1. Fig. 2.46a
shows SRF-MAF1 with frequency adaptation. Frequency adaptive MAFs are employed.
The frequency of the SRF is updated online, so srf =
1 . This assures that vq1 and vd1
are dc components in steady-state, and therefore, there is not filtering delay, so 1e = 0
is achieved. Fig. 2.46b represents the adatptive SRF-MAF1 (Fig. 2.46) depicted as an
adaptive filter.
Fig. 2.46c shows the flowchart for frequency estimation. This adaptive filter has been
designed taking into account the singular features of grid-applications. The main parts
of the proposed frequency estimation are detailed below:
The error signal (e), or cost function, is e = atan2(vd1 , vq1 ) variation with respect
to the previous sample (numerical derivative), as in [140, 177].
The abs(e) <  condition is placed in order not to estimate the frequency during
transients. Hence, it is assured that the transient response is the same as in open
loop operation.
The update of
1 is proportional to a gain factor () and e2 ; the e2 factor causes the
system to adapt rapidly when there is a high frequency shift and smoothly when
the shift is small.
The value of e is saturated in a range [emin , emax ] avoiding very big changes between
consecutive
1.
The value of
1 is saturated in the range [
1min ,
1max ], since practical frequency
deviations are within a reduced range.
The optimum mainly depends on the input signal features, specially uncorrelated
white noise. The optimum depends on the main algorithm, i.e. SRF-MAF1
optimum is not optimum for SRF-MAF3.
The approach made for single-phase systems is suitable for the three-phase approach
+ +
using the fundamental positive-sequence set of values (
vd1
,
vq1 ) to calculate e.
Table 2.5 shows the algorithm values used in the implementation. Different gains ()
have been used in order to show the noise dependence of this parameter.
Fig. 2.47 shows simulation results for the frequency adaptive SRF-MAF1 implementation using = 5 104 s/rad. The test shows the response of the system during the initial

110

Chapter 2 State-of-the-Art in Grid Synchronization

srf = srf t + srf

sin(u)
d

z-1

srf (k ) = 1 (k 1)

cos(u)
q

2H(z)MAF
f (dc, 2 , 4 ,...)

2H(z)MAF

)
vd 1

)
vq1

Frequency
Estimation
Algorithm

(a) SRF-MAF1 with frequency adaptation/estimation.

Initialize: x(0)=0; k=0

New sample: k=k+1

Estimate: vd1(k) and vq1(k)

x(k ) = atan2(vq1 (k ), vd 1 (k ))
Calculate error: e=x(k)-x(k-1)

no

abs(e)<
yes

SRF-MAF1
(Adaptive Fiter)

atan2(vq1 (k ), vd 1 (k ))
+

z-1

e(k)

(b) Fig. 2.46a depicted as an adaptive filter.

update

1 (k ) = 1 (k 1) + sig (e) e 2

Frequency
Estimation

Limit e: e min e emax

Saturate 1 estimation

1 (k ) min < 1 (k ) <= 1 (k ) max

(c) Flowchart of the adaptive filter

based frequency estimation.

Figure 2.46: Adaptive filter scheme of SRF-MAF1 with frequency adaptation/estimation.

2.5 Frequency Adaptation of Synchronization Algorithms

111

Table 2.5
Adaptive algorithm values.

103 rad/s

emin

0.7 103 rad/s

emax

0.7 103 rad/s

1max

251.5 rad/s

1min

248.5 rad/s

1 105 s/rad

1 104 s/rad

00

5 104 s/rad

transient (start-up) of an input signal with 1 = 49 Hz. Fig. 2.47a shows the fundamental
component reconstruction. As expected, the transient response lasts half a cycle of f1 .
Fig. 2.47b shows the phase error during and after the transient. The same result is shown
for the scheme without frequency adaptation in Fig. 2.47c. These results prove the improvement in steady-state, keeping the transient response features. Fig. 2.47d shows the
frequency adaptation; as said, during the initial transient
1 is not updated (abs(e) > 
condition); the update is made only in steady-state.
Regarding to SRF-MAFs, due to selectivity of MAFs, they cancel well harmonics but
not specially well other components. The effect of uncorrelated white noise is studied
below.
The optimum value of , under different noisy conditions, is studied for the SRFMAF3. This tests show the speed of the algorithm to adapting itself to the input frequency
during the start-up transient. Fig. 2.48a shows a set distorted (unbalance and harmonics)
input waves. The input frequency is 50.8 Hz. Fig. 2.48b shows how the system with higher
( = 1 105 s/rad) is adapted faster and with good accuracy. Fig. 2.48c shows the same
results when white noise of BW 10 kHz and PSD of 4 108 p.u. is added to Fig. 2.48a
waves. In this case ten times lower ( = 1 104 s/rad) is more suitable, since it has a
much lower level of frequency jittering. It is clear the influence of noise in the election of
the value, so the variables acquisition is key.

112

Chapter 2 State-of-the-Art in Grid Synchronization

Input Frequency= 51 Hz.

0.8

-10

0
-0.2
-0.4

Phase error (deg)

0.2

-30
-40
-50
-60

ZERO AVERAGE STEADYSTATE PHASE ERROR

-70

-0.6

-80

-0.8

-90

-1
0

ZOOM

-20

0.4
Phase error (deg)

Amplitude (p.u.)

0.6

0.01

0.02

0.03

0.04

0.05
Time (s)

0.06

0.07

0.08

0.09

-100
0

0.1

(a) Input wave and reconstructed (f1 = 51 Hz).

0.01

0.02

0.03

0.04

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

(b) Phase-error with frequency adaptation.

51.2

0
-10

51

-30

Phase error (deg)

Phase error (deg)

System Frequency (Hz)

ZOOM

-20

-40
-50
-60
-70

NON ZERO AVERAGE STEADYSTATE PHASE ERROR

50.8

50.6

50.4

50.2

-80

50

-90
-100

0.01

0.02

0.03

0.04

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

(c) Phase-error without frequency adaptation (

+2 deg average steady-state phase error).

49.8

0.1

0.2

0.3

0.4
Time (s)

0.5

0.6

0.7

0.8

(d) Frequency estimation.

Figure 2.47: Adaptive SRF-MAF1 Vs open loop SRF-MAF1 during the start-up and
steady-state.

2.6

Conclusion

This chapter provides an in-depth review of the state-of-the art in grid synchronization.
It is clear that the simplest open loop systems based on zero-cross detection are not
suitable for distorted environments. The first milestone in grid synchronization was the
PLO proposed by Ainsworth. The PLO system is almost immune to harmonics and
frequency deviations in weak grids. The drawback of the PLO is its complex dynamics (
dependence). Later, the use of CP-PLLs as measurement blocks was proposed in motor
drives applications, mainly to handle with big frequency deviations. The use of CP-PLLs
resulted in simpler controllers. However, this first CP-PLLs have important limitations
due to their PD are based on zero-cross detection. With the suitability of discrete devices,
digital PLLs were proposed. They perform much better than analog CP-PLLs. It should
be specially highlighted the SRF-PLL proposal. In fact, SRF-PLL implementation is being
investigated nowadays; several optimization techniques have been proposed since its first
appearances. Digital single-phase PLLs are also an interesting alternative to CP-PLL in
single-phase systems. On the other hand, by taking advantage of digital implementation
some interesting schemes have been proposed as alternative to PLLs, e.g. SRF-MAFs
and WLSE. However, PLLs provide a big advantage with respect to other systems: its

113

2.6 Conclusion

1.5

51.5

Frequency (Hz)

Amplitude (p.u.)

51

0.5

-0.5

50.5

50

-1

-1.5
0

0.01

0.02

0.03

0.04

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

49.5
0

0.2

0.4

0.6

0.8

1
Time (s)

1.2

1.4

1.6

1.8

(a) Unbalanced and harmonic contaminated set of (b)

Frequency
estimation
(green
input waves (blue is va , green is vb and red is vc ). with = 1 104 s/rad, red with = 1 105 s/rad).
51.5

Frequency (Hz)

51

50.5

50

49.5
0

Input Frequency
Freq. Meas with K2
Freq. Meas with K1
0.2

0.4

0.6

0.8

1
Time (s)

1.2

1.4

1.6

1.8

(c) Frequency estimation for a noisy input (green (d) dSpace implementation of Adaptive SRFwith = 1 104 s/rad, red with = 1 105 s/rad) MAF3. Frequency estimation using = 1
104 s/rad.

Figure 2.48: Frequency estimation with Adaptive SRF-MAF3.

very good frequency adaptation. Some frequency adaptation techniques for alternative
algorithms are reviewed.

114

Chapter 2 State-of-the-Art in Grid Synchronization

Chapter 3
Dynamics Study of Low-Gain PLLs
Abstract
This chapter presents a novel approach in the tuning of phase locked loops (PLLs) for power
electronic converters. PLLs are implemented inside a higher level controller to estimate the grid
voltage phase-angle and then control the energy transfer between the power converter and the ac
mains. The tuning of the PLL is not a trivial task, specially when considering power quality
phenomena.
In a general way, PLLs with a low bandwidth (low-gain PLLs) are required when handling
with distorted voltages. It is analytically demonstrated that low-gain PLLs have more trade-offs
than high-gain PLLs (e.g. PLLs for communications): it is not possible to optimize the settling
time for a phase-jump without getting slower the PLL response to frequency variations. Existing
tuning methods do not take into account low-gain features, which may result in non-optimum
designs.
The proposing PLL tuning methodology is based on inspection of frequency-domain diagrams
and, contrary to the other existing tuning methods, takes into account low-gain dynamics. It is
assured an optimized performance in the presence of any kind of disturbances in the grid.
From practical point of view, the proposed tuning procedure is very intuitive for controller
designers. Some significant design examples and experimental results, obtained from a discrete
implementation (dSpace platform), are provided in order to validate the theoretical approaches.
In the second part of the chapter, the DCO based on a RC oscillator is presented: the digital model of a sinusoidal oscillator is implemented, instead of explicit trigonometric functions.
This solution reduces the needed digital resources without reducing the performance, which could
be specially useful for DSP-based control of power converters. Experimental results are shown
proving the good performance of the proposal.

115

116

3.1

Chapter 3 Dynamics Study of Low-Gain PLLs

Introduction

As said in chapter 2, distortion in the ac mains should be taken into account when
tuning a PLL: there is a trade-off between filtering and transient response. With the
suitability of an ever increasing potential of discrete devices, several techniques to improve
this trade-off have been proposed, such as the placement of extra filter inside the loop
[106, 109, 112, 126] or before the phase detector (pre-filters) [111, 117, 123], and the
implementation of complex feedback structures [108, 126, 127]. However, it can be checked
that the implementation of filtering techniques always leads to a drastic reduction in the
whole bandwidth and therefore in the transient response speed. More specifically, when
optimization techniques affect to the closed-loop dynamics (filters inside and/or feedback),
the PLL should be tuned with a low bandwidth accordingly, giving rise to a low-gain PLL.
This chapter analyzes in depth the dynamics of low-gain PLLs through the frequency
response of their equivalent linearized model. It is analytically proved that low-gain PLLs
do not respond equally to phase or frequency changes. More specifically, it is not possible
to control the overshoot in the step response (phase-jump) without affecting very much
the dynamics when a frequency variation occurs. This fact is not taken into account in
previous works, which could easily result in a non-optimal tuning.
Taking into account low-gain features, a tuning method for grid-connected PLLs is
provided. This method is based on inspection of Bode and pole/zero diagrams, so it could
be said that it is very intuitive and useful for the controller designer. Some significant
design examples of SRF-PLL tuning are provided and tested in real time. These tests
contemplate both steady-state distortion and grid transients (faults). The dSpace DS1103
platform, using the discrete solver, and a programmable ac source have been employed
for the tests. Experimental results prove all the theoretical approaches.
In the second part of the chapter, the DCO based on a RC oscillator is presented. The
digital model of a sinusoidal oscillator is implemented, instead of explicit trigonometric
functions. This reduces the needed digital resources without reducing the performance,
which could be specially useful for DSP-based control of power converters.

3.2

Frequency Domain Based Tuning

Fig. 3.1 shows the PLL linear model, which is suitable for studying the dynamics of
PLL for which the linearization approach is accurate, such as SRF-PLLs and multiplied
based single-phase PLLs. The linear model open loop transfer function in the Laplace

117

3.2 Frequency Domain Based Tuning

PD

1t + 1

+-

1e

L(s )

DCO

1t + 1
H (s )

1
s

Figure 3.1: Studied linear model.

domain is given by the equation:

H(s) =

L(s)
| {z }

Loop F ilter

3.2.1

1
.
s
|{z}

(3.1)

DCO

Stability Margins and Cut-off Frequency

The stability condition of the linear model through the open loop frequency response
is: |H(s)| < 1 when H(s) 180 deg. Two quantities are directly related with this
stability criterion: the phase margin (PM) and the gain margin (GM). The crossover
frequency (c ) is referred to the frequency at which |H(s)| is 1 (0 dB). In this point the
PM is measured. PM is very useful to specify control system performance because it is
related with the damping ratio of the system () [191]:
PM

=
100

f or P M < 70 deg .

(3.2)

The information of PLL settling time (ts ) can be obtained from the H(s) frequency
response, since c is approximately equal to the closed loop bandwidth (3dB ) and natural
(n ) frequencies: ts to within 2% of the final value of a second order closed loop system
can be estimated with

ts =

4
4

n
c

(3.3)

[192]. Therefore, by inspection of the Bode diagram of H(s) the PLL transient response
can be estimated accurately. From (3.3) a high c results in a fast system. However, a
high c leads to a bad steady-state filtering: the choice of c is the main trade-off in the
tuning [28, 99]. ts can also be optimized increasing [117].

118

Chapter 3 Dynamics Study of Low-Gain PLLs

Stability margins and c can be estimated by different frequency domain methods

such as Nyquist, Nichols and Bode diagrams. The use of Bode diagrams is employed in
this work, since they provide information of both transient and steady-state performance.

3.2.2

Steady-state Distortion and Bandwidth

The needed information for phase-angle tracking is the dc component after the phase
detector. Any other harmonic content in the error signal causes jittering in the estimation
and should be canceled [78]. For the single-phase PLL it is clear that the second harmonic
is an annoying problem even though the input signal is totally clean. The problem of the
second harmonic appears in the SRF-PLL when there is fundamental negative-sequence
in the set of input voltages [99]. The presence of higher harmonics in the inputs could
also result in a loss of performance [28, 99].
The very first action to cancel the presence of non dc components in the error signal was
the reduction of the PLL bandwidth (c ), so the closed loop has low gain at non desired
frequencies [28, 99]. The suitability of ever-increasing performance digital devices allows
the implementation of more complex discrete filters and techniques. Some significant
proposals are

the implementation of different kind of filters inside the loop filter to cancel for
specific harmonics and unbalance effect [106, 109, 112, 126].
the use of filters before the phase detector (pre-filters) to cancel for specific harmonics and unbalance effect [111, 117, 123]. It should be noticed that the use of
pre-filters does not affect to PLL tuning, but reduces the whole bandwidth, since
they cause a lag when there is an input transient.
the implementation of complex feedback structures to cancel for second harmonic
(single-phase PLLs) and unbalance effect (SRF-PLL) [108, 126, 127].

Fig. 3.2 explains by itself the pros and cons of introducing extra filters inside the
loop (L(s)). Indeed, the magnitude versus frequency response allows to cancel for specific
components. However, each filter introduces phase inside the loop, which results in a
reduction of stability margins. Therefore, in order to have an acceptable PM, when extra
filters are placed inside the loop, the bandwidth (c ) should be reduced. It could be said
that, in general, the better the filter cancellation pattern of a specific filter, the worse
its phase response. Moreover, it should be also noticed that the effect of adding extra
feedback signals results in a drastic bandwidth reduction [108].

119

Magnitude (abs)

3.2 Frequency Domain Based Tuning

1
0.8

Notch (Q=10)
Notch (Q=1)
Moving Average

0.6
0.4
0.2

Phase (deg)

90

0
-90

-180

50

150
250
200
100
Frequency (Hz)

300

350

400

Figure 3.2: Frequency response of different filters for canceling harmonics.

3.2.3

Grid Events and Transient Responses

Typical power system electromagnetic phenomena related with transients in the input
of the PLL are voltage variation (sag and swells), phase-angle shifts or phase jumps and
frequency deviations [31].
The bandwidth is set by the gain of the loop filter, but also, by the amplitude of the
input signal. This is indeed a limitation of PLLs: the dynamics depends on the input
amplitude. A practical problem appears when a voltage sag is in the inputs. Usually,
voltage sags have a phase-jump associated [32]. Under such a situation, a low-gain PLL
is even slower than usual, and therefore the re-tracking time could be unacceptable. To
overcome this situation the PD input can be normalized using an amplitude estimation,
but it adds complexity to the PLL as well as to the dynamics assessment [111, 117, 126,
127].
Another limitation of low-gain PLLs, which is analytically proved below, is the fact
that the settling times in the presence of phase-jumps or frequency deviations could be
very different. More specifically, the step response of Fig. 3.1 model is not accurate for
frequency steps when H(s) overdamped. This introduces a new trade-off in the design of
the PLL, since, it is not possible to optimize ts for phase jumps without getting worse the
response to frequency deviations.
The error transfer function relating the phase error e to the input phase 1 is:

He (s) =

1
.
H(s) + 1

(3.4)

120

Chapter 3 Dynamics Study of Low-Gain PLLs

The Laplace transform of the phase error when a phase step or phase jump () is
applied at time t = 0 is [78]:

e (s) = He (s)

.
s

(3.5)

Through the final value theorem, a PLL has zero average steady state phase error
after a phase jump if:

lim s
e () = s
e (s) = 0.

(3.6)

In the same way, the Laplace transform of the phase error when a frequency step ()
is applied at time t = 0 is:

e (s) = He (s)

.
s2

(3.7)

and

e () = s
lim s
e (s) = 0

(3.8)

assures zero steady-state phase error after a frequency step.

The condition imposed by (3.8) requires of two origin poles in H(s) giving rise to a
type 2 PLL [79]. Applied to the PLLs of Fig. 2.18 if there is no origin poles in L(s)
this PLL does not have zero average steady-state phase error when the input signal is
not rotating at the frequency set by the feedforward constant of the VCO (vco ). Typical
digital PLLs implements PIs as loop filter resulting in type 2 PLL [99]. The use of a
lag-lead filter (lag compensator) instead of a PI filter, as proposed e.g. in [46], results in
type 1 PLL which does not assure tracking under frequency deviations.
Eqs. (3.6) and (3.8) do not provide information about how long the transients last.
In order to study the transient responses of the PLL, the inverse Laplace transform is
applied to eqs. (3.6) and (3.8). This analysis is performed assuming that L(s) is a PI
filter (type 2 PLL):
Ki
,
(3.9)
s
where Kp and Ki are the proportional and integral constants, respectively. This approach
is valid even though extra discrete filters are present inside the loop, since, from stability
conditions, their implementation require a low gain and therefore, the dominant roots
are the PI filter ones.
L(s) = Kp +

121

3.2 Frequency Domain Based Tuning

Eqs. (3.5) and (3.7), expressed also as function of and n , are:

e (s) =

s2

s
s
= 2
,
+ Kp s + Ki
s + 2n s + n2

(3.10)

s2

= 2
.
+ K p s + Ki
s + 2n s + n2

(3.11)

and

e (s) =

The expression of e (t) and e (t) in the time domain (being t = 0 the moment of
the transient) depends on the roots of the denominator (p1 and p2 ):

p1,2 = n (

3.2.3.1

2 1).

(3.12)

Underdamped Case: < 1

n t
2
e (t) =

sin(
n 1 t + )
1 2

(3.13)

where = tan1 ( 1 / ), and

e (t) =

3.2.3.2

n t

sin(
1 2 t).
n
n 1 2

(3.14)

Overdamped Case: > 1

e (t)

n (1 2 1)t
2

=
[(1 1) e

2 2 1 |
{z
}
slow pole

(1 +

2
2 1) en (1+ 1)t ] =
{z

f ast pole

q
q

2
[(1 2 1) ep2 t (1 + 2 1) ep1 t ]
2 1 |
{z
} |
{z
}
slow pole

f ast pole

(3.15)

122

Chapter 3 Dynamics Study of Low-Gain PLLs

and

e (t) =

n (1+

e|

{z

2 1)t
2
[e| n (1
{z
}
2n 1
slow pole

ep1 t ]
ep2 t |{z}
}] = 2 2 1 [ |{z}
n
f ast pole
slow pole

(3.16)

2 1)t

f ast pole

From eqs. (3.13) and (3.14), it is clear that for the underdamped case the transient
response can be improved both increasing Ki (n ) or Kp (). However, for overdamped
situation the situation is not clear at all. Eqs. (3.15) and (3.16) have two terms, one
decaying with ep1 t (fast pole) and another with ep2 t (slow pole).
In the case of e (t) (phase-jump) the term associated with the slow pole has associated
a smaller coefficient. If the system is tuned so |p1| >> |p2| the transient response only
depends on the fast pole, so this transient response can be improved increasing . A step
response with almost no overshoot can be achieved. It should be noticed that an increase
in is also equivalent to an increasing in the PM. The problem of this approach arises
when e (t) (frequency deviation) is considered (eq. (3.16)). The terms associated to the
slow pole has the same magnitude than the other one. If p2 is very close to the origin,
the transient defined by e (t) lasts very much.
Fig. 3.3a shows a diagram of poles/zeros for underdamped and overdamped situations.
As larger is the distance of the dominant poles to the imaginary axis, the faster is the
transient response. Moreover, the higher the imaginary part of a pole, the higher the

overshoot. Therefore, for the case of

e (s), it is clear that the transient response to a
phase-jump is better for the overdamped case because the dominant pole is p1 , since p2

is almost canceled by the origin pole (Fig. 3.3b). However, in the case of
e (s) the
absence of zero in the overdamped tuning leads to a situation where p2 is the dominant
root, and therefore, the underdamped case has a better frequency step transient (Fig.
3.3c). Therefore, it seems that a tuning around critical damping (Kp2 4Ki , so that
1) results in the better trade-off for transient responses, even though the overshoot
in e (t) is not canceled.
Finally, it should be noticed that a similar approach can be made in the Z-domain
obtaining the equivalent results. A very overdamped system in the Z-domain has its
dominant poles very close to the unity circle [117]. As PLLs are implemented in a discrete
device, an analysis/tuning in the Z-domain seems to be more suitable. However, the
analysis/tuning could be made in the Laplace domain if the sampling frequency (fs ) is
high enough when compared with the dominant poles frequency; the poles/zeros place in
the Laplace domain is much more intuitive to predict the time constants of the system.

123

3.2 Frequency Domain Based Tuning

(a) Poles-zeros diagram for e (s) and e (s) . Blue poles refer to < 1
and green poles to > 1. The origin zero (red) is only present in e (s) .

(b) e (t) comparative.

(c) e (t) comparative.

Figure 3.3: Comparative between underdamped and overdamped cases.

3.2.4

Limitations of Existing Tuning Approaches for Low-gain

PLLs

First of all, it should be noticed that the Evans root-locus diagram does not provide an
accurate tuning of low-gain PLLs: a type II PLL has a zero close to the origin (dominant
root). Its effect is negligible when the dominant poles are high, but not when they are
also close to the origin. In practice, Evans root locus does not provide a reliable overshoot
information from its for low-gain type II PLLs. It should be noticed that, in control
theory, the Evan root-locus is provided to analyze second order systems without zeros
[191].
In [28, 99, 117] analytical methods to predict the bandwidth and overshoot of PI
based type II PLLs are provided. It can be easily checked that low overshoot tuning
results in very overdamped systems which lead to big transient response in the presence of
frequency steps. Moreover, if extra filters (notch, MAF, DSC) are placed, those methods,
by themselves, are not accurate (P M and c change).

124

Chapter 3 Dynamics Study of Low-Gain PLLs

When comparing with previous tuning methods, two important new outcomes can be
extracted from this chapter:

PM and c information from the Bode diagram provides a very reliable information
to tune a PLL when extra harmonics/noise filters are placed inside the loop (lowgain PLLs).
The PI filter coefficients tuning should not give rise to very overdamped system,
which damages the transient response in the presence of frequency deviations, which
had been previously reported as an optimum tuning [117].

3.2.5

Design Examples

Some significant examples are shown in order to provide a comparison among tuning
strategies. The sampling frequency (fs ) is 10 kHz and the nominal frequency 50 Hz.

3.2.5.1

High Bandwidth SRF-PLL (HB-PLL)

A SRF-PLL with a very high Bandwidth is designed:

Ki
)
{z s }

L(s)HBP LL = (Kp +
|

(3.17)

P I f ilter

Table 3.1
Significant parameters of HB-PLL

c ( rad/s)
3

4.56 10

P M (deg)
49

Kp
4000

Ki
7

10

p1 ( rad/s)
(2 + i2.45) 10

p2 ( rad/s)
3

p1

From Fig. 3.4 and table 3.1, it is expected a PLL with a very fast transient response
both for phase jumps and frequency deviations. Some overshoot is expected. There is
not harmonic/unbalance cancellation.

125

3.2 Frequency Domain Based Tuning

80
60
40
20

-20
-120

-150

-210
2
10

10

10

10

Figure 3.4: Frequency response of H(z) for the HB-PLL (L(s)HBP LL was discretized
using the zoh method).

3.2.5.2

Unbalance/Notch SRF-PLL (UN-PLL)

A SRF-PLL for canceling the second harmonic generated by the negative sequence
using a notch filter is designed:

Ki
) N (s)
s
{z
}

(3.18)

L(s)U N P LL = (Kp +
|

P I f ilter

where N (s) is a notch filter at 100 Hz with Q = 1.25.

Table 3.2
Significant parameters of UN-PLL

c ( rad/s)

P M (deg)

Kp

Ki

p1 ( rad/s)

p2 ( rad/s)

145 (23 Hz)

70

141.44

5000

71.9

69.6

From Fig. 3.5 and table 3.2 it is expected a PLL with an acceptable transient response
both for phase and frequency jumps with some overshoot, since the system is near critical
damping (p1 p2 ). It has very good unbalance cancellation and an acceptable harmonic
filtering.

126

Chapter 3 Dynamics Study of Low-Gain PLLs

100
50

0
-50
-100
-150
0
-45
-90
-135

-180
-225
-1
10

10

10

10

10

10

Figure 3.5: Frequency response of H(z) for the UN-PLL (L(s)U N P LL was discretized
using the zoh method).

3.2.5.3

SRF-PLL with Moving Average Filter (MA-PLL)

A SRF-PLL is designed to have a very good harmonic/unbalance cancellation in

steady-state. L(s) is:

Ki
) M A(s)
{z s }

(3.19)

L(s)M AP LL = (Kp +
|

P I f ilter

where M A(s) is the transfer function of a moving average filter tuned to cancel even
harmonics; it is better expressed in the Z-domain (fs = 10 kHz):

M A(z) =

1 1 z 100
100 1 z 1

(3.20)

Table 3.3
Significant parameters of MA-PLL

c ( rad/s)

P M (deg)

Kp

Ki

p1 ( rad/s)

p2 ( rad/s)

69 (11 Hz)

69

70

70

68.98

1.02

From Fig. 3.6 and table 3.3 it is expected a SRF-PLL with an excellent harmonic/unbalance
cancellation, an acceptable phase-jump transient response (decaying with ep1 t ) with no
overshoot (high PM), but with a bad frequency variation transient (decaying with ep2 t ).

127

3.2 Frequency Domain Based Tuning

-100
-200
-300
-90
-135

-225
-270
-315
0
10

10

10

10

10

Figure 3.6: Frequency response of H(z) for the MA-PLL (PI filter was discretized using
the zoh method).

3.2.6

Experimental Results

The SRF-PLLs of section 3.2.5 have been implemented in a digital device (dSpace
DS1103) using the discrete solver at fs = 10 kHz. The execution times of all SRF-PLLs
were lower than 10 s. The three-phase input voltages have been generated with a threephase programmable ac source (three Chroma 61501 modules). In order to obtain the test
signals the three-phase ac source has been used as an arbitrary power amplifier connected
to a three-phase arbitrary waveform generator based on a DSP card. The input signals
have been acquired through the dSpace I/O interface by means of LEM LV25-P voltage
transducers and adapted to p.u. units. Fig. 3.7 shows the key oscillograms, obtained by
three different tests.
Figs. 3.7a, 3.7b and 3.7c show experimental results when the SRF-PLLs were tested
using a clean signal (no harmonics/noise) having a phase-jump of +45 deg; the input
frequency was 49.5 Hz. Steady state and phase-jump transient responses are shown. From
these results it is clear that the HB-PLL is the best option when there is not distortion,
since it has a very fast re-tracking (see Ch2: vq phase-error) and good steady-state
phase-angle estimation (see Ch4). As expected from their bandwidth, the other two
systems are slower.
In the frequency step tests (Figs. 3.7d, 3.7e and 3.7f) sudden frequency changes in
the input waves (alternating between 49 Hz and 51 Hz) were programmed in order to
show the response of each system in the presence of frequency deviations. As expected,
the frequency step and phase jump transient times are almost equivalent for not very
overdamped systems (HB-PLL and UN-PLL). For MA-PLL (very overdamped PLL) the
optimization in the phase transient settling time (low overshoot) resulted in a very slow
response in the presence of frequency deviations (see Ch2: vq phase-error).
In the distorted signal test (Figs. 3.7g, 3.7h and 3.7i), the pre-programed input waves

128

(a)
Clean
(HB-PLL).

Chapter 3 Dynamics Study of Low-Gain PLLs

signal

Test (b)
Clean
(UN-PLL).

signal

Test (c)
Clean
(MA-PLL).

signal

Test

(d) Frequency
(HB-PLL).

Step

Test (e) Frequency

(UN-PLL).

Step

Test (f) Frequency

(MA-PLL).

Step

Test

(g) Distorted
(HB-PLL).

signal

Test (h) Distorted

(UN-PLL).

signal

Test (i) Distorted

(MA-PLL).

signal

Test

Figure 3.7: Experimental results for different SRF-PLLs: Ch1 (black) is the Va input
in p.u./V, Ch4 is the instantaneous phase-angle measurement (100 mV/rad), Ch2 is the
error signal vq in p.u./V (1 p.u. = /2 deg of phase error), Ch3 is o (10 mV/(rad/s)).

3.3 RC Model of Digitally Controlled Oscillator

129

have unbalance ( 10% of negative sequence ) and high ammount of harmonics (10%
of 5th , 5% of 5th and 5% of 11th ); the input frequency was 50.5 Hz and a phase-jump
of +45 deg was pre-programmed. The HB-PLL responds very fast to the phase-jump
transient. However, it does not filter either harmonics or unbalance effect because its
high bandwidth, so that the quality of its phase-angle estimation is very poor due to the
jittering (see Ch4 of Fig. 3.7g). Excellent steady-state results are obtained with MA-PLL
thanks to the moving average filter, which cancels all the even harmonics caused by the
presence of odd harmonics and unbalance in the inputs (see Ch3 of Fig. 3.7i: o ).
However, its phase-jump transient response is slow, since it has a low bandwidth. UNPLL has a very good unbalance cancelation and acceptable harmonic filtering (see Ch3
of Fig. 3.7h: o ), and an average phase-jump transient response.
From these results, it could be stated that a previous knowledge of the grid level
distortion is very recommended when tuning a PLL. It should be noticed that, very
overdamped (e.g. MA-PLL) and very high bandwidth (e.g. HB-PLL) PLLs present some
important drawbacks when dealing with power quality phenomena, which may lead to
a poor energy exchange control (between the grid and the power electronic converter).
Therefore, an average system (no overdamped with a medium bandwidth), such as UNPLL, could be a good choice for most of the applications.

3.3

RC Model of Digitally Controlled Oscillator

This section provides a novel technique of trigonometric functions and SRF matrices
implementation, which has been presented in [112]. With regard to the PLL structure,
these blocks are part of a DCO.
The implementation of trigonometric functions is not a trivial task, specially in lowcost fixed point DSP; technical reports provide some techniques such as the use of look-up
tables, linear interpolation methods and IIR filters [193195].
This work proposes an efficient IIR based algorithm based on the model of a RC
electronic oscillator; its block diagram is depicted in Fig. 3.8a. Two unitary orthogonal
waves are obtained. This implementation reminds to GI based on two integrators [119],
but without input.
Fig.3.8b shows the closed loop poles of the digital oscillator for
1 = 1n ; of course, in
real time operation, the oscillation frequency
1 is updated online. Following Barkhausen
criteria, this system oscillates at
1 : from control theory, this system tends to instability
since its poles are on the imaginary axis; however, as the integrators are saturated, the
signal amplitude can be controlled [196]. Also from oscillators theory, the output of one
of the integrators must be non-zero in order to start the oscillation. e.g. sin(1 ) = 0,
cos(1 ) = 1 can be chosen to quickly achieve the oscillation steady-state.

130

Chapter 3 Dynamics Study of Low-Gain PLLs

cos(ot + o )
0.99

300

0.99

0.99

0.99

sin(ot + o )

o
Reset

o t + o

200
Imaginary Axis

Pole-Zero Map

400

(a) Block diagram of the digital oscillator.

Pole : 0 + 314i

100
0
-100
-200
-300
-400
-1

LOOP
FILTER

Pole : 0 - 314i

-0.5

0
Real Axis

0.5

(b) Poles/Zeros map of the oscillator (in

rad/s, continuous model).

Figure 3.8: RC Oscillator features.

The estimated phase (1 ) is calculated through the numeric integration of

1 between

[, ]. When sin(1 ) crosses zero in the falling edge 1 is reset to . Another option is
to use the range [0, 2] and reset on the rising edge.
As seen, this diagram is very low resource-consuming. A small drawback of the oscillator is that the generated waves sin(n ) and cos(1 ) are not pure sinusoidal waveforms,
due to the non-linear behavior of the saturation in the integrators. However, the total
harmonic distortion (THD) of these waves is negligible (0.70% when implemented at a
sampling frequency (fs ) of 10 kHz).The limits of the integrator should be chosen accordingly in order to assure that the amplitude of the fundamental component is 1. E.g. the
integrators are saturated at 0.99, not at 1.
As said, two orthogonal waves are the outputs of the oscillator. With regard to singlephase the in-phase and feedback signals are directly obtained. With regard to SRF-PLLs,
the assessment of Park transformations is immediate by:

3
2

) = 0.5 sin (1 )
cos(1 ).
sin (1
3
2

(3.21)

Fig. 3.9 shows the P1+ matrix calculation from the oscillator signals (Fig. 3.8a) and
(3.21) identities.

131

3.3 RC Model of Digitally Controlled Oscillator

2/3 sin(2/3)
cos(^1)

-2/3
2/3 cos(2/3)
2/3 sin(2/3)
sin(^1)

-2/3
2/3 cos(2/3)

Figure 3.9: P1+ generation from the oscillator signals.

3.3.1

Experimental Results

3.3.1.1

Simulation Results

Fig. A.7 of the Appendix shows a Matlab script which simulates the single-phase PLL
start-up tracking. A notch filter is placed to cancel the second harmonic. This script
also proves the simplicity and significance of the oscillator implementation: trigonometric
functions are not explicitly present. It is important to mention that the output of the
LF should be saturated (max/min = 128 rad/s). This is implicit in a DSP fixed point
implementation.

3.3.1.2

Single-phase PLL Implementation

The single-phase PLL has been implemented in the Technosoft MSK2407 board containing a TMS320LF2407 fixed point DSP of Texas Instruments; the word length of this
DSP is 16 bits. In the script of Fig. A.7 of appendix it is shown the representation for
each variable in Q format. It is important to comment that there is a trade-off in the
choice of the ylf pipeline format. A smaller pipeline (e.g. Q9) gives rise to a system
slower since it saturates easily. However, a bigger pipeline (e.g. Q7) would give rise to a
noticeable lose of performance due to the truncation after the LF multipliers. Q8 resulted
to be the optimum choice.
Fig. 3.11a shows the steady state phase measurement of the single-phase PLL when
a clean sinusoidal of 51 Hz is at the input. Fig. 3.11b shows the phase tracking when
the real grid signal is at the input. Fig. 3.11c shows the excellent transient response of
the PLL: after a strong fault such as a voltage sag from 1 p.u. to 0.5 p.u. and +45 deg
phase-jump the PLL re-tracks in less than a cycle. These results confirm the expected

132

Chapter 3 Dynamics Study of Low-Gain PLLs

Amplitude (p.u.), Phase-angle (rad/s)

3
2
1
0

-1
-2
Input signal
Mysin
Phase-angle

-3
0

0.01

0.02

0.03

0.04

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

(a) Single-phase PLL start-up simulation (ideal input signal).

Amplitude (p.u.), Phase-angle (rad/s)

3
2
1
0
-1
-2

Input signal
Mysin
Phase-angle

-3
0

0.01

0.02

0.03

0.04

0.05
Time (s)

0.06

0.07

0.08

0.09

0.1

(b) Single-phase PLL start-up simulation (highly harmonic contaminated input signal).

Figure 3.10: Simulation results for single-phase PLL (1 = 250.3 rad/s).

performance of the system.

3.3.1.3

SRF-PLL

The SRF-PLL have been implemented in the floating point PowerPC inside the dSpace
DS1103 prototyping platform. This platform contains a floating point micro PowerPC
and an I/O interface.
Fig. 3.11d shows the steady-state phase measurement for a highly unbalanced (both in
amplitude and phase) voltage system at the inputs of SRF-PLL. As expected, the second
harmonic is canceled. Fig. 3.11e shows the good tracking of the SRF-PLL when there is
superimposed white noise of 10 kHz BW and a power spectral density (PSD) of 106 p.u.
to the previous test wave. Fig. 3.11f shows the excellent performance of the SRF-PLL
tracking an unbalanced voltage system with notches.

3.3 RC Model of Digitally Controlled Oscillator

133

Zoom

(a) Phase measurement for sinusoidal input with

input frequency of 51 Hz.

(b) Phase measurement for real grid voltage.

Trigger

(c) PLL response under a strong fault.

(d) SRF-PLL steady state phase measurement

for a set of unbalanced voltages as input.
(fin = 50.5 Hz)

(e) SRF-PLL steady state phase measurement

of a highly noisy signal (fIN = 49.5 Hz).

(f) SRF-PLL steady state phase measurement

of a signal with deep notches (fIN = 50.8 Hz).

Figure 3.11: Experimental results.

134

3.4

Chapter 3 Dynamics Study of Low-Gain PLLs

Conclusions

This chapter presents an in-depth study of the dynamics of digital PLLs for gridconnected power electronic converters.
Section 3.2 reviews some PLL theory important concepts and proposes a tuning approach based on inspection of Bode and pole/zero diagrams. From a practical point of
view it could be said that the proposed tuning method is very intuitive. Moreover, two
new significant outcomes are contributed in this chapter:

1. PM and c information from the Bode diagram provides a very reliable information
to tune a PLL when extra harmonics/noise filters are placed inside the loop (low-gain
PLLs). This information is much more reliable that the obtained from analytical
methods having into account only the PI filter roots.
2. It is analytically proved that low-gain PLLs have a trade-off between the responses
to phase-jumps and frequency deviations. A very overdamped PLL has an optimized phase-jump response since the overshoot is minimized, but it has a very slow
response in the presence of frequency deviations. Therefore, the PI filter coefficients should not give rise to a very overdamped system, which had been previously
reported as an optimum tuning.

Some significant design examples of SRF-PLL tuning are provided in order to check in
real time the theoretical approaches. Experimental results prove the accuracy and validity
of the analysis.
The second part of the chapter shows the good performance of the RC-oscillator based
DCO. The low ratio grid over sampling frequency allows to implement an RC-oscillator
algorithm to work as DCO. In this way, a simple and accurate method of trigonometric
functions implementation is achieved. This method is specially suitable for low-cost fixed
point DSPs. Experimental results prove that, in practice, the proposed DCO performs as
an ideal oscillator, both for single-phase and three-phase PLLs.

Chapter 4
Predictive based SRF-MAF
Synchronization Algorithms
Abstract
Chapter 4 presents a novel open-loop synchronization system, designed from SRF-MAF
schemes. Accurate measurements of phase, frequency and amplitude are carried out in realtime.
Previous works establish that the fundamental positive-sequence vector of a set of utility voltage/current vectors can be decoupled using Parks transformation and low pass filters. However,
the filtering process introduces delays that impair the system performance. More specifically,
when the input signal frequency is shifted above the nominal, a non zero average steady-state
phase error appears in the measurements (estimations).
To overcome such limitations, a suitable combination of predictive and moving average FIR
filters is proposed to achieve a robust synchronization system for all input frequencies inside
typical normal operation ranges. MAFs are linear phase FIR filters which have a constant time
delay at low frequencies. A characteristic which is exploited to good effect to design a predictive
FIR filter which compensates such time delays, enabling zero steady-state phase errors for shifted
input frequencies.
In summary, the main attributes of the new system are its good frequency adaptation, good
filtering/transient response trade-off, the fact that its dynamics is independent of the input vector
amplitude and no trade-off between frequency deviation and phase-jump transient responses.
Comprehensive experimental results validate the theoretical approach and the high performance of the proposed synchronization algorithm.

135

136

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

As shown, synchronization is an issue of paramount importance in the control of

grid-connected power electronics equipment. Most control algorithms use some form of
systems voltage/current information, such as the phase, amplitude and frequency of the
fundamental component. It is expected that, the speedier and the more accurate these
measurements are, the better the generation of reference signals will be, and therefore the
more efficient the control actions.
Arguably, phase locked loops (PLLs) are the most widespread synchronization algorithms employed in grid-connected converters, as shown in previous chapters.
PLLs have been employed successfully in systems where an accurate phase measurement is required in high and medium voltage grid connected converters [64, 83, 197, 198],
and in systems with self adapting frequency variations characteristics [92, 145, 199201].
However, the dynamics of PLLs presents some drawbacks, as analyzed in chapter 3: lowgain features and input amplitude dependent dynamics.
As reviewed in Chapter 2, some alternative algorithms perform better than PLLs
under certain conditions, particularly when the input frequency is close to the nominal.
However, as the input frequency shifts, their performance tend to worsen. Frequency
control algorithms have been added to open loop schemes in order to make them frequency
adaptive. However, this is at the expense of increasing the complexity of their dynamics
and implementation by a considerable margin. So, in practical implementations, the PLL
continues to be the most employed synchronization algorithm, mainly due to its simplicity,
frequency adaptation features and versatility.
SRF-MAF based synchronization algorithms, have amplitude independent dynamics
and good filtering/transient-response. SRF-MAFs take advantage of both frequency and
transient (step) responses of MAFs. However, similarly to other open loop systems, they
lack frequency of adaptation features if a closed loop frequency loop is not added, which
adds complexity to the scheme.
In order to achieve frequency adaptation, predictive filters for compensating the delay
through the MAFs are proposed in this chapter: MAFs have linear-phase which implies
that the time of delay is constant and known for low frequencies [152]. The oscillation
frequency of Park variables is set by the input frequency deviation from the nominal. The
time of delay through the MAFs is always much smaller than the oscillation period of the
Park variables. Therefore, the trajectory in the time domain of the Park variables can be
approximated to a straight line, where only the time interval between the measured value
and the actual value are considered [202208]. Using this approach, the transfer function
of a predictive filter which predicts the current value of Park variables is obtained.
In summary, the use of moving average and predictive filters enables a purely open loop
system with frequency adaptation, amplitude independent dynamics and good filtering
versus transient-response trade-off. The dynamics of this open loop system is mainly
stated by the frequency and transient responses at the filtering stage. Moreover, more
than one moving average filter can be used in order to improve the cancellation pattern,

137

4.1 Calculation of Predictive Filters

but this at the expense of making the transient response slower.

Two design examples are presented. Their high performance is shown in the experimental results section. Simulation and real time implementation results are provided and
amply discussed.

4.1

Calculation of Predictive Filters

As shown in section 2.5, the most problematic drawback of SRF-MAF3 and SRFMAF1 (Fig. 2.40 and 2.36) is that 1 is unknown. Focusing in the design of SRF-MAF3,
+
+
when 1 6= 1n , vd1
and vq1
are low frequency components rotating at d = 1
1n . In
+
+
such a situation vd1 and vq1 are obtained with a time delay (td ) set by the phase versus
frequency response of the low pass filter employed. If it is not compensated, this time
delay would cause a constant average steady-state phase error (1e ) proportional to td and
d :
1e = 1 1 = d td .

(4.1)

The only way to know td in open loop, without knowing d is using a linear-phase FIR
filters. Linear-phase refers to the condition where the phase response of the filter is a linear
function of frequency, excluding phase wraps at 180 deg. This results in td through the
filter being the same at all frequencies [152].As shown in section 2.4.2.2, MAF filters have
linear-phase. in the Z-domain a MAF is 1 :
1 1 z N1
.
H1 (z) =
N1 1 z 1

(4.2)

The time delay through this filter is

td =

N1 1
.
2 fs

(4.3)

A predictive filter compensating for MAF lag can be calculated as follows. From (2.44)
td is calculated off-line. While td << 2d , it is correct to say that in any td interval both
+
+
vd1
and vq1
trajectories in the time domain fit very well to a straight line. Therefore, it is
possible to predict future samples from current samples into this trajectory [202208].
y2 (k + 1) being the current sample of a straight line trajectory, it can be expressed as:

y2 (k + 1) = y2 (k) + m
1

In this chapter, it is used N1 instead of n.

1
fs

(4.4)

138

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

m being the slope. In the same way:

y2 (k + 2) = y2 (k + 1) + m

1
.
fs

(4.5)

From eqs. (4.4) and (4.5):

y2 (k + 2) = 2 y2 (k + 1) y2 (k).

(4.6)

N2 being the number of samples of delay through a moving average FIR filter, it is set by
td (eq. 4.3) and fs :

N2 = td fs =

N1
.
2

(4.7)

Knowing N2 from the moving average FIR filter parameters, through eq. (4.6) the
future N2 sample can be predicted from the current and past samples as follows:

y2 (k + N2 ) = 2 y2 (k + N2 1) y2 (k + N2 2) =
= 3 y2 (k + N2 2) 2 y2 (k + N2 3) =
= (N2 + 1) y2 (k) N2 y2 (k 1).

(4.8)

Eq. (4.8) can be expressed as the Z domain transfer function:

H2 (z) = (N2 + 1) N2 z 1 .

(4.9)

The predictive filter defined by eq. (4.9) compensates the delay through the moving
average FIR filter: for low frequencies, the phase versus frequency response of H2 (z) has
a linear positive phase which cancels the negative linear phase of H1 (z).
By inspecting the phase versus frequency response of the whole filtering stage (H1 (z)
H2 (z)) , H2 (z) can be optimized accordingly in order not to have almost any phase delay
without introducing amplitude error. H2 (z) is redefined as:

H2 (z) =

(N2 + 1) (N2 )z 1

,
1+

where  is an optimization parameter ( << 1).

(4.10)

139

4.2 Design Examples

Vabc

H1(z)

vd+1

H2(z)

[P1+ ]

Vabc

H1(z)

H1(z)

H1(z)

H2(z)

[P1+ ]

vq+1
H1(z)

H1(z)

H2(z)

H2(z)

vd+1

vq+1

Filtering Block

Filtering Block

(a) Filtering stage of S1.

(b) Filtering stage of S2.

Figure 4.1: Filtering blocks of the design examples.

4.2

Design Examples

Following the theoretical approach of the previous section, two design examples are
contributed.

4.2.1

Design Example 1

Fig. 4.1a shows the filtering block which employs two pairs of linked moving average
and predictive filters. The values of the parameters are summarized in table 4.1.

Table 4.1
Design Example 1 Values.

fs

N1

N2

10 kHz

100

50

0.0095

The whole system implementing this filtering block is named S1. Fig. (4.2a) shows
H1 (z)H2 (z) frequency response. The cancellation pattern is optimized for even harmonics
after P+
1 caused by odd harmonics in the input signal vabc [146]. Fig. (4.2b) proves
the feasibility of the predictive filter approach: the phase delay is almost zero for low
frequencies. This error is even minimized by the optimization of the  value (Fig. (4.2c)).
Figs. 4.2d and 4.2e show that the transient response is kept in half a fundamental cycle.
As said, in this approach only odd harmonics in vabc are considered since non-linear
electrical loads causing high even harmonic disturbances (in vabc ) are not usual and their
use must be precluded in ac networks [163165]. To deal with the presence of even
harmonics in vabc , N1 = 200 and N2 = 100 could be considered.

140

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

Magnitude (abs)

0.5

90

Phase (deg)

1.002

45

0
-45
-90

-135

50

100

150

200

250

300

350

400

450

500

Frequency (Hz)

550

(a) Frequency response (in Hz).

0.03
0.02
0.01

0
-0.01
0

0.5

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

Frequency (Hz)

1 sample

0.4

1.011

0.3
1.0105

Amplitude

Magnitude (abs)

1.001
1.0005

(b) Fig. 4.2a zoomed around low frequency with

 = 0.

1.0115

1.01

1.0095
0.001
0

Phase (deg)

1.0015

0.9995
0.04
Phase (deg)

Magnitude (abs)

1.5

0.2
0.1

100 samples of 0.01

0
-0.1
-0.2

-0.001

-0.3

-0.002

-0.4
-0.003

-0.004

0.2

0.4

0.6

0.8

1.2

1.4

1.6

Frequency (Hz)

1.8

-0.5
0
2

(c) Fig. 4.2a zoomed around low frequency with

 = 0.0095.

1 sample
0.002

0.004

0.006

0.008

Time (sec)

0.01

0.012

(d) Impulse response (tw = 0.01 s). .

1.8
1.6

Amplitude

1.4

1.2

1
0.8

0.6

0.40

0.002

0.004

0.006

0.008

Time (sec)

0.01

0.012

0.014

(e) Step response (tw = 0.01 s).

Figure 4.2: Design example 1: time and frequency responses of H1 (z) H2 (z).

0.014

141

4.3 Simulation Results

4.2.2

Design Example 2

Even though S1 is a very good practical solution dealing with unbalance and harmonics, the presence of other factors such as interharmonics, noise, notching (also noise), dc
offset ([132]) could degrade the performance of the measurements. In fact, the limitations
of the proposed system are mainly set by its cancellation pattern. In order to improve the
0
cancellation pattern two moving average filters H1 (z) and H1 (z) can be linked, as proposed in this section (Fig. 4.1b). The predictive filter should be recalculated according
to eq. (4.7), since the time of delay through the two filters is doubled. The whole system
implementing this filtering block is named S2, and its values are summarized in table 4.2:
Table 4.2
Design Example 2 Values.
0

fs

N1

N1 (Eq. (4.2) for H1 )

N2

10 kHz

100

100

100

0.009

Fig. 4.3 shows the frequency and step responses of design example 2. The cancellation
pattern is improved at cost of doubling the transient time. As in other systems such as
PLLs, there is a trade-off between filtering and transient response.

4.3

Simulation Results

The S1 system proposed in the previous section has been simulated in order to test
its performance. Simulation results have been obtained through Matlab/Simulink, using
the fixed step discrete time solver at fs = 10 kHz.
The most important feature of time domain simulation with respect to real time
implementation is the possibility of obtaining curves of phase error, frequency error and
amplitude error in the time domain. These errors are defined as the difference between
the actual and estimated values.
The amplitudes of the input waves are in p.u. units, so they can represent both
voltages or currents. The magnitude displayed to indicate the amount of unbalance in

vabc is the negative sequence vector magnitude (va1

).
max

+
Fig. 4.4 shows the phase error for an unbalanced (va1
= 0.1 va1
) input wave
max
max
rotating at 51 Hz (1 = 251 rad/s). A 45 deg phase jump has been programmed to
show both steady-state and transient responses. The result is also displayed for the system
without predictive filters. As expected, the system without predictive filters has the nonzero average steady-state phase error set by eq. (4.1). With predictive filter, steady-state
zero error is achieved. As also expected, the transient lasts 0.01 s.

142

1.6

1.5

1.4

1.2

Amplitude

Magnitude (abs)

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

0.5

Phase (deg)

360

1
0.8

0.6

-360
-720

0.4

-1080
-1440

0.2

-1800

-2160
0

50

100

150

200

250

300

350

400

450

500

Frequency (Hz)

00

550

0.005

(a) Frequency response (in Hz).

Phase (deg) Magnitude (abs)

0.01

0.015

Time (sec)

0.02

0.025

(b) Step response (tw = 0.02 s).

1.01
1.008
1.006
1.004
1.002

1
0.998
0.01

0
-0.01
-0.02
-0.03

-0.04
0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

(c) Fig. 4.3a zoomed around low frequency with

 = 0.009.
0

Figure 4.3: Design example 2: Frequency and Step responses of H1 (z) H1 (z) H2 (z).

143

4.3 Simulation Results

Va

Amplitude (p.u.)

Vc

0
Vb

-1
0.99

1.01

1.02
Time (s)

1.03

1.04

1.05

+
) set of input waves
= 0.1 va1
(a) Phase jump transient in unbalanced (va1
max
max
rotating at 1 = 2 51 rad/s.

20

10
0
Phase error (deg)

Phase error (deg)

10
0
Average steady-state
phase error equal to 0

-10
-20
-30
0.99

Average steady-state phase

error equal to 1.8 deg.

-10
-20
-30
-40

1.01

1.02
1.03
Time (s)

1.04

1.05

(b) Phase error: transient and steady-state

with predictive filters (H2 (z)). Zero average
phase error is achieved.

-50
0.99

1.01

1.02
1.03
Time (s)

1.04

1.05

(c) Phase error: transient and steady-state

without predictive filters (H2 (z)). There is no
zero average phase error.

Figure 4.4: S1: Test to show predictive filters action.

144

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

Frequency error (Hz)

Phase error (deg)

Input frequency (Hz)

Fig. 4.5 shows the phase error when the input wave of the previous test has a big
frequency step in 0.2 s: from 48 Hz to 52 Hz. Before and after the transient of duration
0.01 s, the average phase and frequency error are zero. As shown, frequency deviation
and phase jump responses are equivalent, on the contrary to overdamped PLLs.
53

52
51
50
49

48
47
0.17

0.18

0.19

0.2

Time (s)

2
1.5
1

0.21

Average steadystate phase error

equal to 0

0.22

0.23

Average steadystate phase error

equal to 0

0.5

0
-0.5
0.17

0.18

0.19

0.2

Time (s)

0.21

0.22

0.23

Average steadystate phase error

equal to 0

Average steadystate phase error

equal to 0

0
-2
0.17

0.18

0.19

0.2

Time (s)

0.21

0.22

0.23

+
Figure 4.5: S1 response to a big frequency step at 0.2 s. Unbalanced (va1
= 0.1 va1
max
max
) input wave. Frequency step (up), phase error (center) and frequency error (down). Zero
steady state error and transient duration of 0.01 s are achieved.

+
Fig. 4.6 shows the results for an unbalanced (va1
= 0.1 va1
) and harmonic
max
max
th
th
th
contaminated ( 10% 5 , 7% 7 , 4% 11 ) input wave rotating at 49.5 Hz. In 1 s a
deep magnitude change (sag) from 1 p.u. to 0.2 p.u. with a +45 deg phase jump has been
programmed. Fig. 4.6b shows how steady-state phase error is achieved; the transient
+
+
+
+
lasts 0.01 s. Fig. 4.6c shows va1
, amplitude error, vd1
and vq1
; as expected vd1
and
max
+
vq1
rotate at 0.5 Hz. The average amplitude error is non zero only during the transient
+
+
(0.01 s). Fig. 4.6d shows the Clarke variables (
v1
and v1
) employed in the calculation
of 1 .

4.4

Experimental Results

The proposed algorithm has been implemented in the dSpace platform DS1103 at
(fs = 10 kHz) and tested in the laboratory. The execution time of S1 and S2 was 11.2 s
and 15.8 s respectively. The three phase voltage system has been generated with a three
phase programmable AC source (three Chroma 61501 modules). In order to obtain the

145

4.4 Experimental Results

40

1.5
Va

Vb

Vc

20

0.5
-20

0
-40

-0.5
-60

-1

-1.5
0.95

-80

0.96

0.97

0.98

0.99

1.01

1.02

1.03

1.04

1.05

-100
0.95

0.96

0.97

0.98

0.99

1.01

1.02

1.03

1.04

1.05

(a) S1: set of distorted input waves in time domain. (b) Phase error: the transient lasts 0.01 s and zero

+
) and harmonics average steady-state error.
= 0.1 va1
Unbalance (va1
max
max
th
th
th
( 10%5 , 7%7 , 4%11 ).
1.2

|Vp|

0.8

0.8

0.6

Vq

0.6

0.4

0.4

0.2

0.2

-0.2
-0.4

-0.2
Vd

-0.4

-0.6
-0.8

-0.6
-0.8
0.95

-1
0.96

0.97

0.98

0.99

1.01

1.02

1.03

1.04

1.05

0.95

0.96

0.97

0.98

0.99

1.01

1.02

1.03

1.04

1.05

+
+
+
+
+
(c) va1
, vd1
and vq1
measurements. The tran- (d) v1
and v1
estimations. They are not dismax
sient lasts 0.01 s and zero average steady-state er- torted.
ror.

Figure 4.6: S1 tested under a distorted set of input waves rotating at 49.5 Hz. At 1 s, a
1 p.u. to 0.2 p.u. sag with +45 deg phase jump has been programmed.

146

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

Vb

Vc

Va, V

Va
V

VaV
VaV

(a) Balanced set of voltages oscillating at 48 Hz and (b) Zoom of Fig. 4.7a around the zero cross. The
+
which tends to zero. average error is slightly positive due to the sampling
V measurement. M1 is va
v1
process.

Figure 4.7: S1: steady state error for a balanced set of inputs oscillating at 48 Hz.

test signals containing sags, unbalance, harmonics and notching signals the three phase AC
source has been used as an arbitrary power amplifier connected to a three phase arbitrary
waveform generator based on a DSP card. The input signals have been acquired through
the dSpace I/O interface by means of LEM LV25-P voltage transducers. As in previous
section, p.u. units have been employed.
As the system is an open loop system, no feedback error signals can be presented.
+
However, considering only the fundamental component, va = v1
for balanced conditions

0
0
and for unbalalanced systems when va = va , that is vabc and vabc
cancel each other
+
for the a phase. Therefore, testing the systems under such conditions va v1
represents
+
the error; that is va v1
= 0 implies zero error in phase, frequency and amplitude. The
subtraction function of the oscilloscope has been used to obtain this error (channel M 1).
Fig. 4.7 shows the error signal of S1 in steady-state when the set of inputs is balanced,
and oscillates at 48 Hz. As shown, the error is negligible. In the zoomed figure, it could
be noticed the small positive delay between the input (va ) and the output or processed
+
signal (
v1
). This error is due to the sampling process (execution and conversion times).
Fig. 4.8 shows the error signal of S1 in steady-state for an unbalanced set of inputs

+
oscillating at 51 Hz. As explained before, va = va0 and va1
= 0.1 va1
in order
max
max
to test the error signal. These figures also prove the absence of steady state error of the
algorithm. Fig. 4.8b shows again the small delay in the visualization due to the sampling
process.
Fig. 4.9 shows the error signal of S1 before, during and after a transient. The pro+
grammed transient is a sag with post-fault component [32]. During the fault va1
=
max

0
0.8 p.u. and va = va with va1max = 0.05 p.u., and a 45 deg phase jump with respect to

147

4.4 Experimental Results

Vb
Vc

Va, V

Va
V

VaV
VaV

(a) Steady state measurements for a balanced set of (b) Zoom of Fig. 4.8a around the zero cross. The
+
voltages oscillating at 51 Hz. M1 depicts va v1
average error is slightly positive due to the sampling
as error signal tends to zero in steady-state.
process.

+
) set of inputs
= 0.1 va1
Figure 4.8: S1: Steady state error for an unbalanced (va1
max
max
oscillating at 51 Hz.

+
the balanced wave of va1
= 1 p.u..
max

Once proved the theoretical approach in terms of zero steady state error and transient
response, other interesting figures are shown. Because of the features of the input waves,
the error signal is not available for these tests.
Fig. 4.10 shows how the measurement of 1 through S1 for a set of unbalanced

+
(va1
= 0.09 va1
) and harmonic contaminated ( 9% 5th , 5% 7th , 3% 11th ) inmax
max
put waves rotating at 48 Hz is rippleless.
Figs. 4.11) and 4.12 compare S1 with S2 in terms of the trade-off between filtering
and transient response.
Fig. 4.11 shows the test made for a balanced input wave containing notches, which,
+
under the frequency domain point of view, is noise. Fig. 4.11a shows v1
measured with
+
S1 contains notches, even though smoother than in input waves. Fig. 4.11b shows as v1
measured with S2 is clean. These results are expected from Figs. 4.2a and 4.3a.
Fig. 4.12 shows how S2 improves the frequency rejection of S1 at cost of incrementing
the resources (execution time) and transient response. This test has been realized with

+
an unbalanced (va1
= 0.09 va1
) input wave which presents a very deep sag: from
max
max
1 p.u. to 0.1 p.u. with 45 deg phase jump. S1 is faster than S2 as expected from Figs.
4.2e and 4.3b. Figs. 4.12 emphasize the fact that the system gain is independent from
the input amplitude.

148

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

Vb
Vc
Va

Va

VaV

VaV

(a) S1: Transients response to a sag with 45 deg

+
as error signal
phase jump. M1 depicts va v1
which is zero in steady-state. As expected, the transients lasts 0.01 s. Time scale at 5 ms.

(b) S1: Transients response to a sag with 45 deg

+
as error signal
phase jump. M1 depicts va v1
which is zero in steady-state. As expected, the transients lasts 0.01 s. Time scale at 2 ms.

Figure 4.9: S1: Transient response for a sag with 45 deg phase jump.

4.4.1

Brief Comparative

Table 4.3 shows a brief comparative with other significant proposals which successfully
deal with unbalance [108, 140, 144] 2 .
Table 4.3
Brief comparative among significant systems with good unbalance rejection

System

Settling time

Execution

(Ts )

Time

S1

0.01 s

11.2 s

S2

0.02 s

DSRF-PLL

Device

Frequency

Amplitude

Loop

Dependence

dSpace 1103

NO

NO

15.8 s

dSpace 1103

NO

NO

0.036 s

(< 50 s)

dSpace 1103

YES

NPSF

> 0.02 s

6.5 s

TMS320F2812 (DSP)

YES

YES

WLSE

< 0.005 s

10 s

TMS320C31 (DSP)

YES

NO

The settling time (ts ) is defined as the time required for the system to settle within a
certain percentage of the steady-state value [192].
As proved, for S1 and S2 ts is accurately set by the step response of the FIR filtering
stage (eq. (2.43)): 0.01 s and 0.02 s respectively. In relation to device implementation,
it is clear that the moving average filters are a part resource consuming as shown in the
2

The comparative is made with respect to data provided in those works. DSRF-PLL is the Double
SRF-PLL provided in [108]

149

4.4 Experimental Results

Figure 4.10: S1: steady-state phase measurement at 48 Hz. Ch1 is 1 , Ch2 is va , Ch3 is
vb , Ch4 is vc (phase in 2 rad, voltages in p.u.). The measurement does not have ripple.

increment of execution time from S1 to S2. However, this and other implementations
[128, 157, 158] prove that current digital devices are powerful enough to implement them
in real time. With regard to amplitude dependence, due to the linearity of all the employed
digital filters the system is amplitude independent.
The settling time ts (to within 2% of the final value) of the DSRF-PLL has been
estimated using the data (c = 225 rad/s, = 0.707 ) of the equivalent linearized
systems studied in [108] through the formula [192]:

ts =

4
.
c

(4.11)

The accuracy of this estimation can be checked in Figs. 11 and 12 of [108]. The
execution time of the DSRF-PLL is not shown in [108], but, it is smaller than the implementation sampling time (50 s).
The non-linearity introduced by the phase detector in PLLs, and therefore also in the
DSRF-PLL has the drawback of amplitude dependence, even though this can be reduced
through a normalization stage [126, 127, 137].
ts of NPSF presents a high vary depending on the kind of transient, as shown in Figs
12 of [144], which is a non linear feature. This time is always higher than 0.02 s.
The WLSE algorithm , tested when the input frequency is tracked (Figs. 6 and 7 of
[140]) presents a very quick response and good harmonic/noise rejection. However, its
frequency adaptation algorithm is very slow when compared with the NPSF one. In fact,
the frequency adaptation seems to be the main lack of the WLSE algorithm [108].

150

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

Va

Va

(a) Measurement with S1.

notches.

+
also contains
v1

Va

Va

+
is clean.
(b) Measurement with S2. v1

+
Figure 4.11: Comparative between S1 and S2 in terms of noise rejection. Ch1 is va1
,
max
Ch2 is va , Ch3 is vb , Ch4 is vc (voltages in p.u., 1 = 2 49.75 rad/s).

Va

Va

Va

Va

(a) Transient response of S1. The steady-state is (b) Transient response of S2. The steady-state is
reached in 0.01 s.
reached in 0.02 s. The settling time is doubled.
+
Figure 4.12: S1 Vs S2 in terms of transient response. Ch1 is va1
, Ch2 is va , Ch3 is vb ,
max
Ch4 is vc (voltages in p.u., 1 = 2 49 rad/s).

4.5 Conclusions

151

In general, it could be said that adaptive filtering based algorithms such as Kalman
based and WLSE have a trade-off between transient response and frequency adaptation,
as proved in [145]. The WLSE approach of [140] is in the extreme of very fast transient
response but with a very slow frequency adaptation.
From table 4.3, it is clear that S1 and S2 present very good dynamics and are suitable
for real time implementation with a high performance.

4.5

Conclusions

This chapter shows how the SRF-MAF systems can be made frequency adaptive by
means of predictive filters. The methodology developed to obtain FIR predictive filters is
contributed. Some interesting features of the proposal should be highlighted.

It has a very good filtering/transient response trade-off. It is specially advantageous

in the presence of unbalances and harmonic distortion.
Since it is based on the implementation of linear filters its implementation is simple
and not very much resource-consuming. No explicit trigonometric functions are required if the Parks transformations are implemented by means of the RC oscillator.
Its dynamics are independent from the amplitude of the input waves, and therefore
the system is highly stable. This advantage is specially advantageous for phase-angle
tracking of variable rms waves such as the current in a SSSC [209].
On the contrary to PLLs, specially overdamped tuned ones, there is not trade-off
between frequency and phase responses.
It is frequency adaptive without resorting to an extra frequency loop. In It yields to
zero steady-state average error for all the measurements with independence of the
input signal frequency.

These features, bode well for the applicability of the algorithm in the control of grid
connected power converters, grid monitoring in distributed power generation systems, and
other applications where a fast and accurate on-line measurement of phase, frequency and
amplitude are mandatory.
Even though they were not developed or commented in the chapter, some interesting
points of this proposal should be also mentioned:

The application of the algorithm in single-phase systems of working per-phase is

immediate, resulting in a predictive SRF-MAF1 system [209].

152

Chapter 4 Predictive based SRF-MAF Synchronization Algorithms

The theoretical approach to achieve the predictive filters is based on predictive FIR
filters. However, IIR all-pass filters with a more advantageous amplitude response
(unitary gain) and positive linear-phase could be developed. In return, this solution
has a longer transient response.

Chapter 5
Frequency Adaptive PR Current
Controller for APFs
Abstract
This chapter provides a novel approach in the implementation of Proportional+Resonant
current controllers, specially suitable for active power filters compensating for high order harmonics. The difference equation to implement each resonant controller has been obtained from
the impulse invariant discretization method; an explicit estimation of the grid-frequency deviation, which is obtained from a PLL, is employed to update online the current controller. The
method to update the difference equation, which is a proposal of this thesis, is based on a Taylor approximation which avoids explicit trigonometric functions. Technical details of the whole
discrete-time controller are provided in the chapter.
A 1 kVA rated lab prototype has been implemented and tested. Experimental tests show
how the system performs both in steady-state and under different transients. Perfect tracking
in steady-state for a wide range of grid-frequencies is achieved. Regarding transient response,
different tests were programmed such as load transients (change in the load), sudden and large
changes in the ac mains frequency (frequency steps) and strong source voltage faults (voltage
sags with phase-jump). Experimental results prove how the system is robust and fast responding
to all of these possible real operation faults.

153

154

5.1

Chapter 5 Frequency Adaptive PR Current Controller for APFs

Introduction

The issue of current control for power electronic converters connected to the grid is a
field of paramount interest at present [210217]. More specifically, schemes including resonant controllers to achieve perfect tracking/rejection in steady-state of periodic currents
have been proposed for all kind of power converter applications, such as active power filters (APFs) [119, 120, 210], distributed power generation systems (DPGSs) [2, 217219],
rectifiers [213, 220] and motor drives [36, 88, 221].
Among other resonant-based controllers, Proportional+Resonant (PR) current regulators are very interesting thanks to their potential high bandwidth [88, 120]. PR current
regulators can achieve perfect tracking for high order harmonics and also a fast transient
response. Another characteristic of PR current controllers is that they are suitable for
single-phase and three-phase applications: three-phase schemes, implemented in the
frame, provide perfect tracking both for positive and negative sequences [88, 120].
When comparing with other structures, PR current regulators have some interesting
features, specially when active filtering operation is considered; in sum:

Hysteresis current controllers are simple and achieve perfect tracking but, in general,
they have poor switching characteristics (variable switching frequency, maximum ontime). Linear regulators, as PR schemes, overcome these limitations by separating
the modulation and regulation functions [222].
Basic schemes based on linear regulators such as simple proportional and dead-beat
schemes do not achieve zero average steady-state error. In a general way, it can
be said that these kinds of controllers perform worse as higher is the harmonic
component to compensate [3]. PR current regulators seem to be a much better
alternative for APFs.
It has been demonstrated that PR current controllers can perform as the ones based
on Synchronous Reference Frame (SRF) [88]. Under the discrete implementation
point of view, PR controllers are an interesting alternative since Parks transformations are not needed [88, 120].
Lately, repetitive regulators based on the discrete cosine transform (DCT) have been
proposed as an alternative to PR controllers [219, 223]. There are more similarities
than differences when both schemes are compared [219]. However, the PR structure
has been chosen in this work due to the fact that its frequency adaptation is more
approachable, since less digital filter coefficients (taps) are involved.

Focusing the problem in PR current regulators for APFs, their open loop transfer
function should have resonant peaks at selected frequencies, as well as at the fundamental
one [119, 120]. The resonance at fundamental frequency provides perfect tracking at

5.1 Introduction

155

fundamental currents (i.e. for dc bus control) as well as total rejection to the fundamental
component of the grid voltage (disturbance) [119].
A practical problem of resonant filters, and hence in PR controllers, arises with gridfrequency deviations owing to their high selectivity; if not compensated, frequency variations cause that resonant peaks do not coincide with input wave frequencies and, therefore,
perfect tracking/rejection is not assured [88]. This problem may be specially critical in
isolated systems where ranges of operation within a range of 2 Hz, or higher, are
taken into account [224]. Indeed, the higher the frequency deviation, the lower the gain;
so, in practice, for so high non-compensated frequency deviations, a PR controller works
as a simple proportional one [88].
With regard to frequency adaptation of resonant controllers, it should be reminded
that there is no benefit to be gained in using damped resonant implementations [88].
Different works have proposed the use of phase locked loops (PLLs) to adapt repetitive and
resonant controllers (resonant peaks) to the grid frequency [2, 119, 218, 223]. A variable
sample rate repetitive controller, where the sampling frequency is driven by the PLL,
has been proposed in [223]. This solution could be approached for PR implementation.
However, the drawback of this option is that, depending on the discrete device, a variable
sample rate implementation could not be a trivial task. Another interesting proposal is
to decompose each resonant controller in two integrators and use the resonant frequency
as an input. The difference equation is updated online using the frequency estimation of
a PLL [2, 119, 218]. The problem of this approach is the fact that the two integrators
based implementation causes a significant displacement of the resonant poles, as proved
below. On the other hand, the maximum level of ripple from the PLL estimation was not
assessed in previous works.
In this chapter the discrete-time implementation of single-phase APF based on a novel
frequency adaptive PR current controller is approached. The APF performs a selective
harmonic cancellation of 3rd , 5th and 7th harmonics. The difference equation of each
resonant controller is obtained from the impulse invariant discretization method, which
provides an accurate placement of the resonant peaks. These difference equations are
updated online accordingly by means of the PLL estimation of the grid-frequency deviation. Experimental results show how the proposed APF achieves perfect tracking for a
big range of input frequencies as well as its robustness under different kinds of distorted
conditions. The maximum allowable level of ripple from the PLL frequency estimation
has been assessed experimentally.

156

Chapter 5 Frequency Adaptive PR Current Controller for APFs

Table 5.1
Significant values of the power circuit.

5.2

Parameter

Value

vdc

220 V

vSrms

110 V

1 mF

ZF

LF + RF

LF

5 mH

RF

0.5

LS

50 H

fsw = fs

10 kHz

tcomp

12 s

Active Power Filter Prototype

Fig. 5.1 depicts the scheme of the lab prototype and its discrete controller. Table 5.1
shows the significant values of the hardware.
The power supply is composed of two programmable single-phase ac sources Chroma
61501 working in parallel. This configuration supplies a maximum power of 1 kVA. The
APF is an IGBTs based voltage source converter (VSC) connected to the point of common
coupling (PCC) through the filter impedance (ZF ). The whole load is composed of two
non-linear loads also connected to the PCC: an uncontrolled rectifier and an ac regulator.
A manual switch has been placed before the ac regulator in order to cause load transients.
The discrete controller has been implemented in the dSpace DS1103 platform, which
implements Matlab/Simulink models in real-time. The discrete solver has been chosen
so all the controller blocks are digital filters in the Z-domain (neither ode solvers nor
continuous blocks). The sampling frequency (fs ) and IGBTs switching rate (fsw ) have
been set to 10 kHz; the sampling period Ts is defined as 1/fs . System currents and voltages
have been sensed using LEM-LA55P and LEM-LV26V sensors, respectively. These sensed
signals are acquired through the I/O interface of the dSpace target. The average time of
operation tcomp was around 12 s. Fig. 5.2 shows a picture of the built prototype as well
as a capture of a ControlDesk layout in real-time operation.
The goals of the digital control are: to compensate for the selected load harmonic
currents and to keep constant the dc-link voltage (vdc ). The proposed controller works as
follows.

The instantaneous load current iL is detected.

157

5.2 Active Power Filter Prototype

MANUAL
SWITCH

vS

iS

LS

AC REGULATOR

iL

PCC

vPCC
VSC
vDC

vF ZF

UNCONTROLLED
RECTIFIER

iF

PWM

iL

vPCC
P+RESONANT
CURRENT
REGULATOR

vDC

PI
*

vDC

HARMONIC
EXTRACTION

sin( 1 )

PLL
X

iF
-

+
+

iF*

i1*
+

iLh*

DIGITAL CONTROLLER (dSpace DS1103)

Figure 5.1: APF prototype and controller.

The reference harmonic currents to compensate (iF h ) are extracted from iL by means
of digital signal processing. A selective extraction of 3rd , 5th and 7th components is
performed using SRF-MAFs [148] (iF h = iL3 + iL5 + iL7 ).
The reference current iF 1 , calculated to maintain vdc , is obtained through a PI
controller and the in-phase signal from the PLL [18]. The subscript 1 emphasizes
the fact that only the fundamental component is controlled to set the active power
flow from the PCC to the VSC dc-link.
The total reference of current for the APF (iF ) is calculated as iF h + iF 1 .
The PR current regulator assures that (iF iF ) is zero in steady-state (for the
fundamental, 3rd , 5th and 7th harmonic components).

The PLL and PR schemes are detailed in subsequent sections.

158

Chapter 5 Frequency Adaptive PR Current Controller for APFs

(a) Detail of dSpace ControlDesk layout.

VSC
I/O Interf
Non-linear
Load circuits

Box with
sensors (PCC)

PC with
dSPace
DS1104

Non-linear
Load circuits

AC Sources
connected
in parallel

(b) Photo of the lab prototype.

Figure 5.2: Experimental set-up features.

159

5.3 Phase Locked Loop

2 3

MAF2

2 3

vPCC ( p.u.)

1e

PI

cos(1 )
sin( )
1

MAF1

cos(u)

+ +

1n
2 53

2 47

sin(u)

Figure 5.3: Phase locked loop.

5.3

Phase Locked Loop

A single-phase PLL has been implemented to track online the phase-angle (1 ) and
frequency (1 ) of vP CC fundamental component. Fig. 5.3 shows the PLL block diagram.
It uses a multiplier as phase detector. The loop filter is composed of a proportional
integrator (PI) controller and a moving average filter (MAF1), for which the equivalent
transfer functions are

C(z)P I =

c1 c0 z 1
1 z 1

(5.1)

and
1 1 z n

,
(5.2)
n 1 z 1
respectively. The PI controller assures that 1 and 1 are tracked with zero average
steady-state error, even though 1 6= 1n [78, 112114]. A second MAF (MAF2) with
the same transfer function as C(z)M AF 1 can be placed before
1 estimation in order to
control the
1 ripple.
C(z)M AF 1 =

The PLL outputs are employed with the following goals:

1. A normalized in-phase signal (sin(1 )) is multiplied by the output of the PI controller
to obtain iF 1 [18].
2. The frequency estimation is employed to generate the multiple SRF waves of the selective extraction algorithm. The frequency value is saturated to avoid malfunctions
during vP CC transients [148].
3. Usually, digital PLLs are designed to have a feedforward frequency (1n ), so the
closed-loop path provides a correction (
1 ) around it (
1 = 1n +
1 ). This

160

Chapter 5 Frequency Adaptive PR Current Controller for APFs

Table 5.2
Values of PLL parameters.

Parameter

Value

c1

c0

1.995

n (MAF1)

100

n (MAF2)

100

100

Magnitude (dB)

50

0
-50

-100

-150

-200

Phase (deg)

-90

-135

PM=31 deg

-180
-225

-270
-1

10

28

100

Frequency (Hz)

1000

10000

Figure 5.4: Open loop PLL Bode diagram.

work extends this approach to resonant controllers design: the difference equation
of each one is function of h 1n and h
1 (see section 5.4).

5.3.1

PLL Tuning

PLLs have a trade-off between transient response and filtering: the higher the bandwidth the faster the transient response but the worse the harmonic cancellation. Specially
critical is the internal second harmonic generation in multiplier based single-phase PLLs.
If not canceled, this second harmonic causes ripple in
1 ,
1 and 1 , which could affect
to the whole controller performance [112114].
Fig. 5.4 shows the open loop frequency response of the linear PLL. The values of the
coefficients are shown in table 5.2. Stability and bandwidth optimization has been sought
during the tuning process [112114]. The phase margin (PM) could be considered a bit
low for a controller design, but, in the case of PLL tuning, a very big increase in vSrms is
not expected, so stability is assured with this PM [112114].

161

5.4 PR Current Controller

Forward
Euler

iF*-iF

Ts z 1
1 z -1
Ts
1 z -1

output

12

Backward
Euler

Figure 5.5: Two integrators based implementations, as proposed in [2].

From Fig. 5.4, when 1 = 1n , thanks to MAF1 all the harmonics, including the
second one, are canceled. However, when 1 6= 1n perfect harmonic cancellation is not
achieved.
It is out of the scope in this chapter to show how to optimize more the PLL loop filter
in order to reduce jittering. Instead of it, harmonic ripple effect in PR current controllers
is studied. In this work, control over ripple has been achieved by placing/removing MAF2.

5.4
5.4.1

PR Current Controller
Resonant Controllers Implementation

Resonant filters are undamped GIs which can be implemented as two linked integrators [119]. Frequency adaptation is provided by means of PLL estimation [2, 119, 218].
Regarding the discretization method, it has been suggested to discretize the direct integrator using Forward Euler method while the feedback one is discretized using the Backward
Euler method, as shown in Fig. 5.5 [2]. The resulting transfer function in the Z-domain
is:

z 1 z 2
.
Rtwo (z) = Ts
1 + z 1 (12 Ts2 2) + z 2

(5.3)

It can be checked that to discretize the two integrators separately results in a displacement of the resonant peaks from the expected values. However, the linear dependence of
the different equation on 12 eases the frequency adaptation.
To use the Z-transform of the cosine wave was proposed in [120]. This means, in
practice, to discretize a second order generalized integrator with the impulse invariant

162

Chapter 5 Frequency Adaptive PR Current Controller for APFs

method, giving rise to the following resonant controllers:

Rii (z) = Ts

1 z 1 cos(1 Ts )
.
1 2z 1 cos(1 Ts ) + z 2

(5.4)

This method results much more accurate, as shown in Fig. 5.6. Its drawback appears when frequency adaptation is desired, since trigonometric functions are involved. A
method to avoid explicit cosine wave calculations is provided in section 5.4.2.
The error induced by the two integrators based implementation may be acceptable for
some applications handling with very low order harmonics and fundamental. However,
the loss of performance is very significant for higher harmonics. Rii (z) seems to be a
better choice, specially for APFs.
A PR controller (C(z)) of the form of (5.5) has been selected for implementation. Ts
is a constant term so it can be included in each Kh .

C(z) = KP +

KRh Ts

h=1,3,5,7

1 z 1 cos(h 1 Ts )
=
1 2 z 1 cos(h 1 Ts ) + z 2

1 z 1 cos(h 1 Ts )
KP +
KRh
.
1 2 z 1 cos(h 1 Ts ) + z 2
h=1,3,5,7

(5.5)

5.4.2

Frequency Adaptive Implementation of Resonant Blocks

From (5.5), it seems immediate to update the terms cos(h 1 Ts ) using

1 from
the PLL [225]. The main drawback of this approach is that it requires computation of
trigonometric functions online. The explicit implementation of the cosine function can be
avoided, using the proposed Taylor approximation detailed as follows.
In a similar manner that the digital PLL of Fig. 5.3 works around the equilibrium
point established by 1n , the PR current regulator of (5.6) has been derived from (5.5):
assuming that h
1 Ts 0, the equilibrium point strategy of PLL is also applied to
resonant controllers.

1 z 1 (cos(h 1n Ts ) h
1 Ts sin(h 1n Ts ))
.
C(z) = KP +
KRh
1
1 2 z (cos(h 1n Ts ) h
1 Ts sin(h 1n Ts )) + z 2
h=1,3,5,7
(5.6)
X

Fig. 5.7 shows the implementation block for each resonant controller. Block diagram

163

5.4 PR Current Controller

Hz

Two integrators based implementation

Impulse Invariant based implementation

100

200

300

400

500

600

Hz

Figure 5.6: Comparative of the error induced by different implementations (fs = 10 kHz).
iF*-iF

KRh

+
+
-

ah

Z-1

Z-1

bh

++

+
-

To adder

2
Precalculated constants:
ah = cos(hw1nTs)
bh = sin(hw1nTs)

1
(From PLL)

hTs

Figure 5.7: Frequency adaptive resonant block implementation.

algebra has been applied to optimize the implementation set by (5.6), so the number of
multiplications by non-fixed coefficients (
1 ) has been reduced to one.
Fig. 5.8 shows the accuracy of the approximation for each resonant block. The higher
the harmonic order, the worse the approximation, since a shift of 1 Hz at fundamental
results in a h 1 Hz shift at the harmonic h. At any rate, this error can be considered
low enough, even for significant frequency deviations, as proved in section 5.5.

5.4.2.1

Effect of the Frequency Correction in Dynamics

As explained, when
1 6= 0 the resonant peak is moved to the estimated frequency;
i.e. Fig. 5.9 shows the effect of the frequency correction around the 3rd harmonic resonant
peak. It could be said that when the peak is well centered the PR is working as an ideal
resonant controller (infinite gain), but in other case the performance tends to approach

164

Chapter 5 Frequency Adaptive PR Current Controller for APFs

Hz

0.35

Fundamental
3rd harmonic
5th harmonic
7th harmonic

0.25

0.15

0.05

-1.5

-0.5

0.5

1.5

Hz

Figure 5.8: Accuracy of the resonant controllers (fs = 10 kHz).

100
Magnitude (dB)

90

1<0

80

1>0

70

60
50

40
30

Proportional
controller

Resonant
controller

Proportional
controller

Phase (deg)

20

45

0
-45
-90

-135

-180
149.8

149.9

149.98 150 150.02

Frequency (Hz)

150.1

150.2

Figure 5.9: Frequency response of C(z) P (z) around 150 Hz. When
1 > 0 the peak
moves to higher frequencies and vice versa.
the one of a proportional controller. The exact place to depict the resonant/predictive
borderline in that figure could be considered a subjective issue. The idea is to show how
a practical very high gain is sought with frequency adaptation.

1 , as obtained from a PLL, can be written as

1 +
1 ,

1 =

(5.7)

1 and
1 are the average value and an oscillating term associated with jittering,
where
respectively.
1 is tracking perfectly, that is,
From Fig. 5.9, the best performance occurs when
1 = 0 (no jittering). The first condition is
the resonant peak is well centered, and
easily performed by any PLL, but the second one is more complicated, specially under

165

5.4 PR Current Controller

vPCC
iF*

+-

C ( z)

G (z )

iF

Plant Model P(z)

iF

Figure 5.10: Current control block diagram.

distorted conditions [112114]. Analytical expressions of the maximum level of jittering
seem to be very complex to obtain. Alternatively, the quantification of the maximum
level of jittering has been assessed by experimental tests.

5.4.3

Design and Tuning of C(z)

Fig. 5.10 depicts the current control system including the PR controller C(z) and the
model of the plant P (z). P (z) has been modeled including the computational delay (z 1 )
and the PWM converter operation. The PWM reference (m) is kept constant over each
sampling interval, so the power converter can be assumed to be a zero order hold (ZOH)
circuit. Therefore, the filter inductance discrete-time model (G(z)) should be obtained
through the ZOH method, as follows [3, 226]:

G(s) =

1 1 eRf Ts /Lf
1
ZOH

G(z) =
.
sLF + RF
Rf z eRf Ts /Lf

(5.8)

The effect of the ZOH circuit is noticeable at high frequencies, since an extra phase
lag is introduced in the current control loop, and it should be taken into account when
tuning C(z).
As said in the introduction, resonant controllers provide perfect tracking (and disturbance rejection) of currents for which frequency C(z) P (z) has infinite gain.
Fig. 5.11 shows C(z) implementation. Four resonant blocks have been implemented
in the APF controller: one at fundamental component to provide perfect tracking of iF 1
(vdc control) and vP CC fundamental rejection, and the other three ones to provide perfect

tracking of iF 3 , iF 5 and iF 7 . The term 1/vdc

is included so Kp and Kh tuning is made
independent from vdc (plant).
The controller C(z) has been tuned by inspection of C(z) P (z) transfer function
[120, 219]; 1 = 1n has been considered. Fig. 5.12 shows C(z) P (z) frequency response
and the parameters are specified in Table 5.3. From Fig. 5.12, the implemented PR
controller has the following features:

166

Chapter 5 Frequency Adaptive PR Current Controller for APFs

iF*-iF

^1

KP
Res.1st

Res.3rd

Res.5th

Res.7th

(From PLL)

Figure 5.11: PR block (C(z)).

Table 5.3
Values of parameters of the PR controller.

Parameter

Value

KP

25

KR1

0.1

KR3

0.1

KR5

0.1

KR7

0.1

High enough phase margin (P M = 46 deg) so that stability is assured.

Perfect tracking and disturbance rejection at resonant peaks are expected.
A fast transient response is expected: the open loop cut-off frequency and hence the
system bandwidth are around 800 Hz.

167

5.5 Experimental Results

Magnitude (dB)

100
80
60
40
20

0
-20
180

Phase (deg)

135
90
45

0
-45
-90
-135

-180
10

PM=46 deg.

100

800 1000

Frequency (Hz)

Figure 5.12: Bode diagram of C(z) P (z).

5.5

Experimental Results

Different tests have been carried out to show how the APF performs both in steadystate and under transients.
Fig. 5.13 shows experimental results obtained from steady-state operation when an
input frequency sweep has been carried out. Oscilloscope figures show results at nominal (50 Hz) and very shifted (48 Hz) frequencies; system currents and vP CC are displayed.
It should be noticed that iL spectrum varies slightly with the frequency due to load reactances. Fig. 5.13g depicts a table with all the results of the input frequency sweep. These
results prove that the 3rd , 5th and 7th harmonics of iL are not present in iS . Therefore,
perfect tracking of the APF harmonic reference is achieved. The fundamental component
of iS is slightly higher than iL1 , since vdc should be maintained.
Fig. 5.14 shows experimental results when there is a load transient. Initially only the
uncontrolled rectifier is connected to the PCC and then the ac regulator starts up. As
expected from the PR controller bandwidth (800 Hz) the system has a very fast transient
response. It should be noticed that the extraction algorithm settling time is 0.01 s and
also affects to dynamics [148].
Fig. 5.15 illustrates the APF response when there is a sudden step in f1 . Fig. 5.16
depicts results from a similar test but showing
1 from the PLL in Ch2. In both cases,
the PR current regulator and, therefore, the whole system presents a very good frequency
adaptation. The frequency step has been detected inside the dSpace model and connected

168

Chapter 5 Frequency Adaptive PR Current Controller for APFs

(a) Steady-state currents and voltage at the (b) Fourier spectra of iL in (c) Fourier spectra of iS in
PCC when f1 = 50 Hz.
Fig. 5.13a (Ch1).
Fig. 5.13a (Ch3).

(d) Steady-state currents and voltage at the (e) Fourier spectra of iL in (f) Fourier spectra of iS in
PCC when f1 = 48 Hz.
Fig. 5.13d (Ch1).
Fig. 5.13d (Ch3).
48 Hz

49 Hz

50 Hz

51 Hz

52 Hz

iL

iS

iL

iS

iL

iS

iL

iS

iL

iS

3.02 A

3.2 A

2.96 A

3.13 A

2.87 A

3A

2.79 A

2.94 A

2.71 A

2.87 A

886 mA

30 mA

874 mA

10 mA

856 mA

4 mA

826 mA

14 mA

738 mA

25 mA

223 mA

8 mA

206 mA

5 mA

199 mA

4 mA

190 mA

6 mA

186 mA

9 mA

176 mA

13 mA

153 mA

9 mA

134.6 mA

3 mA

115 mA

6 mA

94 mA

11 mA

(g) Values of harmonic current of the load and the source for different frequencies.

Figure 5.13: Steady-state currents and vP CC for different input frequencies. Ch1 is iL ,
Ch2 is iF , Ch3 is iS and Ch4 is vP CC .

5.5 Experimental Results

169

Figure 5.14: Transient response when there is a load change. Ch1 is iL , Ch2 is iF , Ch3 is
iS and Ch4 is vP CC .

Figure 5.15: Transient response when there is a frequency step in f1 from 48 Hz to 52 Hz.
Ch1 is iL , Ch2 is iF , Ch3 is iS and Ch4 is vP CC .

to the oscilloscope external trigger. Again, it is noticeable the change in iL spectrum due
to the frequency dependence of load reactances.
Figs. 5.15 and 5.16 have been obtained by implementing the PLL with MAF2. As
expected,
1 is ripple-less (two MAFs). Fig. 5.17 results have been obtained repeating
the previous test, but eliminating MAF2 from the PLL. In this test, a second-harmonic
1 oscillates 1 Hz around
1 . This result is very interesting,
oscillating term
and even quite surprising, since the practical high performance of the PR controller is
kept. Even though, posterior tests made by the authors with a higher level of jittering
(3 Hz) resulted in instability, it is clear that this implementation is very robust under
the presence of harmonics/noise ripple in the frequency estimation.
1 = 0, that is, a PR without frequency
Another test has been made considering
adaptation. Fig. 5.18 shows results obtained when the input frequency is 48 Hz. The
same results have been obtained testing with a current controller C 0 (z) = KP . Therefore,
the PR controller without frequency adaptation behaves equal that a simple proportional
regulator.

170

Chapter 5 Frequency Adaptive PR Current Controller for APFs

Figure 5.16: Transient response when there is a frequency step in f1 : from 52 Hz to 48 Hz.
Ch1 is iL , Ch2 is
1 (scale at 23 rad/div), Ch3 is iS and Ch4 is vP CC .

Figure 5.17: Transient response when there is a frequency step in f1 from 48 Hz to 52 Hz.
Effect of ripple of 1 Hz in
1 . Ch1 is iL , Ch2 is 1 (scale at 23 rad/div), Ch3
is iS and Ch4 is vP CC .
Finally, the prototype has been tested when there is a voltage sag (from 1 p.u. to
0.8 p.u.) with phase-angle jump (+45 deg) in vP CC (programmed in vS ). The test has
been made at 49 Hz (
1 = 2 rad/s). When the fault occurs the PLL frequency
increases, but
1 to the PR is limited to 23 rad/s. As shown in Fig. 5.19, this
protection is crucial and steady-state is achieved in 1 2 cycles. It should be noticed
that the fault also affects to the extraction algorithm [148].

171

5.5 Experimental Results

(a) Steady-state currents and voltage at the (b) Fourier spectra of iL (c) Fourier spectra of iS
PCC when f1 = 48 Hz.
(Ch1 of Fig. 5.18a).
(Ch3 of Fig. 5.18a).

48 Hz

49 Hz

50 Hz

51 Hz

52 Hz

3.14 A

3.08 A

3.02 A

2.90 A

2.85 A

349 mA

282 mA

4 mA

297 mA

320 mA

71 mA

60 mA

4 mA

73 mA

81 mA

56 mA

38 mA

3 mA

29 mA

32 mA

(d) Values of iS for

1 = 0 (No frequency adaptation).

Figure 5.18: Steady state figures when error in estimation of

1 is considered.

1 = 0 rad/s and 1 = 4 rad/s (f1 = 48 Hz). Ch1 is iL , Ch2 is 1 (scale at

23 rad/div), Ch3 is iS and Ch4 is vP CC .

Figure 5.19: Transient response when there is a voltage sag (1 p.u. 0.8 p.u.) with phaseangle jump of +45 deg in vP CC (vS ). Ch1 is iL , Ch2 is 1 (scale at 23 rad/div), Ch3
is iS and Ch4 is vP CC .

172

5.6

Chapter 5 Frequency Adaptive PR Current Controller for APFs

Conclusions

A novel approach in the implementation of PR current regulators is contributed in

this chapter. More specifically, the issue of frequency adaptation using a PLL is deeply
analyzed. From this study, some practical conclusions of significant importance can be
extracted. In sum:

1. Resonant controllers implementations based on the impulse invariant discretization

are more reliable for APFs than the ones based on two discrete integrators.
2. The impulse invariant resonant controllers can be made frequency adaptive by means
of a PLL estimation of the grid-frequency deviation. The proposed implementation
has good performance and no needed of explicit trigonometric functions.
3. The most critical parameter of the PLL is its accuracy detecting the average value of
the fundamental frequency. Jittering in
1 should be reduced as much as possible,
even though high robustness to this parameter is provided.
4. The tested resonant controllers achieve perfect tracking even for the worst case (7th
harmonic and 2 Hz deviation), so it is also expected a good performance in APF
applications compensating for higher order harmonics.
5. The proposed PR controller has a very high bandwidth and, therefore, the system
has a very fast transient response. The whole controller is robust under all kind of
transients such as load changes, frequency variations, and even input voltage sags.
It should be remarked that some PLL outputs (estimations) have been saturated to
avoid malfunctions.

Chapter 6
Conclusion and Future Work
6.1

Conclusion

This dissertation addresses the issue of grid-synchronization for power electronics converters. Its main contributions and conclusions are summarized below.

A thorough review of the State-of-the-Art is contributed. The problem of frequency

adaptation is presented as the most important practical issue in the implementation
of discrete algorithms.
Methods based on SRF-MAF both for grid-synchronization as well as for harmonics/sequences extraction are provided. It is also proved that there is a close relation
between these implementations and other based on DFT and DCT.
An in-depth analysis of the dynamics of low-gain PLLs. It is proved that, opposite as
considered in some works, overdamped tuning should be avoided when considering
frequency deviations.
A novel methodology based on RC oscillator model to optimize the discrete implementation is contributed.
An open-loop frequency adaptive SRF-MAF algorithm providing an accurate and
fast grid phase-angle estimation is contributed.
A novel approach on the implementation of PR current controllers is contributed.
The provided APF implementation proves the high performance of the proposed
implementation as well as the robustness and frequency adaptability of the solution.
173

174

6.2

Chapter 6 Conclusion and Future Work

Publications

Research work included in the dissertation has given rise, at the moment, to three
journal papers [114, 147, 148] and eight conference papers [112, 113, 127, 146, 149
151, 209]. A summary of the contributions of each journal paper is detailed as follows:

1. The basics of SRF-MAF synchronization/extraction algorithms, presented in chapter 2, are detailed in [148]. This paper focuses more in extraction for active power
filters than in synchronization itself.
2. The tuning methodology for PLLs proposed in chapter 3 is provided in [114].
3. The synchronization method based on SRF-MAFs and predictive filters, presented
in chapter 4, is provided in [147].

6.3

Future Research

There are several interesting topics suggested for further research. Some of them are
described in the following:

As shown in chapter 5, frequency adaptation of PR controllers is not a trivial task.

An immediate future task is to compare more deeply the provided technique based
on Taylor approximations with other alternatives presented in technical literature.
A more in-depth research of the applicability of the different synchronization algorithms (proposed and studied) in distributed power generation applications in order
to fulfill with existing normative (Grid codes).
Rotor position and speed estimation of synchronous machines operating at any
speed.
Implementation of the most significant proposals (Predictive SRF-MAF, Adaptive
PR current controllers,...) in industrial devices such as FPGAs and DSPs.
It is also expected to carry out solutions for industry based on the contributions of
this thesis.

Appendix A
Matlab Scripts

175

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Chapter A Matlab Scripts

%% Matlab Script for executing the Ainsworth model

%% Main File
%% Francisco D. Freijedo, Glasgow, August 2008
clear all
% Step of the simulation.
% Input Frequency
% Final time of the simulation
% Time of a transient
% Time vector
%R eq
% L eq
% Initial value of current
% initalize output current reference
% initial condition for VCO phase
%inital value of grid phase
% initalize frequency correction of VCO
% initalize error vector
% initalize output current vector
% initalize output current vector average value
% initizalize Vd output vector
% initialize output frequency correction vector
while
% time for each simulation loop
if taux>ttran
% transient changes
end
%function call
[il,Vd,Vln,phaseVCO,wcorr,e,phaseGrid]=calc_icl(tsim,Ts,w1,...
taux=taux+tsim % show current simulation time
% update output vector
% save output current value for next function call
% save output current average value

end
% Visualize values
% PLOT CURRENTS

%PLOT STEADY-STATE VOLTAGES

plot((0:length(Vln)-1)*Ts+tfinal-0.5,Vln,...
(0:length(Vd)-1)*Ts+tfinal-0.5,Vd,[Ts+tfinal-0.5 Ts+tfinal]...
xlabel('Time (s)','FontSize'
ylabel('Current (p.u.)','FontSize'

Figure A.1: PLO system Matlab script. Main file.

177

1 %% Matlab Script for executing the Ainsworth model

2 %% Function file
3 %% Francisco D. Freijedo, Glasgow, August 2008
4
5 function [il,Vd,Vln,phaseVCO,wcorr,e,phaseGrid]=calc_icl(tsim,Ts,w1,R,L,phia,phib,
phic,iin,phaseVCOi,wcorri,iref,ei,phaseGridi)
6
% 30 deg phase offset
7
8 % Initialize current values from previous function calls
9
% Grid phase
10
% VCO phase
11
% VCO correction around the nominal frequency (2*pi*50 rad/s)
12
% Set VCO frequency
% current error signal
13
14
% current value of the system current
15
16
17 % The Ainsworth problem is stated as a state state.
18
19 % .
20 % x=Ax+Bu
21 % y=x
22 % where x=y is the current through L and R and
23 % u is the set line to neutral voltages vector.
24
25
% A in the continuous space state
26
% Discretize of A
27
28 % Definition of the switching functions:
29 % Different swtiching functions are defined since the circuit
30 % depends on the VCO phase. That is, B is changing with VCO phase.
31
32
% Continuos swtiching function
33
% Discretized switching function
34
35
36
% ss en con
37
38
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43
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45
% Initial value of Bd
46
47 for
48
49
% Calculation of instantaneous phase to neutral voltages
50
Va=sin(offset+phaseGrid+phia)/sqrt(3)+0.1*sin(5*phaseGrid)+0.1*sin
51

Vb=1*sin(offset+phaseGrid+phib)/sqrt(3)+0.1*sin(5*phaseGrid+0.1)+0.1*sin

52

Vc=1*sin(offset+phaseGrid+phic)/sqrt(3)+0.1*sin(5*phaseGrid+0.9)+0.1*sin

53
54
55
56

% Error signal vector update

Figure A.2: PLO system Matlab script. Function file (page 1 of 2).

178

Chapter A Matlab Scripts

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% The output of the filter is obtained through the discretized

% transfer function using the tustin method
tmp=1.3333*wcorr(2)-0.33329*wcorr(1)+33.334*e(3)+0.0033332*e(2)-33.331*e

% VCO frequency update

% The phase must be in the range [0,2*pi]

while phaseGrid>=2*pi
end
while

phaseVCO>=2*pi

end
while

phaseVCO<0

end
% Set of Bcd as function of VCO phase (switching functions)
if phaseVCO<=pi/3

end
if phaseVCO>pi/3 && phaseVCO<=2*pi/3

end
if phaseVCO>2*pi/3 && phaseVCO<=pi

end
if phaseVCO>pi && phaseVCO<=4*pi/3

end
if phaseVCO>4*pi/3 && phaseVCO<=5*pi/3

end
if phaseVCO>5*pi/3

end
% Save output current vector
% Save Vd voltage
% Save line to neutral voltages
% Grid phase update
% VCO phase update

Figure A.3: PLO system Matlab script. Function file (page 2 of 2).

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C:\Documents and Settings\anonimo\Mis documentos\MA...\SRF_PP.m

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%% Matlab Script to get SRF-PLL trajectories in the Phase-Plane

% Francisco Freijedo
Ts=1e-4; Tfinal=0.1; t=0:Ts:Tfinal;
wn=2*pi*50; % Feedforward constant at nominal frequency (or =0).
ypd=0; ylfP=0; ylfIv=[0 0 0 0 0 0 0]; theta=0; thetadif=0; difw=[];
diftheta=[];
figure; hold on;
colors=['k' 'y' 'b' 'm' 'g' 'r' 'c']';
phiuv=[pi-0.1 pi/2 pi/4 0 -pi/2 -pi+0.6 -pi+0.1];
limitI=[1000 1000 1000 1000 1000 1000 1000]; %Limit the word lenght
ylf=ylfIv;
for u=1:size(phiuv')
% Create INPUT WAVE for SIMULATION
wu=2*pi*51; % Input wave frequency
phiu=phiuv(u);
thetain=rem((wu*t+phiu)+pi,2*pi)'-pi;
ua=sin(wu*t+phiu); % Input wave definition
ub=sin(wu*t+phiu-2*pi/3); % Input wave definition
uc=sin(wu*t+phiu+2*pi/3); % Input wave definition
% SIMULATE THE PROCESS
ylf=ylfIv(u);
cont=2;
difw=wu-(wn+ylf); diftheta=[phiuv(u)];
for n = 1:Tfinal/Ts % Number ot iterations
ypd(n+1)=ua(n)*cos(theta(n))+ub(n)*cos(theta(n)-2*pi/3)+...
uc(n)*cos(theta(n)+2*pi/3); % Phase Detector (Q15)
ylf(n+1)=(1*ylf(n)+250*ypd(n+1)*1-248*ypd(n)*1);
ylf(n+1)=max([ylf(n+1) -1*limitI(u)]); % Limit LF
ylf(n+1)=min([ylf(n+1) 1*limitI(u)]); %(according to a pipeline)
wo=wn+ylf(n+1);
theta(n+1)=theta(n)+abs(wo)*Ts; % Effect of discard frequency sign
% theta(n+1)=theta(n)+wo*Ts; % Good operation
if theta(n+1)>=pi % Reset phase-angles
theta(n+1)=theta(n+1)-2*pi;
end
if theta(n+1)<=-pi
theta(n+1)=theta(n+1)+2*pi;
end
thetadif(n+1)=thetain(n)-theta(n);
if thetadif(n+1)>pi
thetadif(n+1)=thetadif(n+1)-2*pi;
end
if thetadif(n+1)<-pi
thetadif(n+1)=thetadif(n+1)+2*pi;
end
if abs(thetadif(n+1)-thetadif(n)) < pi
difw(cont)=wu-wo;
diftheta(cont)=thetadif(n+1);
cont=cont+1;
else
plot(diftheta,difw,colors(u),'LineWidth',2); %plot phase plane
cont=1; difw=[]; diftheta=[];
end
end
plot(diftheta,difw,colors(u),'LineWidth',2); %plot phase plane
difw=[];
diftheta=[];
end

Figure A.4: Matlab script to depict SRF-PLL trajectories in the Phase-plane.

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C:\Documents and Settings\anonimo\Mis docume...\KalmanExample.m

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clear all;
t=1e-4:1e-4:0.1;
w1n=2*pi*50; % Kalman filter frequency = Nominal frequency.
w1=2*pi*50; % Fundamental frequency of the input wave.
% Sinusoidal input
% v=sin(w0i*t-pi/4);
% Non sinusoidal input (harmonics)
v=sin(w1*t-pi/4)+0.11*sin(3*w1*t)+0.08*sin(5*w1*t);
% Voltage Sag with pi/4 phase jump
% v=-sin(w0i*t(1:500));
% v=[v -0.5*sin(w0i*t(501:1000)-pi/4)];
%add white noise to the input
% noise=[];
% for i=1:1:1e3
%
noise=[noise;randn*0.05];
% end
% v=v+noise';
xhat=[0;0];
M=[cos(w1n*1e-4) sin(w1n*1e-4);-sin(w1n*1e-4) cos(w1n*1e-4)];
H=[1 0];
p=100;
P=[p 0; 0 p]; % Set P(0).
q=0.001;
Q=[q 0; 0 q]; % States covariance Matrix. High q ==> high K.
R=5; % Measurement covariance. High R ==> low K.
x=[];
phase=[];
for i=1:1:1e3
% Innovation
Inn = v(i) - H * xhat;
% Covariance of Innovation
s = H * P * H' + R;
% Gain matrix.
K = M * P * H' * inv(s);
% State estimate
xhat = M * xhat + K * Inn;
% Covariance of prediction error
P = M * P * M' + Q - M * P * H' * inv(s) * H * P * M';
%Save values
x=[x xhat];
phase=[phase atan2(xhat(1),xhat(2))];
end
plot(t,v,t,x);
figure;
plot(t,phase);

Figure A.5: Matlab script of the Kalman Filter Single-phase synchronization example.

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%% Matlab Script for testing the WLSE synchronization algorithm (3-phase)

%% Francisco D. Freijedo, Vigo, December 2008.
clear all;
t=1e-4:1e-4:0.1;
w1n=2*pi*50; % Nominal frequency ==> System frequency
w1=2*pi*50; % Input wave frequency.
% A transient is programmed in the input wave. The distorted signal has
% unbalance.
Va=1*cos(w1*t(1:499)-pi/6);
Vb=1*cos(w1*t(1:499)-2*pi/3-pi/6);
Vc=1*cos(w1*t(1:499)+2*pi/3-pi/6);
Va=[Va 1*(sin(w1*t(500:1e3)))];
Vb=[Vb 0.6*sin(w1*t(500:1e3)-2*pi/3+0.4)];
Vc=[Vc 0.9*sin(w1*t(500:1e3)+2*pi/3+0.3)];
% The error covariance is initialized.
P=300*[1 0 0 0;0 1 0 0;0 0 1 0; 0 0 0 1];
lamb=0.95; % Forgetting factor
lambinv=1/lamb;
ang1vec=[];
x=[0 0 0 0]'; % x is v_{dq}^{+-}
xvec=[];
angvec=[];
vab=[];
for i=1:1:1e3
Vabc=[Va(i) Vb(i) Vc(i)]; % Input wave
Talfabeta=(2/3)*[1 -1/2 -1/2;0 -sqrt(3)/2 sqrt(3)/2];
Valbe=Talfabeta*Vabc'; % input wave in alfa beta frame
vab=[vab Valbe]; % Save alfa beta frame values
H=[cos(w1n*t(i)) sin(w1n*t(i)) cos(w1n*t(i)) -sin(w1n*t(i));...
-sin(w1n*t(i)) cos(w1n*t(i)) sin(w1n*t(i)) cos(w1n*t(i)) ];
r=[1 0; 0 1]+H*P*H'; % compute of R matrix
rinv=inv(r);
k=P*H'*rinv; % Compute of K gain.
P=lambinv*P-lambinv*k*H*P; % Update of error covariance
xhat=x+k*[Valbe-H*x]; % Output voltage update
xvec=[xvec xhat]; % Save values of SRF coefficients
% Compute of phase angle of fundamental positive sequence vector
angvec=[angvec atan2(xhat(1)*cos(w1n*t(i))+xhat(2)*+sin(w1n*t(i)) ...
,(-xhat(1)*sin(w1n*t(i))+xhat(2)*cos(w1n*t(i))))];
x=xhat; % for next sample...
end
plot(t,Va,t,Vb,t,Vc);
figure;
plot(t,vab);
figure;
plot(t,xvec);
figure;
plot(t,angvec);

Figure A.6: Matlab script of the WLSE syncrhonization example.

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C:\Documents and Settings\anonimo\Mis d...\pll_single_iecon08.m

clear all;
Ts=1e-4; % Sampling time (= 1/fs).
Tfinal=0.8; % Time for the simulation.
t=0:Ts:Tfinal; % time vector.
wn=2*pi*50; % Nominal frequency.
Mysin=[0;0]; % Initialize Mysin.
Mycos=[0;0.99]; % Initialize Mycos.
ypd=[0;0]; % Initialize PD output.
ylf=[0;0]; % Initialize LF output.
ynotch=[0;0]; % Initialize notch filter output.
theta=[0;0]; % Initialize phase angle
% Create INPUT WAVE for SIMULATION
wu=2*pi*50.3; % Input wave frequency
u=sin(wu*t+pi); % Input wave definition
% SIMULATE THE PROCESS
for n = 2:Tfinal/Ts % Number ot iterations
ypd(n+1)=u(n)*Mycos(n); % Phase Detector (Q15)
% Notch Filter (Q15)
%ynotch(n+1)=ypd(n+1);
ynotch(n+1)=1.94*ynotch(n)-0.944*ynotch(n-1)+...
0.972*ypd(n+1)-1.94*ypd(n)+0.972*ypd(n-1);
% Loop Filter Q(8)
ylf(n+1)=(1*ylf(n)+250*ynotch(n+1)-247.8*ynotch(n));
% Limit LF according to its Q8 size pipeline
ylf(n+1)=max([ylf(n+1) -128]);
ylf(n+1)=min([ylf(n+1) 128]);
% Update Output frequency and compensate 1/2 (Q6)
wo=wn+2*ylf(n+1);
% Integration process (digital oscillation)
Mysin(n+1)=Mysin(n)+wo*Ts*(Mycos(n));
%(Q15)
Mycos(n+1)=Mycos(n)-wo*Ts*(Mysin(n));
%(Q15)
% Limit the oscillator integrators
Mysin(n+1)=max([Mysin(n+1) -0.99]);
Mysin(n+1)=min([Mysin(n+1) 0.99]);
Mycos(n+1)=max([Mycos(n+1) -0.99]);
Mycos(n+1)=min([Mycos(n+1) 0.99]);
% Update the output phase (Q12)
theta(n+1)=theta(n)+wo*Ts;
% Output phase reset condition
if Mysin(n)>=0 && Mysin(n+1)<=0
theta(n+1)=-pi;
end
end
plot(t,u,t,Mysin,t,theta); % Plot experimental results

Figure A.7: Matlab script of the single-phase PLL with RC-Oscillator based DCO.

1 of 1

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