Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

ECE 4104
EXPERIMENT #8

UNIVERSAL SHIFT REGISTERS

Members:
Jiles C. Maasin
John Emmanuel S. Nacion
Cleo P. Rubino
Submitted to:
Engr. Ramon A. Alguidano Jr.
Instructor

Date Performed:
October 12, 2016
Date Submitted
October 18, 2016

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

OBJECTIVES:
1.
2.
3.
4.
5.

To define a universal shift register

To define the IC used in a universal shift register
To know the specification of the IC used for a universal shift register
To apply the IC in a circuit
To compare the output of the designed circuit and the truth table of the IC.

BASIC THEORY
Universal Shift Register is a register which can be configured to load and/or
retrieve the data in any mode (either serial or parallel) by shifting it either towards right or
towards left. In other words, a combined design of unidirectional (either right- or left-shift of
data bits as in case of SISO, SIPO, PISO, PIPO) and bidirectional shift register along with
parallel load provision is referred to as universal shift register.
SISO (Serial-In, Serial-Out) shift register, are the simplest kind of shift registers.
The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance'
is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first

flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
The next is SIPO (Serial-in, Parallel-Out), this configuration allows conversion
from serial to parallel format. Data is input serially, as described in the SISO section above.
Once the data has been clocked in, it may be either read off at each output simultaneously, or it
can be shifted out.
PISO (Parallel-In, Serial-Out), this configuration has the data input on lines D1
through D4 in parallel format, D1 being the MSB. To write the data to the register, the
Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought
HIGH and the registers are clocked. The arrangement now acts as a SISO shift register, with D1
as the Data Input. However, as long as the number of clock cycles is not more than the length of
the data-string, the Data Output, Q, will be the parallel data read off in order.

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

Schematic

Figure 1 Schematic

Truth Table
FIGUR
E

MODE

CLEAR S S
0
X
X

INPUTS
SERIAL
CLOC
LEF
RIGH
K
T
T
X
X
X
L
X
X

1
2

L
H

1
X
X

PARALLEL

QA

OUTPUTS
QB QC QD

A B C D
X
X

X
X

X
X

X
X

L
QAO

L
QBO

L
QCO

L
QDO

QAn

QBn

QCn

QAn

QBn

QCn

QBn

QCn

QDn

QBn

QCn

QDn

QAO

QBO

QCO

QDO

Figure 2 Truth Table

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

Truth Table Information

H= high level (steady state)

L= low level (steady state)
X= irrelevant (any input, including transitions)
= transition from low to high level

a, b, c, d= the level of steady-state input at inputs A, B C or D, respectively

QAO, QBO, QCO, QDO= the level of QA, QB, QC or QD respectively, before the indicated steadystate input conditions were established.
QAn, QBn, QCn, QDn= the level of QA, QB, QC or QD respectively, before the most recent
transition of the clock.

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

PROCEDURES AND RESULTS

EQUIPMENT NEEDED
1. Laptop or PC with Multisim

PROCEDURE
1.
2.
3.
4.

Open Multisim
Make the connection as shown in Figure 1 Schematic
Test the combinations given in the truth table. (See Figure 2 Truth Table)
Compare the output of the truth table and the result of the simulation.

RESULTS

Figure 1

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

Figure 2

Figure 3

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College of Engineering
Department of Electronics and Communications Engineering

Figure 4

Figure 5.1

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

Figure 5.2

Figure 6.1

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

Figure 6.2

Figure 7

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College of Engineering
Department of Electronics and Communications Engineering

Figure 8

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

OBSERVATION
In this experiment, the researchers followed the connection shown in figure 1 schematic.
The researchers connected the pins 3, 4, 5, 6 to an interactive digital constant so that the states
can be switched to logic 1 or zero depending on the combinations shown in the truth table. SL,
SR, S0, S1 are connected to switches which are then connected to a 5V voltage source. The
terminal 1 is connected to a clock with a frequency of 10Hz. The frequency will control the delay
the output of the segment will change. Pins 15, 14, 13, and 12 is connected to the 7 segment
display. The researchers put digital probe between the connections of this pin to show the
sequence if the circuit shifts to the left or right.
Following the truth table, in figure 1, as clear is set on low and provided that all other
elements are dont care. The output reveals no light. As the clear is set on high and the clock on
low, the rest is dont care, the output follows the same output before it. As the clear, S1 and S0 is
set on high while the rest is dont care, the output becomes an F like figure. Proceeding to the
next combinations on the truth table, one can see the alternation of light and how it affects the
values shown in the 7 segment display. After testing the combinations on the truth table, it was
then compared to the actual output which shows that the actual output and the output from the
truth table is the same.

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

SYNTHESIS
There are many applications that require the use of shift registers. It is one of the
many elements of digital circuits that are vital especially to the electronics or technology
industry. Conducting an experiment on this topic is essential especially when studying in
electronics and later on, in microprocessor.
In this experiment, a software simulation for the circuit was just required to
make a better use of the time. With the given truth table for the shift register, it is implemented
to test all the following conditions that were stated in there. The first to be conducted is the
condition with low outputs. The four (QA, QB, QC, QD) had low outputs when the CLEAR was
set to low and the rest of the input is of X (dont care), this result was shown in the figure 1. For
condition 2 or test 2, to maintain the levels of the output, CLEAR was set to high, and CLK to
low and the rest is of still X (dont care). For the third test, the inputs CLEAR and mode S1 and
S0 being set to high, clock in transition (low to high, with parallel in their steady-state inputs,
and serial to be of X, outputs were regained to be of their steady-state. Fourth condition resulted
output QA to be high with the rest to be of their level before steady-state, inputs were
determined with parallel to be of X, serial right, CLR and mode S0, was set to high also with the
clock in transition and only S1 to be of low condition. Test 5 had the results of the outputs to be
of QA which was low and the rest to be of the same of test 4, the difference of their input is just
that serial right was set to low. In test 6, it was output QD who turned to high with the
remaining on their respective levels, this was because of the inputs in mode and serial to which
they were in contrast of that of test 4 and 5. In test 7, instead of serial left to be high, it was
changed to low with the rest to be the same as of that in test 6, and resulted with an output of
QD to be low in which an opposite to the previous test. For the last condition, which is test 8,
with the same condition of the previous, except for mode s1 to low and the clock to be not in
transition, an output of level before steady-state were acquired. Photos of the results in the
simulation were attached in the previous pages also for better outlooks.
After the test by test implementation, the basic principles for this topic, Universal
Shift Registers were learned and the group was able to come up with a design using the
functions or works of a shift register.

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

CONCLUSION
In the early years of computer, the use of the shift registers is of great impact
especially in data processing. Here now, in present time, shift registers are still in use and can be
seen around, and in every corner. This just means that this type of logic circuit has a demand for
their use whether for a simple application or a complex one. Here in the experiment, the test
must be not that complex because of the given truth table and the specification sheet of the IC
used, but its application as a part of another circuit are seen to be influential as to what they
produced when combined.
For better understanding on shift register, it is insisted to know first the function
of the IC. In this experiment the IC used was the 74F194N. The functions of the pin must be
studied well, but in this condition, the circuit for this shift register was given, so to know what
key to be of logic high or logic low must be taken into consideration to acquire the desired
output. Basing on the results and procedures that were made, the keys or inputs doesnt really
vary differently with another, only the clock, the mode and the serial inputs are the ones that
makes a little difference on the output side, even the parallel ones doesnt really that noticeable
because they are of all in X (dont care) except for a test in there in which it was change to its
steady-state levels and the output resulted also in their steady-state level as well. One important
thing to know in shift registers is that the IC to be used must be of in relation as to what
experiment must be done and its specification sheet must be considered also to understand
more of its function. Also, the truth table must be familiarized for easy access in future use.
Shift registers may sound just as simple especially their different types, but they
are more useful than what it is thought it would be. They do have many applications especially
when used in other circuits or to be a part of another circuit that is usually used in ranging world
of technology as of now.

Central Philippine University

College of Engineering
Department of Electronics and Communications Engineering

Design