Low Power Data-Aware STT-RAM based

Hybrid Cache Architecture

In the proposed design dynamic and adaptive STT-RAM and SRAM partitions are
designed. We develop a controlled cache block which dynamically varies the memory
control during run time itself. This modeling is established to drastically reduce the
power which is wasted through unwanted wait statements executed during the
operation.Dynamic adaptive control block keep on monitors the SRAM Operation to
recycle the energy wasted as well as reduce the data wait time and enables variable
options for memory controls during Run time.
Advantages of Proposed System

Dynamic adaptive control Block

Power Recycling

Reduce the data wait time

Proposed system Algorithm