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15ECL38

DIGITAL ELECTRONICS LABORATORY

Sub Code: 15ECL38

IA Marks: 20

Hrs/ Week: 03

Exam Hours: 03

Total Hrs. 42

Exam Marks: 80

NOTE: Use discrete components to test and verify the logic gates. The IC numbers given
are suggestive, any equivalent ICs can be used.
1. To verify
a) Demorgans Theorem for 2 variables
b) The sum-of product and product-of-sum expressions using universal gates.
2. To design and implement
a) Full Adder using basic logic gates.
b) Full subtractor using basic logic gates.
3. To design and implement 4-bit Parallel Adder/ subtractor using IC 7483.
4. Design and Implementation of 4-bit Magnitude Comparator using IC 7485.
5. To realize
a) 4:1 Multiplexer using gates
b) 3-variable function using IC 74151(8:1 MUX)
6. Realize 1:8 Demux and 3:8 Decoder using IC74138.
7. To realise the following flip-flops using NAND Gates.
a) Clocked SR Flip-Flop
b) JK Flip-Flop
8. To realize the following shift registers using IC7474
a) SISO b) SIPO
c)PISO
d) PIPO
9. To realize the Ring Counter and Johnson Counter using IC7476
10. To realize the Mod-N Counter using IC7490
11. Simulate Full- Adder using simulation tool.
12. Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool.

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EXPT NO: 1

15ECL38

DATE:

SIMPLIFICATION, REALIZATION OF BOOLEAN EXPRESSION USING

LOGIC GATES/UNIVERSAL GATES
Aim: To verify
(a) Demorgans Theorem for 2 variables
(b) The sum-of product and product-of-sum expressions using universal gates.
Components required:Sl.No
1
2
3
4
5
6
7
8
9

NAME OF THE
COMPONENT
AND gate
OR gate
Not gate
EXOR gate
NAND gate
NOR gate
EX-NOR gate
Patch chords
Trainer Kit

IC NUMBER
7408
7432
7404
7486
7400
7402

NOT GATE
TRUTH TABLE

SYMBOL

IC7404

OR GATE
TRUTH TABLE

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SYMBOL

IC7432

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15ECL38

AND GATE
TRUTH TABLE

SYMBOL

IC7408

NAND GATE
TRUTH TABLE

SYMBOL

IC7400

NOR GATE
TRUTH TABLE

SYMBOL

IC7402

XOR GATE
TRUTH TABLE

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SYMBOL

IC7486

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EX-NOR GATE
SYMBOL

TRUTH TABLE

15ECL38

IC7486

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections for the gate as shown in the circuit diagram.
3. Verify the Truth Table.
4. Repeat the above steps for other gates in the different Ic chips.
(a) Demorgans Theorem for 2 variables
Components required:Sl.No
1
2
3
4
5
6
7

NAME OF THE
COMPONENT
AND gate
OR gate
Not gate
NAND gate
NOR gate
Patch chords
Trainer Kit

IC NUMBER
7408
7432
7404
7486
7400
7402

Theory: De Morgans Law allows us to convert NANDs to OR, and NORs to ANDs.
There are two parts to De Morgans Law:
1. A 2-input NAND is equivalent to OR-ing two inverted inputs. In boolean
equation terms:

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15ECL38

2. A 2-input NOR is equal to AND-ing two inverted inputs. Or, in boolean terms:

Procedure:
1. Place the IC in the socket of the trainer kit.
2. Make the connections as shown in the circuit diagram.
3. Apply diff combinations of i/ps according to the truth table. Verify the o/p.
4 Repeat the above procedure for all the circuit diagrams.

Result: the Demorgans theorem is realized using logic gates and the truth table has been
verified

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15ECL38

(b) The sum-of product and product-of-sum expressions using universal gates.
Components required:Sl.No
1
2
3
4
5
6
7
8

NAME OF THE
COMPONENT
AND gate
OR gate
Not gate
EXOR gate
NAND gate
NOR gate
Patch chords
Trainer Kit

IC NUMBER
7408
7432
7404
7486
7400
7402

THEORY: To minimize a Boolean expression we can employ any one of the following
techniques:
i)
Boolean Algebra
ii)
Karnaugh maps.
Before we proceed to simplification techniques, two forms of the Boolean
expression must be noted
1) Sum of product (SOP):
Ex: ABC+AB+AC
2) Product of Sum (POS) :
Ex: (A+B+C)(A+B)+(A+C)
SUM OF PRODUCT (SOP):
F(A,B,C,D) = (5,7,9,11,13,15)
Simplification- SOP form

using basic gates

Using NAND gates

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using NOR gates

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15ECL38

PRODUCT OF SUM : F(A,B,C,D) = (0,1,2,3,4,6,8,10,12,14)

Simplification- SOP form

Using basic gates

Using NAND gates

Using NOR gates

Truth Table:

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0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Y=(A+B)
D
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0

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15ECL38

Procedure:
1. Place the Ic in the socket of the trainer kit.
*complex Boolean Expressions are simplified by using K maps.
2. Make the connections as shown in the circuit diagram.
3. Apply diff combinations of i/ps according to the truth table. Verify the o/p.
4 Repeat the above procedure for all the circuit diagrams.
*NOTE: The Truth Table is common for Both SOP and POS form.
Result: Given Boolean expression is simplified and realized using logic gates and the
truth table has been verified
Conclusion: Simplifying and then realizing a given logic expression uses less number of
gates and thus helps in implementing more logic within the given area.
Viva Questions:.
1. Boolean laws, Identities, Properties, Huntingtons postulates.
2. Realization of basic gates using universal gates and vice versa. Conversion of 2 input
NAND into 3 inputs NAND and 4 input NAND gate. Decoding of the IC number,
Significance of Schottky Series.
3. Noise Margin, Fan out, Fan in, Propagation delay, Speed Power product. Comparison
of different Logic families, fastest logic family, TTL Logic family.
4. Application of X-OR gate, realizing X-OR using minimum number of NAND gates.
Coincidence gate?
5. Different methods of Simplification, which method is preferred when?
6. State DeMorgans Theorem and prove them.
****

Observation:

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EXPT NO: 2

15ECL38

DATE:
FULL ADDER & FULL SUBTRACTOR

Aim: To design and implement

(a) Full Adder using basic logic gates.
(b) Full subtractor using basic logic gates.
Components required:Sl.No

NAME OF THE
COMPONENT
AND gate
OR gate
Not gate
EXOR gate
Patch chords
Trainer Kit

IC NUMBER

THEORY: The basic rules of

binary addition are
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = (10)2
Column by column addition,
similar to decimal addition is performed a logic circuit known as half adder adds two 1 bit
signals. In octal addition there is often a thiral bit, the carry bit that must be added. Hence
to add 3 bits at a time a logic circuit known as a Full adder is used.
1
2
3
4
5
6

7408
7432
7404
7486

FULL ADDER:

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15ECL38

Fig. Full Adder using Basic Gates

Truth table (Full adder)

Procedure:
1.
Make connections as shown in the circuit diagram.
2.
Connect Vcc and GND to respective pins of IC
3.
Switch on the trainer kit
4.
Apply inputs using toggle switches and verify the truth table using LEDs.
FULL SUBTRACTOR:
Truth Table

Logic Diagram
Fig. Full Subtractor
Procedure:

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Bin

Diff

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1
10

Borro
w
0
1
1
1
0
0
0
1

using basic gates

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1.
2.
3.
4.

15ECL38

Make connections as shown in the circuit diagram.

Connect Vcc and GND to respective pins of IC
Switch on the trainer kit
Apply inputs using toggle switches and verify the truth table using LEDs.

Result: Full adder, Full Subtractor circuits are realized using logic gates and the truth
tables are verified.
Conclusion: Adder and Subtract or circuits are the most essential part of ALU. Working
of these circuits at gate level is understood in this experiment.
Viva Questions:.
1. Applications of Adder and Subtract or circuits.
2. Definition of Half adder, Full Adder, Half Subtract or, Full Subtract or. Realizations of
the same. Derivation of truth table in each case. Obtaining the logic expression.
3. Realizing FA using 2 Half adders, FS using 2 Half Subtractor.
4. Application of X-OR gate, realizing X-OR using minimum number of NAND gates.
Coincidence gate?
****

Observation:

EXPT NO: 3
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DATE:
11

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15ECL38

PARALLEL ADDER/SUBTRACTOR USING IC 7483

Aim: To design and implement 4-bit Parallel Adder/ subtractor using IC 7483.
Components required:Sl.No
1
2
3
4

NAME OF THE
COMPONENT
EXOR gate
Patch chords
Trainer Kit
4 bit parallel
adder/subtractor

IC NUMBER
7486

7483/

Theory:
The IC 7483 is a 4- bit parallel adder IC that contains four inter connected FAs
high speed operation. the inputs to this IC are two 4-bit numbers A3,A2,A1,A0 &
B3,B2,B1,B0 and the carry Cin in to the LSB position. The outputs are the sum bits 3,
2,1,0. and the Cout of the b position.
Pin diagram:

1) Realization Of Parallel Adder/Subtract or Using 7483chip

Logic Diagram

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15ECL38

Fig. Block Diagram of Parallel Adder

Procedure:
1. Make the connections as shown.
2.For addition ,make Cin=0 and apply the 4 bits as i/p for A and apply another set of A
bits to B. Observe the o/p at S3, S2 S1 S0 and carry generated at Cout.
3. Repeat the above steps for different inputs and tabulate the result.
4. For subtraction Cin is made equal to 1 and A-B format is used.
A First no
B Second no.
By Xor ing the i/p bits of B by 1 , is complement of B is obtained. Further Cin,
which is 1 is added to the LSB of the Xor ed bits. This generates 2s complement of
B.
5. Verify the difference and polarity of differences at S 0, S1, S2, S3.and Cout. If Cout is 0 ,
diff is ve and diff is 2s complement form. If Cout is 1, diff is +ve .
6. Repeat the above steps for different inputs. And tabulate the result.
Readings:Cin
0
0
1
1

A3
1
0
1
0

A2
0
1
0
0

A1
0
1
0
0

A0
1
1
1
1

B3
1
0
1
0

B2
0
0
0
0

B1
0
0
0
1

B0
1
1
0
1

Cout
1
0
1
0

S3
0
1
0
1

S2
0
0
0
1

S1
1
0
0
1

S0
0
0
1
0

Observation and calculation:

4 bit Binary Adder:
1. Make Cin = 0. The circuit works as an Adder.
2. Set A3A2A1A0 = Binary equivalent of the Addend using toggle switches.
B3B2B1B0 = Binary equivalent of the Addend using toggle switches.
3. Verify the Result on CoutS3S2S1S0 using LEDs.

Ex.1
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Ex.2
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15ECL38

A=4, B=8
S=A + B

A=13, B=9
S=A + B

Augend Addend

Augend Addend

A3A2A1A0 = 0 1 0 0
B3B2B1B0 = 1 0 0 0
CoutS3S2S1S0 = 0 1 1 0 0 = (12)10

A3A2A1A0 = 1 1 0 1
B3B2B1B0 = 1 0 0 1
CoutS3S2S1S0 = 1 0 1 1 0 = (22)10

4 bit Binary Subtract or:

1. Make Cin = 1. The circuit works as a Subtract or.
2. Set A3A2A1A0 = Binary equivalent of the Minuend using toggle switches.
B3B2B1B0 = Binary equivalent of the Subtrahend using toggle switches.
3. Verify the Difference on S3S2S1S0 and Carry generated on Cout using LEDs.

Ex.1

Ex.2

A=4, B=8
D = A - B = A + (2s Complement of B)
Complement of B)
Minuend

Subtrahend

A=15, B=9
D = A - B = A + (2s
Minuend

A3A2A1A0 = 0 1 0 0
B3B2B1B0 = 1 0 0 0
2Complement of B = 1 complement of B + 1
of B + 1
=0111
+1
2Complement of B = 1 0 0 0
D = A - B = A + (2s Complement of B)
Complement of B)
= 0100
+(1 0 0 0)
CoutS3S2S1S0 = 0 1 1 0 0

A3A2A1A0 = 1 1 11
B3B2B1B0 = 1 0 0 1
2Complement of B = 1 complement
=0110
+1
2Complement of B = 0 1 1 1
D = A - B = A + (2s
= 1111
+(0 1 1 1)
CoutS3S2S1S0

Cout = 0 implies that answer is negative

positive, ignore carry
& in 2s complement form.
Answer = (- 0 1 0 0) =(-4) 10

Subtrahend

=10110

Cout = 1 implies that answer is

& in direct form.
Answer = (+ 0 1 1 0) = (+6) 10

Note: Examiner may specify the numbers.

Viva Questions:
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1. What are the different methods of representing ve numbers, which type is preferred
and why?
2. Procedure for 1s complement method of subtraction
3. Procedure for 2s complement method of subtraction
4. State different methods of subtraction using complementary methods
5. Why complementary methods are preferred?
6. What are the advantages of 2s complement method?
7. Internal diagram of IC 7483, what is the significance of Cin and Cout pins.
8. Types of Adders, advantages and disadvantages of different types, Explain Look ahead
carry adder.
*****

Observation:

EXPT NO: 4
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DATE:
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15ECL38

4-BIT MAGNITUDE COMPARATOR

Aim: Design and Implementation of 4-bit Magnitude Comparator using IC 7485.
Components required:Sl.N
o
1
2
3

NAME OF THE
COMPONENT
Magnitude comparator
Patch chords
Trainer Kit

IC NUMBER
7485

THEORY:
A Magnatitude comparator is a combinational circuit that compares two numbers,
A and B , and determines their relative magnitudes. The outcome of the comparison is
specified by three binary variables that indicates whether A > B, A =B, A<B
IC 7485 Pin Details:

IC 7485: The IC 7485 is a 4-bit magnitude comparator that can be expanded to almost
any length. It compares two 4 bit binary and produces three magnitude results

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Logic Diagram:

Procedure:
1) Rig up the circuit for one bit & two bit comparator as shown in the figure using IC
7485 magnitude comparator and basic gates.
2) Verify the Table of values .the output obtained should match the required result.
Result: 4-bit magnitude comparator operation is verified using 7485
Viva Questions:
1. Design 1-bit magnitude comparator
2. State applications of magnitude comparator
3. What is the significance of cascading inputs in 7485?
4. What is the principle used in comparing multi bit number.
*****

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15ECL38

Observation:

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EXPT NO: 5

15ECL38

DATE:
MULTIPLEXERS

Aim: Realize
a) 4:1 Multiplexer using gates.
b) 3-variable function using IC 74151(8:1MUX).
Components required:Sl.N
NAME OF THE COMPONENT
o
1
NAND gate(2 pin)
2
NAND gate(4 pin)
3
MUX
4
Not gate
5
Patch chords
6
Trainer Kit

IC NUMBER
7400
74151
7404

Ics required: Ic 7400, 7410,7420,74151 and 74139.

Theory: A digital Multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Multiplexer means many to
one. A multiplexer is a circuit with many inputs but only one output. By using control
signals (select lines) we can select any input to the output. Multiplexer is also called as
data selector because the output bit depends on the input data bit that is selected. The
general multiplexer circuit has 2n input signals, n control/select signals and 1 output
signal.
De-multiplexers perform the opposite function of multiplexers. They transfer a small
number of information units (usually one unit) over a larger number of channels under the
control of selection signals. The general de-multiplexer circuit has 1 input signal, n
control/select signals and 2n output signals. De-multiplexer circuit can also be realized
using a decoder circuit with enable.
a) 4:1 Multiplexer using gates.
Procedure:
1. Set up the circuit as shown in figure
2. Apply any arbitrary 4 bit word. record this word, NAND verify the o/p sequence for
each combination of the select line and verify that it functions as a 4:1 MUX.
S1 S0 I0
0 0 I0
0 1 X

I1
X
I1

I2
X
X

I3
X
X

Y
I0
I1

1
1

X
X

I2
X

X
I3

I2
I3

0
1

X
X

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Truth table (4:1 MUX)

Symbol

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Logic Diagram of 4:1 MUX:

b) 3-variable function using IC 74151(8:1MUX).

Pin Details Of 74151

Truth table of 8:1 MUX

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Result: The Operation of Multiplexer has been realized.

Conclusion: It is observed that any given function can be realized very easily realized
using Mux
Viva Questions:
1. Define Multiplexer
2. Design a 2X1Mux.
3. Realize a 4X1 Mux using 2X1 Mux
4. What is the significance of enable inputs?
5. What is the relation between select and I/P lines
6. State practical applications of Mux
7. What is the inference from realizing arithmetic circuits using Mux.
Observation:

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15ECL38

EXPT NO: 6

DATE:
DEMULTIPLEXERS & DECODERS

Aim: Realize 1:8 Demux and 3:8 Decoder using IC74138/39.

Components required:Sl.N
NAME OF THE COMPONENT
o
1
NAND gate(2 pin)
2
NAND gate(4 pin)
3
DEMUX
4
Not gate
5
Patch chords
6
Trainer Kit

IC NUMBER
7400
74139
7404

Ics required: Ic 74139.

Demultiplexer Theory:
The data distributor, known more commonly as a Demultiplexer or Demux for short, is
the exact opposite of the Multiplexer . The demultiplexer takes one single input data line
and then switches it to any one of a number of individual output lines one at a time. The
demultiplexer converts a serial data signal at the input to a parallel data at its output
lines.
IC 74139: The ic 74139 is a high speed dual 1 of 4 decoder/ demultiplexer. This device
has two independent decoders each accepting two binary weighted inputs (a, b) and
providing four mutually exclusive active low o/ps(Y0-Y3).each decoder has an active low
enable (E) when E=1 every o/p is forced high. The enable can be used as the data input
for a 1 of 4 DEMUX applications

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15ECL38

IC 74139 DEMUX/ DECODER

Functional Table

Decoder Theory:
In digital electronics, a decoder can take the form of a multiple-input, multipleoutput logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different e.g. n-to-2n , binary-coded decimal decoders. Decoding is
necessary in applications such as data multiplexing, 7 segment display and memory
address decoding. A slightly more complex decoder would be the n-to-2n type binary
decoders. These types of decoders are combinational circuits that convert binary
information from 'n' coded inputs to a maximum of 2n unique outputs. In case the 'n' bit
coded information has unused bit combinations, the decoder may have less than 2n
outputs. 2-to-4 decoder, 3-to-8 decoder or 4-to-16 decoder are other examples.
IC and Functional Table:

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Procedure:
1) Rig up the circuit using NAND gates and then with IC74139/38 as shown in figure.
2) Verify the output with the truth table Value
3) The output obtained practically should match the required result.
Result: Operation of Demux and their applications in Arithmetic circuits and Code
converters has been realized.
Conclusion: It is observed that any given function can be realized very easily realized
using Mux and Demux.
Viva Questions:
1. Define Dmux
2. What are the different methods of indicating active low signals?
3. What is the difference between Demux and Decoder?
*****

Observation:

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EXPT NO: 7

15ECL38

DATE:
VERIFICATION OF SR & JK FLIP-FLOPS

AIM: - To realise the following flip-flops using NAND Gates.

(a) Clocked SR Flip-Flop (b) JK Flip-Flop
Components required:Sl.No
1
2
3
4
5

NAME OF THE
COMPONENT
Dual J.K FlipFlop
NAND gate
NOT gate
Patch chords
Trainer Kit

IC NUMBER
7476
7400
7404

THEORY:
The flip-flops can be mode to respond to trailing edge of a pulse by employing two flipflop circuits, one to hold the output state on the trailing edge and the other to sample the
i/p information on the leading edge. Such a combination is called a master- slave flipflop. The MS combination can be constructed for any type of FF. In case of JK MS FF the
information present at the J and K inputs is transmitted to the master FF on the leading
edge of the clk pulse and held there until the trailing edge of clock pulse occurs offer
which if is allowed to pass through to the slave FF.
Circuit of SR FF

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Symbol of SR FF

Truth table :

Symbol of MS-JK FF

Circuit diagram:

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Fig. Circuit diagram of master slave flip-flop

Truth Table:
Inputs
Clk Cr pr
1
1 1

Output
Q
Qn+1

Operation Performed

Normal FF(Table-2)
(F.F. enabled)
F.F. Cleared(Reset)

F.F. Preset(Set)

Table 2
Inputs
Clk
J
K
X

Output
Qn+1

COMMENTS

Qn

No Change

Qn

No change

Reset

Qn

Set

X
0
0
0
1
1

F.F. Preset(Set)

0
1
1
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Note: - Keep Pr= Cr=1 for verifying the truth tables JK MS F.F, T and D type FF.
Procedure:
1) Rig up the circuit as shown in the diagram.
2) Apply the i/ps to these flip-flops as per the Truth table and observe the o/p verify
with the truth table.
Result: Thus the truth table for Master Slave JK FF was verified and T FF were realized
using MS JK FF.
1. Distinguish between the combinational & sequential circuits.
2. What are the two types of sequential circuits?
3. What is a Flip-Flop & Distinguish between the flip-flop & Latch?
4.A Flip-flops is a Divide By _____ Counter.
5. Can we use SR Flip-flops as a D Flip-flops?
6. What is a Race condition?
7. What is a Race around condition?
*****

Observation:

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EXPT NO: 8

DATE:
SHIFT REGISTERS

Aim: To realize the following shift registers using IC7474

(a) SISO (b) SIPO (c)PISO (d) PIPO
Components required:Sl.No
1
2

NAME OF THE
COMPONENT
Shift register
Trainer kit
Patch Chords

IC NUMBER
7474

Theory: A Shift register is a storage device that can be used for temporary storage of
binary data he basic building block in all shift registers is the flip-flop, mainly a D-type
flip-flop. Based on the method by which data can be loaded onto and read from shift
registers, they are classified. The IC 7474 is a 4-bit shift registers, allowing
Serial in serial out (SISO)
Serial in parallel out (SIPO)
Parallel in serial out (PISO)

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Parallel in parallel out (PIPO) above all four are shift right operation and also to do Shift
left operation.
Pin Diagram of IC 7474:

Serial In Serial Out (SISO)-Shift Right:

Truth table for SISO

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Procedure:

Serial in Parallel out (SIPO):

Truth table for SIPO

Procedure:
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Parallel in serial out (PISO):

Truth table for PISO

Procedure:

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Parallel in Parallel out (PIPO):

Truth table for PIPO

Procedure:

Conclusion: All the outputs are verified with the truth table.
Viva Questions:

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a)
b)
c)
d)

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What is a difference between Counters & Shift registers?

What is a Universal Shift register?
How many Flip-flops are there in the IC-7495?
What is a Bidirectional Shift registers?
*****

Observation:

EXPT NO: 09

DATE:
RING COUNTER & JOHONSON COUNTER

Aim: To realize the Ring Counter and Johnson Counter using IC7476
Pin Diagram of IC 7476:

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Theory: Ring counter is also called as shift register counter where the FF1S are coupled
as in a shift register and the last FF is coupled back to the first ,which gives the array of ff

the shape of ring . Counting sequence of such counter will depend upon initial state, the
desired initial state should provided by parallel loading before counting begin, loading
can be done by placing a single 1 or single 0 for allowed counting sequence. The logic
1 or 0 will advance by one flip-flop around the ring for each clk pulse and return to
original FF after exactly four clk pulses as there are 4FF ,the standard ring counter
requires n FFs to derive a modulo (n+1) counter.
a) Realization of Ring Counter using IC7476:
Components Required:Sl.No
1
2

NAME OF THE
COMPONENT
Ring Counter
Patch chords
Trainer Kit
CRO & CRO probe

IC NUMBER
7476

Circuit diagram for ring counter:

Truth Table:

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Outputs

Clock

Time

CLK

T0
T1
T2

QA
1
0
0

T3

QB
0
1
0
350

QC
0
0
1

QD
0
0
0

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Waveform:

Result: Thus the function of ring counter is verified.

b) Realization of Johnson Counter using IC7476
Components Required:Sl.No
1
2
3
4
5

NAME OF THE COMPONENT

Ring Counter
Patch chords
Trainer Kit
CRO&CRO probe
Not gate

IC NUMBER
7476

7404

Theory: The modulus value of a ring counter can be doubled by making a small change
in the ring counter circuit. The Q and Q of the last FFS are connected to the J and K input
of the first FF respectively. Initially the FFs are reset. After first clock pulse FF0 is set and
the remaining FFs are reset. After the eight clock pulse all the FFS are reset. There are
eight different conditions creating a mode 8 Johnson counter. Johnson counter is called a
twisted ring counter or divide by 2N counter

Circuit diagram for Johnson ring counter

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Truth Table:

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c lk

Qa

Qb

Qc

Qd

Waveform:

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PROCEDURE:
1. Set up the ring counter and set clear Q outputs using PRESET and apply mono pulse.
2. Note down the state of the ring counter on the truth table for successive clock 0.
3. Repeat the steps for Johnsons counter
Result: Four bit ring counter and the Johnson counter were set up using the JK FF and
verified
Viva Questions:
1. Ring Counter is generally called MOD -------- Counter?
2. How many Flip-flops are present in the 7495 IC?
3. How the Shift Register Counters are different from that of normal binary counters?
4. What is the other name for the Johnson Counter? It is generally called MOD ------Counter?
*****

Observation:

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EXPT NO: 10

15ECL38

DATE:
MOD N COUNTERS USING IC7490

Aim: To realize the Mod-N Counter using IC7490

Components required:IC 7490, Trainer Kit, patch cards
Theory: A sequential circuit that gives through a prescribed sequence of states upon the
application of input pluses is called counters. The straight binary sequence counter is the
simple and most straight forward. An n-bit binary counter has n flip-flops and can count
in binary from 0 to 2n -1.
Asynchronous counter:
A binary ripple (Asynchronous) counter consists of series connections of
T- flip-flops without any logic gates. Each FF is triggered by the output of its
preceding FF goes from 1 to 0.
Synchronous Counter:
In Synchronous counters all FF are triggered simultaneously by the count
pluse. The FF is complemented only if its T input is equal to 1 the advantage of
synchronous counter is its speed, it takes only one propagation delay time for the
correct binary count to appear the clock edge bits.
IC 7490 is a Divide-by 10 counter using 4 Master slave JK flip-flops. It contains a
Divide-by 2 and Divide-by 5 counters, which can be cascaded to give a Divide-by 10
counter.
Procedure for BCD counters using IC 7490:
1. MS1, MS2, MR1and MR2 inputs are connected to GND (Active HIGH I/Os).
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2. Clock input is given to Clock A

3. Output Q0 and Clock B are shorted so that it acts as Divide-by 10 counter with BCD
count sequence.
4. Verify the truth table and observe the waveforms on CRO.
Pin Diagram

Internal Diagram

Conditional Table:
R1
H
H
X

R2
H
H
L

S1
L
X
H

S2
X
L
H

L
X

X
L

L
X

X
L

Qa
L
L
1

Qb
L
L
0

Qc
Qd
L
L
L
L
1

0
MOD-2 COUNTER
MOD-5 COUNTER

7490 As Mod-5 Counter:

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7490 As Mod-10 Counter:

7490 As Mod-8 Counter:

7490 As Mod-6 Counter:

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Result: Thus the truth tables of the modulo counters using different IC is verified.
Viva Questions:
1. Define MOD of a counter?
2. What is a difference between a Synchronous & Asynchronous Counters?
3. Name the ICs which are used as a Synchronous Counters?
4. Define Triggering in the Counters?

Observation:

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MULTISIM
Creating a Digital Component Using Multisim
To create a digital component:
1. Click the Create Component button in the Main toolbar.
Or
Choose Tools/Component Wizard. Step 1 of the Component Wizard appears.
2. Complete the following as desired:
Component Name the value of the component, for example, 74ALS00M.
Author Name completed by system; change if desired.
Function a brief description of the component.
3. Select digital from the Component Type drop-down list. The Component Technology
drop-down list appears select the desired technology, for example, 74ALS.
4. Select one of:
I will use this component for both simulation and layout (model and footprint)
to use the component for both simulation and PCB layout.
Simulation only (model) to use the component for simulation only.
Layout only (footprint) to use the component for PCB layout only.
Note The number of steps you must complete depends on the selections you make in step
1. If you choose to use the component for both simulation and layout, the wizard includes
eight steps. If you choose to use the component for simulation only, the wizard

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includes seven steps; for layout only it includes six steps.

5. Click Next. The next step of the wizard appears, where you enter the components
footprint information.
6. Click Select a Footprint. The Select a Footprint dialog box appears, where you select
a footprint from one of the databases.
Select the desired Database Name, scroll down the list at the bottom of the dialog box
and click the desired Footprint, for example, M14A.
7.Click Select. You are returned to the Component Wizard. The Footprint
Manufacturer and Footprint Type fields have been populated based on the selected
footprint.
8. Select Single Section Component or Multi-Section Component as desired. If you
select Multi-Section Component, the Number of Sections and Section Details elements
are added to the dialog. Complete these as desired.
9. Click Next to display the next step of the wizard. This is where you enter symbol
information for the component. The symbol you assign to this component appears when it
is placed on the workspace.
In the Symbol Set area, select ANSI or DIN.
Optionally, to modify the symbol, click Edit to launch the Symbol Editor.
Hidden Ground Pins Depending on the Component Technology selected in step 1,
this section will have different options available (for example, GND). Select the desired
radio button.
Hidden Power Pins Depending on the Component Technology selected in step 1,
this section will have different options available (for example, VCC). Select the desired
checkboxes.
10. Click Next to display the next step of the Component Wizard. Enter the
components pin parameters as described below:
Add Hidden Pin button click to add hidden pins: Power; Ground; Common.
Section column click in a field in this column and select the desired section for this
pin. This is for multi-section components.
Type column click a field in this column and select the pin type from the drop-down
list that appears. Choices are: passive, ground, bidirectional, input, no connection,
output and power.
ERC Status column click in a field in this column and select whether to include or
exclude the pin from Electrical Rules Checking.
11. To accept the symbol information displayed, click Next. This is where you map
symbol and footprint pin information. This mapping is needed for exporting to a layout
package. A symbol pin is the name of the pin in the symbol, for example, VCC. The

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footprint pin is the number or name of that pin on the footprint in PCB layout. The
symbol and footprint pins must accurately map in order to transfer correctly to PCB
layout
For each symbol pin, enter a corresponding footprint pin. The mapping information
you enter here will be displayed in the Footprint tab of the Component Properties
dialog box.
For advanced pin mapping options, click Map Pins. The Advanced Pin Mapping
dialog box displays.
12. Click Next to display the Select Simulation Model step. (If the component does not
require simulation, this step does not appear). The buttons in this step work as described
below.
Select from DB displays the Select Model Data dialog box, where you copy model
data from an existing component.
Load from File displays a standard file browser where you navigate to, and select,
the desired model file.
Copy to displays the Select Target dialog box. Use to copy model information from
a selected section of a multi-section component to the target sections that you select in
the Select Target dialog box.
This would typically be used after using the Select from DB button to copy model data
from another component. This model data will have only been copied to the selected
section of the component. By using Copy to, you can copy the information into the
remaining sections of the component.
13. Click Next to display the next step, where you set mapping information between the
symbol and the simulation model.
For each symbol pin enter a corresponding number to connect to its respective nodes
in the model. The mapping information you enter here will be displayed in the Model
tab of the Component Properties dialog box.
14. Click Next. The dialog box that appears lets you indicate where you would like the
component to be saved. If there is no family in the group that you want to save the
component, you can add a new family by clicking on the Add Family button.
15. Navigate to the family where you want to save the component and click Finish. The
component is saved in the selected family.

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EXPT NO: 11

15ECL38

DATE:
FULL ADDER USING MULTISIM

Aim: Simulate Full- Adder using simulation tool.

Components required:Computer with Multisim tool in it.
THEORY: The basic rules of binary addition are
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = (10)2
Column by column addition, similar to decimal addition is performed a logic circuit
known as half adder adds two 1 bit signals. In octal addition there is often a thiral bit, the
carry bit that must be added. Hence to add 3 bits at a time a logic circuit known as a Full
adder is used.
FULL ADDER:

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Fig. Full Adder using Basic Gates

Truth table (Full adder)

Procedure:
Result: Full adder circuits are realized using logic gates with Multisim and the truth
tables are verified.
****

Observation:

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EXPT NO: 12

15ECL38

DATE:
SYNCHRONOUS MOD-8 UP/DOWN COUNTER

Aim: Simulate Mod-8 Synchronous UP/DOWN Counter using simulation tool.

Components required:Computer with Multisim tool in it.
THEORY: IC 74193 is a Divide-by16 synchronous counter using 4 Master slave JK flipflops. It contains a Divide-by 2 and Divide-by 8 counters which can be cascaded to give a
Divide-by 16 counter.
Procedure for Binary counter using 74193:
1. MR1 and MR2 are connected to ground (Active High)
2. Clock input is given to Clock A
3. Output Q0 and Clock B are shorted so that it acts as Divide-by 16 counter.
4. Verify the truth table and observe the waveforms on CRO.
Pin Details of IC 74193(Synchronous Counter)
[Mod-16 Up/Down Counter]
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Function Table:

H
L
L
L
L

Load

Up

Down

Qd

X
L
H
H
H

X
X
Cp
H
H

X
X
H
Cp
H

0
D

Qc

Qb

0
0
C
B
Count up
Count down
No change

Qa
0
A

Logic Diagram:

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Result: Full adder circuits are realized using logic gates with Multisim and the truth
tables are verified.
****

Observation:

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