Bistable Multivibrator Design PDF

Pulse and Digital Circuits
Venkata Rao K., Rama Sudha K. and Manmadha Rao G.
Chapter 9
Bistable Multivibrators
1. Design a fixed-bias bistable multivibrator using Ge transistors having h FE(min) = 50,
V CC = 10 V and V BB = 10 V, V CE(sat) = 0.1 V, V BE(sat) = 0.3 V, I C(sat) = 5 mA and
assume I B(sat) = 1.5I B(min) .
Solution:
RC
VCC VCE (sat)

IC 2
10 0.1 V 9.9 V
5 mA
5 mA
1.98 k
V (VBB )
R2
I2
Choose I 2
1
IC 2
10
0.5 mA
0.3 10 10.3 V
=20.6 k
0.5
0.5 mA
I
5 mA
C2
=0.1 mA
hFE min
50
R2
I B 2 min
If Q 2 is in saturation
I B 2 1.5 I B 2 min
= 0.15 mA
I1 I 2 I B 2
= 0.5 mA+0.15 mA 0.65 mA
V V
10 0.3
9.7 V
RC R1 CC
14.92 k
I1
0.65 mA 0.65 mA
R1 ( RC R1 ) RC
14.92 1.98 12.94 k .
2. For a fixed-bias bistable multivibrator shown in Fig. 9p.2 using npn Ge transistor
V CC = 10 V, R C = 1 k, R 1 = 10 k, R 2 = 20 k, h FE(min) = 40, V BB = 10 V. Calculate:
(a) Stable-state currents and voltages assuming Q 1 is OFF and Q 2 is ON and in
saturation. Verify whether Q 1 is OFF and Q 2 is ON or not. (b) the maximum load
current.
Dorling Kindersley India Pvt. Ltd 2010
Fig. 9p.2 The fixed-bias bistable multivibrator

Solution:
Assume V CE(sat) = 0.1 V, V BE(sat) = 0.3 V
Calculate V B1 to verify whether Q 1 is OFF or not.

R2
R1
0.1 20 (10)10
VB1 VCE (sat)
(VBB )
R1 R2
R1 R2 10 20 10 20
0.066 3.333 3.267 V
Hence Q 1 is OFF
VC1 VCC 10 V
To verify whether Q 2 is in saturation or not:
Calculate I B2 , I C2
To calculate I B2 .
Consider the cross-coupling circuit shown in Fig.2.1.
Fig. 2.1 Circuit to calculate the base current of Q 2
I1
VCC V 10 0.3 9.7 V
=0.88 mA
RC R1
1 10
11 k
I2
V VBB 0.3 10 10.3
0.515 mA
R2
20
20
I B 2 0.88 0.51
0.37 mA
To calculate I C2
Consider the cross-coupling network shown in Fig. 2.2.
Fig. 2.2 Circuit to calculate the collector current of Q 2
I3
VCC VCE (sat)

RC
10 0.1
9.9 mA
1K
VCE (sat) VBB
I4
R1 R2
10.1
=0.336 mA
30 K
IC 2 I3 I 4
9.9 0.34 9.56 mA
I B 2min
IC 2
hFE min
9.56 mA
=0.24 mA
40
I B 2 I B 2min
Hence Q 2 is verified to be in saturation.
VC 2 0.1 V, VB 2 0.3 V .
V C1 = V CC I 1 R C
= 10 (0.88)1
= 9.12 V
Hence the stable-state currents and voltages are as follows:
V C1 = 9.12 V, V B1 = 3.267 V
V C2 = 0.1 V I B2 = 0.37 mA, I C2 = 9.56 mA
To find the maximum load current or minimum load resistance, consider Fig.2.3.
Fig. 2.3 Circuit to calculate maximum load current

I L is maximum (I L(max) ) when I B2 is I B2(min)
I B2(min) = 0.2 mA
I 2 = 0.51 mA
I 1(min) = I 2 +I B2(min)
=0.51+0.24
=0.75 mA
V C1(min) = I 1(min) R 1 +V
0.75 10 0.3
7.8 V
VCC VC1(min) 12 7.8
4.2 mA
I
1
RC
I Lmax =I I 1(min) = 4.2 mA 0.75 mA
=3.45 mA
7.8 V
RL (min) =
2.26 k.
3.45 mA
3. Design a self-bias bistable multivibrator shown in Fig.9p.2 with a supply voltage of

12 V. A p-n-p silicon transistors with h FE(min) = 50, V CE(sat) = 0.3 V, V BE(sat) = 0.7 V
and I C2 = 4 mA are used.
Fig. 9p.2 Self-bias bistable multivibrator

Solution:
1
1
Assume V EN = VCC 12 4 V
3
3
I C2 = 4 mA
I B2(min) =
4 mA
0.08 mA
50
Choose I B2 = 1.5I B2(min) = 0.12 mA

(I C2 +I B2 ) = 4 0.12 = 6.12 mA
RE
VEN 2
4 V
0.97 k
I C 2 I B 2 4.12 mA
VCC VCE (sat) VEN 2

IC
12 0.3 4 7.7 V
1.925 k
4 mA
4 mA
1
1
Let I 2 I C 2 4 mA 0.4 mA
10
10
VBN 2 VEN 2 V 4 0.7 4.7 V
RC
VBN 2
4.7 V
11.75 k
0.4 mA
I2
Choose R 2 = 12 k
Find I 2 for this R 2
V
4.7 V
I 2 BN 2
0.392 mA
12.0 K
R2
R2
VCC VBN 2
I2 I B2
12 4.7
7.3 V
14.26 k
0.392 0.12 0.512 mA
RC R1
( RC R1 ) = 14.26 k
R 1 = ( RC R1 ) RC 14.26 1.925 12.33 k
Choose R 1 =12 k
Note: Choose the nearest standard values.
4. A self-bias bistable multivibrator uses Si transistors having h FE(min) = 50. V CC = 18 V,
R 1 = R 2 , I C(sat) = 5 mA. Fix the component values R E , R C , R 1 and R 2.
Solution:
1
1
Assume V EN = VCC 18 6 V
3
3
and I C(sat) = 5 mA
5 mA
0.1 mA
50
Choose I B2 = 1.5I B2(min) =0.15 mA
I B2(min) =
(I C2 +I B2 ) = 5 + 0.15 = 5.15 mA
VEN 2
6V
RE
1.16 k
I C 2 I B 2 5.15 mA
VCC VCE (sat) VEN 2
RC
IC
18 0.3 6 11.7 V
2.34 k
5 mA
5 mA
VBN 2 VEN 2 V 6 0.7 6.7 V
V VBN 2
RC R1 CC
I 2 I B2
V VBN 2
R (V VBN 2 )
RC R1 CC
1 CC
VBN 2
VBN 2 R1 I B 2
I B2
R2
R (18 6.7)
11.3R1
2.34 R1 1
6.7 0.15 R1 6.7 0.15 R1

0.15 R12 4.25 R1 15.67 0
(4.25) 2 4 0.15 15.67
R1 4.25
2 0.15
R1 R2 14 k .
5. For a Schmitt trigger in Fig. 9p.4 using npn silicon transistors having h FE(min) = 40,
the following are the circuit parameters: V CC = 15 V, R S = 0, R C1 = 4 k, R C2 = 1 k,
R 1 = 3 k, R 2 = 10 k and R E = 6 k. Calculate V 1 and V 2 .
Fig. 9p.4 The Schmitt trigger circuit

Solution:
From the given data, if Q 2 is in the active region, typically, V BE2 = 0.6 V and let h FE = 40.
To calculate V 1 :
R E (1+h FE ) = 6(1+40) =246 k
R ' R2 / /( RC1 R1 ) 10 k / /(4 k +3 k) 4.11 k
R2
10
V ' VCC
15
8.82 V
( RC1 R1 R2 )
4 3 10
R (1 hFE )
V EN 2 (V ' V BE 2 ) ' E
R R E (1 hFE )
246
8.08 V
4.11 246
V 1 8.08 0.5 8.58 V
VEN 2 (8.82 0.6)

V1 VEN 2
To calculate V 2 :
R2
10
0.769
R1 R2 3 10
Rt
R C 1 ( R1 R 2 )
R C 1 R1 R 2
Rt
4 (3 1 0 )
3 .0 5 k
4 3 10
Rt 0.769 3.05 2.35 k

RE" (1
1
41 6
) RE
6.15 k
hFE
40
Vt V ' VCC
I C1
(V ' V 2 )
Rt R
"
E
R2
10
15
8.82 V
( RC1 R1 R2 )
4 3 10
(8.82 0.5)
0.978 mA
2.35 6.15
V2 VBE1 I C1 RE"
V2 0.6 V (0.978 mA)(6.15 k)
0.6 V 6.01 V 6.61 V
Hence for the given Schmitt trigger
V 1 = 8.58 V
V 2 = 6.61 V
6. The self-bias transistor bistable multivibrator shown in Fig. 9p.3 uses npn Si
transistors. Given that V CC = 15 V, V CE(sat) = 0.2 V, V = 0.7 V,
R C = 3 k ,R 1 = 20 k ,R 2 = 10 k ,R E = 500 . Find:
(i) Stable-state currents and voltages and the h FE needed to keep the ON device in
saturation.
(ii) f (max) , if C 1 = 100 pF.
(iii) The maximum value of I CBO that will still ensure one device is OFF and the other is
ON.
(iv)The maximum temperature up to which the multivibrator can work normally if I CBO at
25C = 20 A.
Fig. 9p.3 The given self-bias bistable multivibrator
Solution:
(i) To calculate I B2 , consider the base circuit of Q 2, Fig. 6.1.
Fig.6.1. Circuit to calculate V thb and R thb of Q 2 .

From Fig. 6.1,
Vthb VCC
R2
15 10
150
=
= 4.54
RC R1 R2 3 20 10 33
V
Rthb R2 ( RC R1 ) =
10 (3 20) 230
=6.96 k
3 20 10
33
(ii) To calculate I C2 , consider the collector circuit of Q 2 , Fig. 6.2.

.
Fig. 6.2. Circuit to calculate V thc and R thc of Q 2

R1 R2
15 (20 10) 450
=
=13.6 V
RC R1 R2
3 20 10
33
3 30 90
Rthc RC (R1 R2 ) =
=2.72 k
33
33
Vthc VCC
10
Now let us draw the base and collector circuits of Q 2 , Fig. 6.3.
Fig. 6.3. Circuit to calculate I B2 and I C2

Writing the KVL equations of the input and output loops
4.54 0.7= (6.96+0.5) I B2 + 0.5I C2
13.6 0.2 = 0.5I B2 + (2.72+0.5) I C2
Eqs. (1) and (2) are simplified as
3.84 = 7.46I B2 + 0.5I C2
13.4 = 0.5I B2 + 3.22I C2
Solving Eqs. (3) and (4) for I B2 and I C2 we get
I B2 = 0.263 mA
I C2 = 3.75 mA
3.75
h FE =
= 14.25
0.263
The h FE that keeps the ON device in saturation is 14.25.
(1)
(2)
(3)
(4)
V EN2 = ( I B2 + I C2 )R E = (0.263+3.75)0.5 = 2 V
V CN2 = V EN2 + V CE(sat) = 2 + 0.2 = 2.2 V
V BN2 = V EN2 + V = 2 + 0.7 = 2.7 V.
R2
2.2 10 22
=0.733 V
R1 R2 20 10 30
V BE1 =V BN1 V EN2 = 0.733 2 = 1.26 V
V BN1 = VCN 2
Hence Q 1 is OFF
V CN1 should be V CC. But actually it is less than V CC .
VCC V BN 2 15 2.7
=
0.534 mA.
RC R1
3 20
V CN1 = V CC I 1 R C = 15 (0.534)(3) =13.4 V.
I1=
f max
R1 R2
(20 10)103
750 kHz
2 R1 R2 C1 2 20 103 10 103 100 1012
(iii) V BE1 was calculated as 1.26 V. This voltage exists at the base of Q 1 to keep Q 1
OFF. Till such time the voltage at B 1 of Q 1 is 0 V, let us assume that Q 1 is OFF, Fig.
6.4.To calculate R B and hence I CBO R B , short V EN (though I E1 = 0, there exists a
11
voltage V EN at the first emitter) and V CE(sat) sources. From Fig. 6.4, it is seen that R B is
the parallel combination of R 2 and (R 1 +R E ).
Fig. 6.4. Circuit to calculate I CBO R B

RB R2 ( R1 RE )
10 20.5
6.72 k
10 20.5
Until I CBo(max) R B = V BE1, Q 1 will be OFF.
I CBo(max) =
1.26 V
0.187 mA 187 A
6.72 k
(iv) I CBo at 25C = 20 A

I CBo (max)
187
9.35
I CB 0
20
9.35 = 2n
log 9.35 0.97
3.23
log 2
0.3
T
n
10
T2 25
3.23
10
T2 25 32.3 57.3C
n=
7. (a) Design a Schmitt trigger shown in Fig. 9p.4 with UTP of 8 V and LTP of 4 V. Si
transistors with h FE = 40 and I C = 5 mA are used. The supply voltage is 18 V. The
ON transistor is in the active region for which V BE = 0.6 V, V CE = 2.0 V. (b) Calculate
R e1 for eliminating hysteresis.
12
Fig. 9p.4 The Schmitt trigger circuit

Solution:
Till UTP is reached Q 1 is OFF and Q 2 is ON and in active region. Just at V 1 (UTP) Q 1
goes ON and Q 2 goes OFF. Just prior to this, Q 2 is ON and Q 1 is OFF, Fig. 7.1.
Fig. 7.1 Circuit when Q 1 is OFF and Q 2 is ON

V 1 = UTP = V BN2 = 8 V
I E = I C2 = 5 mA
V EN = V EN2 = V BN2 V BE2
V EN2 = 8 0.6 = 7.4 V.
V
7.4
RE EN 2
IE
5 mA
13
= 1.48 k
Choose R E = 1.5 k
If Q 2 is in the active region and V CE = 2 V
I C2 R C2 = V CC V CE V EN2
RC 2
Choose R C2 = 1.75 k
18 2.0 7.4 8.6 V
1.72 k
5
5 mA
1
I C 2 0.5 mA
10
V
8V
R2 BN 2
=16 k
I2
0.5 mA
I2
I B 2 min
I C 2 5 mA
0.125 mA
hFE
40
I B 2 1.5 I B 2 min 1.5 0.125 0.1875 mA

I B 2 I 2 0.1875 mA+0.5 mA 0.6875 mA
( RC1 R1 )
VCC VBN 2 18 8
10
14.55 k
( I B 2 I 2 ) 0.6875 0.6875
R1 14.55 k RC1
At LTP = 4 V, consider the Fig. 7.2.
Fig. 7.2 Circuit at LTP

Let I 1 be the current in R 2
V BN2 = V BN1 = 4 V = LTP = V 2
I1
VBN 2
4V
0.25 mA
16 k
R2
I C 1 I E1
V2 VBE1 4 0.6
1.5 k
RE
14
I C1 = 2.27 mA
Writing the KVL equation of the outer loop consisting of R C1 , R 2 and R 1 ,
V CC = (I C1 +I 1 )R C1 +I 1 (R 1 +R 2 ) = (I C1 +I 1 )R C1 +I 1 (14.55 k R C1 +R 2 )
V CC = I C1 R C1 +I 1 (14.55 k +R 2 )
V I (14.55 R2 )
RC1 CC 1
I C1
18 0.25(14.55 16) 10.36
4.56 k
2.27
2.27
R C1 = 4.56 k
R 1 = (R C1 R 1 ) R C1 =14.55 4.56 = 9.99 k
Choose R 1 = 10 k and R C1 = 4.5 k .

The designed Schmitt trigger circuit is shown in Fig. 7.3 with component values.
Fig. 7.3 Designed Schmitt trigger

(b) To eliminate hysteresis R e1 is added in series with the emitter of Q 1, Fig. 7.4, such that
V 1 V 2 = V H = (I C1 +I B1 )R e1
4V
1.76 k
R e1 =
2.27 mA
15
Fig. 7.4 R e1 connected to eliminate hysteresis

8. (i) Design a Schmitt trigger in Fig.9p.5 with UTP of 8 V and LTP of 4 V. Si transistors
with h FE = 40 and I C = 4 mA are used. The supply voltage is 12 V. The ON transistor
is in saturation for which V BE = 0.7 V, V CE(sat) = 0.2 V. (ii) Calculate R e1 for
eliminating hysteresis. (iii) Find R e2 to eliminate hysteresis.
Fig. 9p.5 The given Schmitt trigger circuit

Solution:
(i) Till UTP is reached, Q 1 is OFF and Q 2 is ON and in saturation region. Just at
V 1 (UTP) Q 1 goes ON and Q 2 goes OFF. Just prior to this, Q 2 is ON and Q 1 is OFF,
Fig. 8.1.
16
Fig. 8.1 Circuit when Q 1 is OFF and Q 2 is ON

V 1 = UTP = V BN2 = 8 V
I E = I C2 = 4 mA
V EN = V EN2 = V BN2 V BE2
V EN2 = 8 0.7 = 7.3 V.
V
7.3
RE EN 2
1.825 k
IE
4 mA
If Q 2 is in the saturation region and V CE = 0.2 V
I C2 R C2 = V CC V CE V EN2
12 0.2 7.3 4.5 V
RC 2
1.125 k
4
4 mA
1
I 2 I C 2 0.4 mA
10
V
8V
R2 BN 2
=20 k
I2
0.4 mA
I
4 mA
I B 2 min C 2
0.1 mA
hFE
40
I B 2 1.5 I B 2 min 1.5 0.1 0.15 mA
I B 2 I 2 0.15 mA 0.4 mA 0.55 mA
( RC1 R1 )
VCC VBN 2 12 8
4
7.27 k
(I B2 I2 )
0.55 0.55
R1 7.27 k RC1
At LTP = 4 V, consider Fig. 8.2.
17
Fig. 8.2 Circuit at LTP

Let I 1 be the current in R 2
I1
V BN2 = V BN1 = 4V = LTP = V 2

VBN 2
4V
=
=0.2 mA
20 k
R2
V2 VBE1
4 0.7
1.8 mA
RE
1.825 k
Writing the KVL equation of the outer loop consisting of R C1 , R 2 and R 1 ,
V CC = (I C1 +I 1 )R C1 +I 1 (R 1 +R 2 )
V CC = (I C1 +I 1 )R C1 +I 1 (7.27 R C1 +R 2 )
V CC = I C1 R C1 +I 1 (7.27+R 2 )
V I 1 (7.27 R2 )
RC1 CC
I C1
12 0.2(7.27 20) 10.36
RC1
3.6 k
1.8
2.27
R 1 =(R C1 R 1 ) R C1
R 1 = 7.27 3.6 = 3.67 k
(ii) To eliminate hysteresis R e1 is added in series with the emitter of Q 1 , Fig. 8.3, such
that
V 1 V 2 = V H = (I C1 +I B1 )R e1
4V
=2.22 k
R e1 =
1.8 mA
I C1 I E1
18

(iii) To eliminate hysteresis R e2 is added in series with the emitter of Q 2, Fig. 8.4, such
that

V'
VCC R2
12 20
8.8 V
RC1 R1 R2 3.6 3.67 20
R ' =R 2 //(R C1 +R 1 ) =
20 7.27
5.33 k
27.27
We know,
(1 hFE ) RE
V
R '(1 hFE )( Re 2 RE )
41 1.825
4 (8.8 0.7)
0.5
5.33 (41)( Re 2 1.825)
V2 (V ' VBE 2 )
19
606
80.1 41Re 2
143.5R e2 =325.65
R e2 =2.26 k .
3.5
20

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Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

VCC VCE (sat)

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 9p.2 The fixed-bias bistable multivibrator

Calculate V B1 to verify whether Q 1 is OFF or not.

Fig. 2.1 Circuit to calculate the base current of Q 2

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

VCC V 10 0.3 9.7 V

V VBB 0.3 10 10.3

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 2.2 Circuit to calculate the collector current of Q 2

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

VCC VCE (sat)

9.9 0.34 9.56 mA

Fig. 2.3 Circuit to calculate maximum load current

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

3. Design a self-bias bistable multivibrator shown in Fig.9p.2 with a supply voltage of

Fig. 9p.2 Self-bias bistable multivibrator

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Choose I B2 = 1.5I B2(min) = 0.12 mA

VCC VCE (sat) VEN 2

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

6.7 0.15 R1 6.7 0.15 R1

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 9p.4 The Schmitt trigger circuit

VEN 2 (8.82 0.6)

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Rt 0.769 3.05 2.35 k

Fig. 9p.3 The given self-bias bistable multivibrator

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig.6.1. Circuit to calculate V thb and R thb of Q 2 .

(ii) To calculate I C2 , consider the collector circuit of Q 2 , Fig. 6.2.

Fig. 6.2. Circuit to calculate V thc and R thc of Q 2

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 6.3. Circuit to calculate I B2 and I C2

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.

Fig. 6.4. Circuit to calculate I CBO R B

Until I CBo(max) R B = V BE1, Q 1 will be OFF.

(iv) I CBo at 25C = 20 A

log 9.35 0.97

Dorling Kindersley India Pvt. Ltd 2010

Pulse and Digital Circuits

Venkata Rao K., Rama Sudha K. and Manmadha Rao G.