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CONTENTS
Experiment No Page. No
1. RC coupled amplifier 2
6. Clipping circuits 30
7. Clamping circuits 40
8. Op-Amp applications 46
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Circuit Diagram :-
Design :-
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RC COUPLED AMPLIFIER
AIM: -To design a RC coupled single stage FET/BJT amplifier and determination of
the gain-frequency response, input and output impedances.
APPARATUS REQUIRED:-
PROCEDURE: -
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in
regular steps of 10 and note down corresponding output voltage.
7. Note down the phase angle, bandwidth, input and output impedance.
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1. Input impedance
a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.
2. Output impedance
a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
Vload Vno load
c. Substitute these values in the formula Z O = 100%
Vload
3. Bandwidth
a. Plot the frequency response
b. Identify the maximum gain region.
c. Drop a horizontal line bi 3dB.
d. The 3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of 3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of 3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh fl.
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TABULAR COLUMN : -
Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi
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Result :-
Theoretical Practical
Input impedance
Output impedance
Bandwidth
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Circuit Diagram :-
DC Analysis :-
-7-
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To design a BJT Darlington Emitter follower and determine the gain, input and
AIM: -
output impedances.
APPARATUS REQUIRED:-
PROCEDURE: -
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in regular
steps of 10 and note down corresponding output voltage.
7. Note down the phase angle, bandwidth, input and output impedance.
-8-
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Design :-
VCC 12
VE2 = = = 6v
2 2
IE2RE = VE2
VE2 6
RE = = = 1.2 k [ IE 2 = IC 2 ]
I E2 5 103
R E = 1.2k
VB1 = 7.4 v
I C 2 5 103
IB2 = = = 0.05mA
100
I C1 I B2 0.05
IB1 = = = = 0.0005mA
100
12 - 7.4
R1 = = 920k [Use R 1 = 1M]
10 0.0005 10-3
VB1
R2 = = 1644k
9I B
R 2 = 1.5M
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1. Input impedance
a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.
2. Output impedance
a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
Vload Vno load
c. Substitute these values in the formula Z O = 100%
Vload
3. Bandwidth
a. Plot the frequency response
b. Identify the maximum gain region.
c. Drop a horizontal line bi 3dB.
d. The 3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of 3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of 3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh fl.
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TABULAR COLUMN: -
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4. To find Q-Point
a. Connect the circuit as per circuit diagram
b. Switch on the DC source [switch off the AC source]
c. Measure voltage at VB2, VE2 & VC2 with respect to ground
& also measure
VCE2 = VC2 - VE2
V E2
I C2 = I E2 =
RE
Q - Point = [VCE2 , I C2 ]
Result
Theoretical Practical
Input impedance
Output impedance
Bandwidth
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Circuit Diagram :-
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AIM: - gain, frequency response, input and output impedances with and without
feedback
APPARATUS REQUIRED:-
PROCEDURE: -
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in
regular steps of 10 and note down corresponding output voltage.
7. Note down the phase angle, bandwidth, input and output impedance.
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Given AV1 = 30; A12 = 20; VCC = 10V; IE2 = 1.8mA; IE1 = 1.1mA; S = 3; hfe1 and hfe2
are obtained by multimeter = 0.03
DC Analysis of II Stage: -
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1. Input impedance
a. Connect a Decade Resistance Box (DRB) between input voltage source and
the base of the transistor (series connection).
b. Connect ac voltmeter (0-100mV) across the biasing resistor R2.
c. Vary the value of DRB such that the ac voltmeter reads the voltage half of
the input signal.
d. Note down the resistance of the DRB, which is the input impedance.
2. Output impedance
a. Measure the output voltage when the amplifier is operating in the mid-band
frequency with load resistance connected (V load).
b. Measure the output voltage when the amplifier is operating in the mid-band
frequency without load resistance connected (V no-load).
Vload Vno load
c. Substitute these values in the formula Z O = 100%
Vload
3. Bandwidth
a. Plot the frequency response
b. Identify the maximum gain region.
c. Drop a horizontal line bi 3dB.
d. The 3dB line intersects the frequency response plot at two points.
e. The lower intersecting point of 3dB line with the frequency response plot
gives the lower cut-off frequency.
f. The upper intersecting point of 3dB line with the frequency response plot
gives the upper cut-off frequency.
g. The difference between upper cut-off frequency and lower cut-off
frequency is called Bandwidth. Thus Bandwidth = fh fl.
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TABULAR COLUMN: -
With Feedback (Vi = 50mV)
Sl No. Frequency VO (volts) Gain = VO/Vi Gain (dB) =20log VO/Vi
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Result
Theoretical Practical
With f/b Without f/b With f/b Without f/b
Input impedance
Output impedance
Bandwidth
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Circuit Diagram :-
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To design And test for the performance of RC Phase Shift Oscillator for the
AIM:
- given operating frequency fO.
APPARATUS REQUIRED:-
PROCEDURE: -
2. Switch on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare with its theoretical frequency.
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Result
Theoretical Practical
Frequency
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HARTLEY OSCILLATOR:-
DESIGN:-
1
f= , where L=L1+L2
2 LC
L2
Assume = 5, Let L1=2mH L2=10mH
L1
Vgs 2
Let Vgs =-1.5V, Id =Idss (1 ) = 3mA
Vp
2 Idss Vgs
gm= (1 ) = 4mmhos
Vp Vp
Vs Vgs 1.5
RS= = = = 500
Id Id 3m
L2
Assume Av =10 (> ) 10 = g .Rd
m
L1
10
Rd = = 2.5 K
4m
Assume Rg =1M, Cc1=Cc2=0.1f,Cs=47 f,
Assuming Vds=5V
Vdd = IdRd+Vds+Vs=14V
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To design and test for the performance of FET Hartley & Colpitts
AIM:
- Oscillators.
APPARATUS REQUIRED:-
PROCEDURE: -
2. Switch on the power supply and observe the output on the CRO (sine wave).
3. Note down the practical frequency and compare with its theoretical frequency.
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COLPITTS OSCILLATOR:-
DESIGN:-
1 C1C 21
f= , where C
2 LC C1 + C 2
C1
Assume = 5, Let C1=500pF C2=100pF
C2
L =0.12H, for f=50KHz
Vgs 2
Let Vgs =-1.5V, Id=Id =Idss 1 ) = 3mA
Vp
2 Idss Vgs
gm = = = 4mmhos
Vp Vp
Vs Vgs 1.5
Rs = = = = 500
Id Id 3m
C1
Assume Av =10 (> ) 10 = g .Rd
m
C2
10
Rd = = 2.5 K
4m
Assume Rg =1M, Cc1=Cc2=0.1f,Cs=47 f,
assuming Vds=5V
Vdd = IdRd+Vds+Vs=14V
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DESIGN:-
1
f = 1 MHZ =
2 LC
Assume L=.33H, C=0.0767pF
Let Vce = 6V, Ic = 2mA,
Choose Vcc 2 Vce
Vcc
Assume Ve = = 1.2V
10
Ve Ve
Re = = 1.2V
Ie Ic
Ve Ve 1.2
Re = = = 600
Ie Ic 2m
R1 =34K
Vcc - Cce - Vre 12 6 1.2
Rc = = = 2.4 K
Ic1 2m
Assume Cc1=Cc2=0.1f, Ce = 47 f,
Result:-
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Circuit Diagram:-
Series Clippers
a) To pass ve peak above Vr level :-
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CLIPPING CIRCUITS
To design a Clipping circuit for the given specifications and hence to plot its
AIM:
- O/P
APPARATUS REQUIRED:-
PROCEDURE: -
2. A sine wave Input Vi whose amplitude is greater than the clipping level is
applied.
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Design :-
Choose Rf = 10, Rr = 1M
R = RfRr = 3.3K
e) To pass +ve peak above some level (say +4v) and ve peak above
some level (say -3v)
ie., VR+Vr = 4
VR = 3.4v
-(VR+Vr) = -3v
VR = 2.4v
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Shunt Clippers
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l) To remove +ve peak above some level (say +3v) and ve peak above
some level (say -3v)
ie., (VR1+Vr) = 3v
VR1 = 2.4v
-(VR2+Vr) = -3v
VR2 = 2.4v
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Circuit Diagram:-
a) Positive peak clamped at Vr level :-
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CLAMPING CIRCUITS
To design a Clamping circuit for the given specifications and hence to plot
AIM:
- its output.
APPARATUS REQUIRED:-
PROCEDURE: -
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DESIGN :-
Let RL = 100K
C = 1f
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RESULT :-
a)
b)
c)
d)
e)
f)
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Circuit Diagram:-
INVERTING AMPLIFIER:-
NONINVERTING AMPLIFIER:-
VOLTAGE FOLLOWER:-
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APPARATUS REQUIRED:-
PROCEDURE: -
DESIGN:-
Rf
a) Inverting Amplifier: Let Av = 10 =
Ri
Assume Ri = 1k Rf = 10 K, Ri = 10K
Rf
b) Non Inverting Amplifier Let Av = 11 =1 +
Ri
Assume Ri =1k Rf = (11-1) Ri = 10k
c) Voltage follower Av =unity.
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SUMMER:-
DIFFERENTIATOR:-
INTEGRATOR:-
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DESIGN:-
a) Integrator
RC>>T
Let T=1msec and RC = 100 T = 100 msec
Assume R = 100 K C = 1
Assume Rf = 10 K
b) Differentiator:-
RC<<T
Let T =1msec and Rc =0.01f
Assume R =1K
c) Summer:-
Rf Rf Rf
Let Y=2V1+V2+3V3= V1 + V2+ V3
R1 R2 R3
Rf Rf Rf
i.e, = 2, = 1and V3
R1 R2 R3
Assume Fr = 10k R1=5K, R2=10k and R3=3.33k
Assume R = 10k
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Circuit Diagram:-
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SCHMITT TRIGGER
To design and test USING Operational amplifiers for the performance of:
AIM: (1)Zero Crossing Detector, (2) Schmitt Trigger for different hysterisis
-
values.
APPARATUS REQUIRED:-
PROCEDURE: -
6. For Schmitt Trigger set input signal (say 1V, 1 KHz) using signal generator.
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WAVE FORMS:-
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DESIGN:-
VRRI VsatR 2
Let UTP = 6V = +
R1 + R 2 R1 + R 2
VRRI VsatR 2
LTP = - 2V = +
R1 + R 2 R1 + R 2
2VRRI 2( R1 + R 2) R2
UTP + LTP =4 = VR = = 2(1 + )
R1 + R 2 R1 R1
2VsatR 2 R1
UTP - LTP =8 = VR = =2
R1 + R 2 R2
VR = 3V, Assume R2 = 1 K R1 = 2 K
LTP = - 4, + 2, - 4 and = 4
RESULT: -UTP and LTP is measured and compared with the designed value.
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DESIGN:-
5 Rf
(i) Given A = = 10 =
0.5 Ri
Assume Ri = 1k , Rf = 10K
Choose R = 10K
Rf' = Rf = 10K
5 Rf 3 Rf Rf '
(ii) Given A1 = = 10 = and A2 = =6=3
0.5 Ri 0.5 Ri 2R + Rf '
Assume Ri = 1K
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APPARATUS REQUIRED:-
PROCEDURE: -
3. Switch on the power supply and note down the output from CRO.
4. Without Connecting Rf 2, the wave form of the half wave rectifier is produced.
RESULT:-
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DESIGN:-
Given VO = 12 v
R
VO = 7.15 1 + 1
R2
R
12 = 7.15 1 + 1
R2
Assume R 1 = 10K
R 2 = 17.7K [use 15K ]
Assume R L = 720 & C = 100pf
CHARACTERISTIC CURVE: - OBSERVATION:-
Vi (volts) Vo (volts)
Vo
(volts)
7v Vi (volts)
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APPARATUS REQUIRED:-
PROCEDURE: -
2. Switch on the power supply and note down the output from CRO.
3. Vary the input voltage from 7V, note down corresponding output voltage.
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DESIGN:-
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PROCEDURE:-
2. For line regulation vary the input voltage from 7V, note down the
corresponding output voltage.
GRAPH:-
Vo
(volts) Vo
(volts)
Vi (volts)
Io (mA)
OBSERVATION:-
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CIRCUIT DIAGRAM: -
b b b b
V0 = R f 3 + 2 + 1 + 0 Vref
2R 4R 8R 16R
Note: -
1. b3, b2, b1 and b0 are binary input.
2. Vref = 5V.
Vref
3. If b is the decimal value of the binary input b3, b2, b1, b0, then V0 = b
8
4. Vo is the analog output
5. Binary inputs can either take the value 0 or 1
6. Binary input bi can be made 0 by connecting the input to the ground. It can be
made 1 by connecting to +5V
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APPARATUS REQUIRED:-
PROCEDURE: -
2. The IC is given proper bias of +12V and -12V to Vcc and Vee
respectively.
3. According to the binary values of b3, b2, b1 and b0, b3, b2, b1 and b0 are
connected to +5V or Ground respectively.
4. The o/p voltage is tabulated for different binary inputs and is compared with
the theoretical values.
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O/P vs I/P
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Tabular Column:-
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APPARATUS REQUIRED:-
PROCEDURE: -
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PIN DIAGRAM:-
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Tabular Column:-
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