Fault Tolerance in Active Power Filters, Based on

Multilevel NPC Topology

Pedro Faria Lopes A. M. S. Mendes

University of Coimbra / Instituto de Telecomunicac;oes

Department of Electrical and Computer Engineering, Polo 2 - Pinhal de Marrocos
P - 3030-290 Coimbra, PORTUGAL
pfarialopes@gmail.com, amsmendes@ieee.org

Abstract - The use of neutral-point-clamped (NPC) converters in
high power systems brings many advantages when compared
with traditional ones, and its application in active power filters is
no exception. However, since it is needed a greater number of
switching devices, the probability of a failure in these devices is
higher and must be therefore to be taken into account. Then, in
this paper is proposed a method of fault detection and fault
tolerance operation in shunt active power filters, based on three
level NPC topology. The effectiveness of these techniques is
demonstrated by simulation results.
I. INTRODUCTION
The first neutral-point-clamped (NPC) configuration was
presented in 1981 by A. Nabae, I. Takahashi, and H. Akagi
[1], and proved to have great advantages compared with the
very well-known two-level converters. This new topology
was created in order to enable the use of typical switching
devices in high voltage applications, since each of these
devices has to stand half of dc bus voltage. Furthermore, as
the number of levels increase, output voltage quality is
improved, decreasing the total harmonic distortion (THO) [2].
In the fault tolerance perspective, there is another one great
advantage that will be explored in this paper: the existence of
redundant states. Besides the NPC configuration, there are
other multilevel topologies, like the Capacitor-Clamped
Inverter and the Cascaded Multicell Inverters [3].
Despite the evident advantages of multilevel converters,
their implementation in industry has been slowed down by
technological problems such as reliability, control complexity
and design of fast modulation strategies [2].
A great application of this technology resides in the active
power filters. In the past recent years, the number of
nonlinear loads in industry has been increased significantly,
which results in a considerably higher harmonic pollution. In
the 1970s [4], in order to minimize this pollution, it was
established the basic operation of active power fIlters,
offering a superior fIltering performance over the traditional
passive fIlters. The emergence of insulated-gate bipolar
transistors (IGBTs), digital signal processors (DSPs) and
analog-to-digital converters have supported a deeper interest
in active filters [5]. In the late 1990s and early 2000s, the
NPC topology revealed to be a suitable alternative to the
conventional two-level bridge in active filters [6], [7].
The reliability of these systems is critical and, in some
particular applications, a switch device failure can stop the
whole system. Thus, it is crucial to detect any fault in these
devices and act immediately in order to keep the system
operational. Several fault detection and tolerance methods in
active filters are described in [8]-[I0], but they are applied in
filters using a conventional two-level inverter. Regarding the
NPC topology, these methods are covered in [11]-[16], but
some of them cannot detect with precision which device is
faulty [13], others use a significant number of sensors
[12],[13] or modifications in NPC circuit configuration
[15],[16], and the remaining implicates the reduction of the
output voltage of the NPC inverter [13], [16]. Either way,
none of these papers have proposed solutions for fault
diagnosis and fault tolerance applied to active power filters
based on NPC topology.
Thus, in this paper is proposed and analyzed a diagnostic
and a fault tolerance method techniques applied to a shunt
active power filter implemented with a three-level NPC
voltage-source inverter.
II. SYSTEM DESCRIPTION
A. System Corifiguration
The schematic of the analyzed circuit is illustrated in Fig.
1. This circuit includes four main blocks: the shunt active
power fIlter block, based on a three-level NPC topology, the
non-linear load block, based on an RL load fed by a three
phase diode rectifier, the block with grid and power
transformer, and the triacs block. The connection between
NPC converter and the grid is performed by three choke
inductances. Additional hardware required by the developed
fault tolerance technique is represented in blue: 3 triacs and 6
fast fuses. The three-phase grid voltages are supposed to be
balanced.
In the next sections, the following terminology will be
used, regarding switching devices position:
Upper switches: Slyand S2y, y=I,2,3;
Lower switches: S3yand S4y, y=I,2,3;
Outer switches: Slyand S4y, y=I,2,3;
Inner switches: S2yand S3y, y=I,2,3;
B. Controller
The controller is designed taking into account two main
objectives: compensate the power factor and eliminate the
harmonic distortion. To accomplish that, the following
voltages and currents signals must be acquired accurately:
Vah, V%c, Vdc, IFm IFh ha and hh. The voltage Vca and the
currents IFc and Ir,c can be calculated using the previous
values. On the basis of these data, the control system must be

978-1-4673-2421-2/12/$31.00 2012 IEEE 410

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Shunt active power filter Three-phase triacs

Fig. 1. System configuration of shunt active power filter with fault tolerance elements

able to generate the reference currents ha *, Iph *, Ipc * in order

to obtain the appropriate grid currents.
These reference currents will be calculated based on pq
[IfJ<] /
=_ _,

va-+v r
[VVafJ -VVI!a ] [-p+p/os j
_q
(7)

theory [17]. Using Clarke's transformation, the calculations The compensation of Ploss assures that the dc bus voltage
involving the measured values will be performed in time level is maintained at a constant reference level. The value of
domain and processed in the afJ reference frame. Since there
is no neutral wire, the direct and inverse transformations are
p can be calculated subtracting p to p,
where p can be
obtained using a low-pass filter. Since a voltage modulator is
given by (I) and (2), respectively. used, the reference currents must be "converted" into the

[XrXfJl] 3{2 [I
_ -1/2 -1/2 ] rlX:al (I)
corresponding reference voltages (va Vb Vc
) This can be
*,

done by a current controller, submitting the current error to a

*, * .

- 0 V3/2 -V3/2 PI controller.

)i/2
-V3/2
] [afJ]
Where Xa, Xb, Xc can be instantaneous values of currents
or phase-to-neutral voltages. The real power (P) and the
imaginary power (q) in afJ reference frame are given by (3)
or, in an alternative way given by (4). Taking into account the
dc and ac components, the real and imaginary powers can be
determined by (5) and (6), respectively. The physical
meaning of these powers is described in detail in [17].
[ = [:;
-::.!j [;]
p=p+p
q=q+q
Considering that harmonic distortion and reactive power
must be canceled, the ac component of the real power (jJ) and
the total imaginary power (q) must be both compensated by
the active filter. Furthermore, in a real implementation, the
losses in the active filter must also be compensated. Thus,
considering the previous assumptions and (4)-(6), the
reference currents i" *, i;/ that must be introduced in the
system are determined by (7), where Ploss is the losses in
active filter.
(2) C. SVPWM Modulator
The Space Vector Pulse Width Modulation (SVPWM)
technique is based on the selection of 3 suitable vectors and
respective dwell times, required to obtain a specific voltage
reference vector.
The switching states of a three-level inverter are shown in
Table I, as each leg can be connected to positive (P state),
neutral (0 state) or negative (N state) voltage point of dc bus.
Considering the three phase legs and three possible states for
3
each one, all 3 possible state vectors are represented in Fig.
(3) 2.
As shown in Fig. 2, a specific vector can be created from
different switch states (redundant states). Note that in a two
(4) level inverter, the null vector is the only redundant one. This
characteristic will be really essential in the next chapters.
(5)
(6)
Furthermore, depending on the selected voltage vector, four
different magnitudes are perceptible: 0, (l/2) Vdc. (V3/3) Vdc
and (2/3) Vdc.
For the NPC converter, the IGBTs switching sequence is
very important in order to keep the voltage of the neutral
point balanced. In this work, a sequence suggested in [18]
was used, where each sector is divided into 6 subsectors.
Furthermore, vectors created by redundant states are splited
into two vectors: one related with a positive-neutral points
connection (Vxp) and other with a negative-neutral points
connection (V,N), where x is the vector number.

411

Fig. 2. State vectors diagram for a 3-level NPC inverter
TABLE I
SWITCHING STATES AND NEUTRAL POINT VOLTAGE
States S ,y S2y S3y S4y
P ON ON OFF OFF
0 OFF ON ON OFF
N OFF OFF ON ON
Supposing a voltage reference located in the shaded area in
Fig. 2, the three nearest vectors that must be chosen are VI, V2
and V7. The dwell times are given by:
{V7TTa+V;TTh+TViTeT =T,
a+ h + c- ,
Where Ts is the switching period and Ta, Tb, Tc the dwell
times of the respective vector. For each sector and subsector
the switching sequence is given by the tables developed i
[18], which will be converted to the respective pulses.
III. FAULT IMPACTS
The maj ority number of faults in a power converter occur
in a power or control circuits and are reflected in a permanent
state of short-circuit or open-circuit of a switching device.
Either way, a fault will be reflected in voltage and current
changes, affecting the entire system.
When an open-circuit fault occurs, some connections may
not be established in the converter power circuit. In other
words, the phase where the fault occurs is not connected to
the supposed voltage level, causing a change in Vyo and IFy,
" "
being y the faulty phase and "0" the neutral point of NPC
bridge. An open-circuit fault in an inner switch brings more
severe consequences than in an outer switch since it makes
impossible the occurrence of two states and not merely one.
In the first case, the phase current is mostly positive (Szy
fault) or negative (S3y fault).
Considering, for example, an open-circuit fault in SZ1, a
negative current IFa can only flow through D31 or D41, which
can only happen due to the inductance effect in a short period
of time. This failure is immediately perceptible by the great
increase of source current distortion. In the other hand, if the
fault occurs in an outer switch, Sll for instance, the distortion
suffers, in most cases, j ust a slight increase. However, when
any open-circuit fault occurs, the voltage level at the
capacitors terminals will start to rise/fall over time, even with
a constant dc bus voltage. This happens because the fault
prevents the inverter to achieve all the possible states. So, if
the states are not all available, some connections between the
neutral and positive or negative points of the dc bus are not
performed and the switching strategy will fail to maintain the
same voltage across the two capacitors. If no action is taken,
the neutral point voltage can drift to unrecoverable level [19].
Unlike open-circuit faults, when short-circuit ones occur in
a switching device, a fast response is absolutely critical.
When this type of fault happens, a short-circuit is performed
between the two terminals of one capacitor. For example, if
Sll remains in the "on-state", when the state is active in
phase A (S21 and S31 active) the upper capacitor is short
circuited. The high currents that this type of fault produces
will surely damage the system if no action is taken.
IV. FAULT DIAGNOSIS METHOD
The open-circuit diagnostic method is based on the
VYO
comparison between estimated filter line voltages (VFah, VFhc,
VdJ2
VFea) and the expected voltages generated by the modulator.
a
-VdJ2
This is a fast and reliable method, but it requires a great
precision in the calculation of the filter line voltages.
The first step resides on the calculation of Vfab, Vfbc and
VFca based on the voltages VSab, V%e and Vca and on the
currents Ira, IFb and IFe:
(8) ( d;,' +RFIFa) + (LFdh +RFI )
VFab= V,ab- LF Fb (9)
VFbc=V%c- (LFdh +RFIFb ) + (LF d/ +RFIFC ) (10)
dlFc RFIFe) + (LFddilFa +RrIra )
VFea- Sca- (LFdi+
-v, (11)
The second step includes the calculation of the theoretical
voltage applied by the modulator. The modulator output
(states P,O,N) is converted to a voltage value in the afJ
reference frame (Fig. 2) and then the inverse Clarke's
transformation is applied to get the time domain reference
frame voltages (VMab, VMbc and VMca).
In normal conditions, the filter line voltages can only
assume five different values: Vdc, Vd/2 and o. So, if any of
the calculated voltages VFah, VFhc, VFca are different from
these values, it means that a fault occurred.
Since line voltages are considered, a switching device
failure will affect two of these voltages, remaining one of
them unaffected. For instance, if a fault occurs in a switching
device connected to phase b, for example Szz, VFab and VFbc
will deviate from the above mentioned values, while VFca is
not affected. The relationship between the line voltages and
the faulty leg can be seen in Table II.
To identify the faulty IGBT, and taking into account the
actual switching state, the voltages VFah, VFhc, VFca are
compared with VMah, VMh" VMea. The switching state in which
two voltage pairs are different will identify the faulty IGBT.
If the failure occurs in an outer IGBT, then the voltage errors
are detected during the states P or N. On the other hand, if the
open-circuit is caused by an inner switch, these errors are
identified during the P and states or N and states since
this type of faults affects two switching states. Table III
resumes this evidence. For example, if a deviation is detected
in Vfbe and Vfca while state P is active, then an open-circuit
fault occurred in S13 or S23. If in the next moments these
voltages deviate from VMhc and VMea while state is active'
S23 is the faulty switch; otherwise, the problem lies in Sl3.
412
 TABLE II
CORRESPONDENCE BETWEEN FILTER LiNE VOLTAGES AND NPC PHASE LEG
STATUS
Voltages outside Voltages within
Faulty Phase
reference values reference values
--- VFab, V}bc, vJ<ca
Vt'ab, vJ<ca Vi'bc
Vi'b. Vi'1>c Vl-'ca
VPhc) VPca VPah
TABLE III
CORRESPONDENCE BETWEEN ERROR STATES AND FAULTY SWITCHES
States with voltage error Faulty Switch
P Sly
P and O S2y
N and O Sly
N S4y
Since this method is based on instantaneous voltage values,
its response is quite fast, able to detect a fault in less than half
the fundamental period. Typically, it is even faster than that,
as can be seen in the performed simulations (Fig. 9). Notice
that this technique involves estimated voltages, which implies
that the error between two voltage levels may not be null,
even in normal operation. An appropriate threshold error
must be defined in order to avoid false positives.
Besides the fast detection, this process can specifically
identify which switching device is faulty. Even if this detailed
information is not necessary to the tolerance system, it is
always useful to know which switch must be replaced
afterwards. Furthermore, this technique is implemented with
no additional sensors.
V. FAULT TOLERANCE METHOD
A. Open-Circuit Faults
When a fault is detected, a tolerant system must react so
that the system can remain functional until it can be repaired.
In [18], for instance, the output voltage of NPC inverter was
reduced by a factor of .v3. However, in this referenced case,
the inverter was powering a motor and the consequences of
this voltage reduction might not be critical. In the filtering
system, a voltage level reduction of this magnitude will cause
a great distortion in the source current wave. Then, it is
desirable that the output voltage remains the same, as well as
the harmonic distortion of the line current is kept reduced.
This fault tolerant technique is based on the available states
after a fault occurs and on the existence of redundant vectors.
Due to a failure, some connections between NPC inverter and
the 3 phases are not performed properly, invalidating the use
of some switching states. Fig. 3 represents the available states
when a fault in S" occurs, where all voltage vectors that
require this switch in "on" state are disabled. Since crossed
vectors cannot be used, the technique resides in the use of
redundant vectors. Once this type of vectors only exists in the
"inner hexagon", the modulation output will be restricted to
this area. The available large vectors won't be used so that the
output voltage remains balanced.
Nevertheless, in order to preserve the neutral point voltage
balanced, not every redundant vector is used. In this
particular case, the use of the states OON, ONN and ONO is
mandatory, which performs connections between the neutral
and negative points of NPC inverter. So, to conserve this
balance, vectors that connect the positive to neutral points
must be chosen, like OPO, OPP and OOP instead of NON,
No fault
NOO and NNO respectively. This same approach can be
a done to any outer switching device fault.
b If a failure occurs in an inner IGBT, the approach is
C slightly different. Since a failure in one of these devices
affects two states, a lot of vectors will be impossible to
synthetize. Supposing the failure of S21, the impossible states
are not only those indicated in Fig. 3, but also those which
require S21 in the state "on". The use of redundant states in
"inner hexagon" is now impossible to implement, requiring a
different approach. In [16] a connection of each leg to the
inverter neutral point is proposed, controlled by three triacs.
These devices are visible in Fig. 1. This way, when a fault is
detected in an inner switching device, the respective phase is
directly connected to the inverter neutral point. Therefore, the
number of available vectors will increase, as shown in Fig. 4
for a S21 fault, where phase A is connected to the neutral
point. Once again, it is possible to synthetize every "inner
hexagon" vector, excluding once more the few large vectors
still available. In order to avoid a short-circuit between the
neutral and positive or negative point, all four devices
belonging to the affected leg must be disabled.
The implementation of this technique is quite simple. It can
be done with a simple "if-else condition" that analyses the
modulator output states, which changes according to the
faulty switching device. If the output state is acceptable, then
the respective pulses are applied to the NPC inverter.
Otherwise, the actual state is replaced by the respective
redundant one. This block has also the purpose of disabling
the faulty leg if the failure occurs in an inner IGBT.
If no other action is taken, the inverter output voltage will
decrease to half of previous magnitude since no large vectors
will be used. But, like was said before, this is not acceptable
in a filtering system. To solve this problem, the dc bus
voltage reference must duplicate. Nevertheless, this reference
must be smoothly increased to avoid extremely high currents
flowing into the filter.
The implemented solution is based on a ramp that reaches
the final value in a minimum specified time. During the rising
time, if inverter nominal power has been reached, the
reference ramp becomes stable, increasing again when filter
apparent power is below this limit.
Taking into account what was said before, two fundamental
conditions must be ensured before implementing this method:
413
 The capacitors and switching devices must stand this
I I I I
S 5 - - T - - -I - - - I - - I - - - I -
voltage magnitude;
C
The filter must not be operating in its nominal power
:s I I I I
when a fault occurs; U -5 - - T - - -I - - - I - - I - - - I

Simulations regarding this technique have been performed 0.02 0.04 0.06 0.08 0.1 0.12
Time (8)
and are presented in the next chapter.
Fig. 6 Filter current (lFa).
B. Short-Circuit Faults TABLE V
A tolerant method for short-circuits in a switching device FTT ANALYSIS OF THE MOST SIGNIFICANT HARMONICS
can be implemented in a similar way [13], including the Harmonic I I 11'0
technique that avoid a lower voltage output. However, this Order lISa I (A) L(I,) II.al (A) L(I J 11,1 (A) L(IFa)
1 (50Hz) 13.22 85.5 13.03 85.4 0.l9 93.4
method must act really fast in order to avoid the huge currents
5 0.39 312.6 2.62 241.8 2.52 53.5
caused by a capacitor discharge. The proposed detection 7 0.17 104.6 1.62 58.30 1.51 233.70
method is fast, but may not be fast enough. II 0.20 274.8 0.97 212.6 0.90 21.3
To handle this type of faults, 6 fast fuses are connected to THD 6.96% 27.05% ---
each half inverter leg as shown in Fig I. These fuses must
have a lower 12t characteristic than the IGBTs. When a short
circuit occurs, the affected fuse leaves the respective inner
switching device in permanent open-circuit. This occurrence
is diagnosed as an open-circuit fault and the respective
0.08 0.1 0.12
tolerance method is triggered. Time (8)
Fig. 7 Source Current (lsa) when an open-circuit fault occurs in S21.
VI SIMULATION RESULTS
The fast proposed diagnosis method is presented in Fig. 9.

All simulation tests were performed in a Matlab/Simulink The S21 failure occurs at 0.1s and it is detected 1.5ms after
platform and the parameters used in the mathematical model that. This figure allows to observe the difference between the
are shown in Table IV, considering the system presented in estimated line filter voltage (VFah) and reference voltage
Fig. 1 and a maximum IGBT switching frequency of 20kHz. imposed by the modulator (VMah).
Fig. 5 shows the filter impact on line current (Is a) when it is Fig. 10 shows the line current (IscJ behavior when a fault in
connected to the grid at 0.1s and Fig. 6 illustrates the filter S21 occurs at 0.1s. At 0.10 ISs, the fault tolerant system is
current (I}<'eJ in the same period. As may be observed, after activated and the capacitors voltage starts to increase. The
turning the filter on, the line current (Is a) presents an almost system reconfiguration ends at about 0.6s. The
sinusoidal waveform shape. Information about the most reconfiguration time was set to 0.3s, providing a high slope to
significant harmonics of line, load and filter currents (Is a, ha the voltage ramp and forcing the dc bus voltage control to
and Ira) is presented in Table V. This table reflects what was stabilize this voltage reference in order to not exceed the filter
expected: each filter current harmonic should have the same nominal power. This phenomenon is illustrated in Fig. 11 (a).
amplitude than the respective load current harmonic, but in Furthermore, Fig. 11 (b) represents the progress of C1
opposing phase. voltage, remaining stable after the reconfiguration period.
Fig. 7 and Fig. S show the consequences of an open-circuit Fig. 12 and Fig. 13 show the reconfiguration process in the
in S21 at O.ls. In the following simulations, the moment in same conditions, but changing the reconfiguration time to
which a fault occurs is indicated by a black line. It is evident 0.7s, giving to voltage ramp a reduced slope. This time, since
the increased distortion in source current (Fig. 7), the the nominal filter power was not exceeded, the dc bus voltage
variation of dc voltage over CI (Fig. S (a)) and the deviation reference does not have any "steps". In both cases, the total
of V}<ab from the reference values (Fig. S (b)) used for the harmonic distortion in line current in tolerant operation is
proposed diagnostic method. The total harmonic distortion in about 10%. Note that an increased harmonic distortion leads
source current increased to about 17%. to an increased filter apparent power. Fig. 14 shows that the
TABLE IV load current remains almost unchanged during all this
STMULAnON PARAMETERS
process.
Ee,Eb,E, 220Vm",50Hz LL 20mH
Rs ImO RF 0.90 VII. CONCLUSION
Ls O.lmH LF 8mH
3-phase transformer 220V/127V Cj-C2 4.4mF Due to a great number of switching devices, NPC inverter
RL 250 Vdc 600V has a high probability of device fault when compared with
traditional inverter.
In this paper, a fast and accurate fault diagnosis method is
proposed, as well as a tolerant modulation technique.
Combined, they prevent that any harmful consequence may
result from a switching device failure and allow filtering
0.02 0.08 0.1 0.12
Time (8) continuous operation even under fault condition. Comparing
Fig. 5 Filter effect on source current (IsJ. them with existing methods, the proposed ones do not

414
implicate the use of additional sensors nor a decreased output ACKNOWLEDGMENT
voltage in fault condition. The performed simulations confirm
The authors wish to ackowledge the financial support of
the validity of these methods with suitable results.
the Science and Technology Foundation - Portugal (FCT)
under proj ect number PTDCIEEA-EELII00156/2008.
305r-.---_-_-_----'
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Time (s)
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Fig. 12 Source current (Iso) behavior when a fault occurs in S21 and the
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_600 f-'1--:-:;-,:: :-::: "=-::
- ---; :-::: '-=--=J=:::;::=:Y
- --;:
1200FlC-=-=-=C-=-:;:-::C-=-=::;=====1
:;- G _I__ .l-_ __ J ____
I ---1_
2010.
-; 1000 Q) 500 [IS] Ceballos, S.; Pou, .I.; Gabiola, I.; Villate, .l.L.; Zaragoza, .I.;
Dl Dl
.s 800 .s 400 _1_ ____
1 --1 ____
1 ---l_ Boroyevich, D.; , "Fault-Tolerant Multilevel Converter Topology," 2006
'0 '0 IEEE Int. Symp. Ind. Electron., voL2" pp.1577-1582,July 2006.
> >300 _1__L ____
1 --1 ____
1 ---l_
600 -- _-- --..J [16] Jae-Chul Lee; Tae-Jin Kim; Dae-Wook Kang; Dong-Seok Hyun; , "A
!:--' _0".5 0.2 0.4 0.6 0.8 1.2
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Fig. 13 Vdc (a) and voltage across C1 (b) during reconfiguration period
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0 1a) o 36 118 ) IECON 08 [IEEE 2008 34th Annual Con! Ind Electron}., pp.983-988,
b) C
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Fig. 14 Irn before (a),during (b) and after (c) reconfiguration period

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