ComputerArchitecture:PartIII

FirstSemester2013
DepartmentofComputerScience
FacultyofScience
ChiangMaiUniversity
 Outline
Decoders
Multiplexers
Registers
ShiftRegisters
Binary Counters
BinaryCounters
MemoryUnit

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 Decoders
Adecoderisacombinationalcircuitthat
convertsbinaryinformationfromthencoded
inputstoamaximumof2n uniqueoutputs.
Thedecoderspresentedinthissectionsare
calledntomlinedecoders,wherem<=2
ca ed to e decode s, e e n.

Theirpurposeistogeneratethe2n (orfewer)
binary combinations of the n input variables
binarycombinationsoftheninputvariables.
Adecoderhasninputsandmoutputsandis
alsoreferredtoasannxmdecoder.
l f dt d d

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 3to8linedecoder

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 3to8linedecoder
Thethreedatainputs,A0,A1,andA2,aredecoded
intoeightoutputs,eachoutputrepresentoneof
thecombinationsofthethreebinaryinput
variables.
Aparticularapplicationofthisdecoderisa
pa t cu a app cat o o t s decode s a
binarytooctalconversion.
Commercialdecodersincludeoneormoreenable
Commercial decoders include one or more enable
inputstocontroltheoperationofthecircuit.
ThedecoderisenabledwhenEisequalto1and
Th d d i bl d h E i lt 1 d
disabledwhenEisequalto0.
204231:ComputerOrganizationandArchitecture 5
 Truth Table for 3to8Line Decoder
TruthTablefor3to8LineDecoder
When
WhentheenableinputEisequalto0,alltheoutputsare
the enable input E is equal to 0, all the outputs are
equalto0regardlessofthevaluesoftheothertheredata
inputs.
Thetherexsinthetabledesignatedontcareconditions.
Whentheenableinputisequalto1,thedecoder
p q ,
operatesinanormalfashion.
Foreachpossibleinputcombination,thereareseven
outputsthatareequalto0andonlyonethatisequalto
1.
Theoutputvariablewhosevalueisequalto1represents
theoctalnumberequivalentofthebinarynumberthatis
available in the input data lines
availableintheinputdatalines.
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Truth Table for 3to8Line Decoder
TruthTablefor3to8LineDecoder

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 NANDGateDecoder
SomedecodersareconstructedwithNANDinstead
ofANDgates.
f AND t
ThedecoderisenabledwhenEisequalto0.
Asindicatedbythetruthtable,onlyoneoutputis
equal to 0 at any give time; the other three outputs
equalto0atanygivetime;theotherthreeoutputs
areequalto1.
Theoutputwhosevalueisequalto0representsthe
Th t t h l i lt 0 t th
equivalentbinarynumberininputsA1 andA0.
ThecircuitisdisabledwhenEisequalto1,
regardlessofthevaluesoftheothertwoinputs.
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2to4line decoder with NAND gates
2to4linedecoderwithNANDgates

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 Decoder Expansion
DecoderExpansion
Two
Two2to4linedecodersarecombinedto
2to4line decoders are combined to
achievea3to8linedecoder.
Thetwoleastsignificantbitsoftheinputare
h l f b f h
connectedtobothdecoders.
Themostsignificantbitisconnectedtothe
enable input of one decoder and through an
enableinputofonedecoderandthroughan
invertertotheenableinputoftheotherdecoder.
Itisassumedthateachdecoderisenabledwhen
It is assumed that each decoder is enabled when
itsEinputisequalto1.

204231:ComputerOrganizationandArchitecture 10
 DecoderExpansion
p
WhenEisequalto0,thedecoderisdisabledandall
it
itsoutputsareinthe0level.
t t i th 0 l l
WhenA2 =0,theupperdecoderisenabledandthe
lowerisdisabled.
Theoutputsoftheupperdecodergenerateoutputs
The outputs of the upper decoder generate outputs
D0 throughD3,dependingonthevaluesofA1 andA0.
WhenA
Wh A2 =1,thelowerdecoderisenabledandthe
1 th l d d i bl d d th
upperisdisabled.
Thelowerdecoderoutputgeneratesthebinary
q
equivalentD 4 throughD
g 7.
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A3 8decoderconstructedwith
two2 4decoders

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 Encoder
Anencoderisadigitalcircuitthatperformsthe
inverseoperationofadecoder.
f d d
Anencoderhas2n (orless)inputlinesandn
outputlines.
Theoutputlinesgeneratethebinarycode
p g y
correspondingtotheinputvalue.
Anexampleofandencoderistheoctal
An example of and encoder is the octaltobinary
to binary
encoder.
Ithaseightinputs,oneforeachoftheoctaldigits,
It has eight inputs one for each of the octal digits
andthreeoutputsthegeneratethecorresponding
binary number.
binarynumber.
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Truth Table for OctaltoBinary Encoder
TruthTableforOctaltoBinaryEncoder

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 Encoders
Itisassumedthatonlyoneinputhasavalueof1at
anygiventime;otherwise.,thecircuithasnomeaning.
TheencodercanbeimplementedwithORgates
p g
whoseinputsaredetermineddirectlyfromthetruth
table.
OutputA0 =1iftheinputoctaldigitis1or3or5or7.
Similarconditionsapplyfortheothertwooutputs.
l d l f h h
A0 =D1 +D3 +D5 +D7
A1 =D2 +D3 +D6 +D7
A2 =D
= D4 +D
+ D5 +D
+ D6 +D
+ D7
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 Multiplexers
Amultiplexerisacombinationalcircuitthat
p
receivesbinaryinformationfromoneof2n input
data lines and directs it to a single output line.
datalinesanddirectsittoasingleoutputline.
Theselectionofaparticularinputdatalinefor
the output is determined by a set of selection
theoutputisdeterminedbyasetofselection
inputs.
A2nto1multiplexerhas2n inputdatalinesandn
inputselectionlineswhosebitcombinations
determinewhichinputdataareselectedforthe
output.
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 A 4to1line multiplexer
A4to1linemultiplexer
EachofthefourdatainputsI
p 0 throughI
g 3 is
appliedtooneinputofandANDgate.
ThetwoselectioninputsS
Th t l ti i t S1 andS
d S0 are
decodedtoselectaparticularANDgate.
TheoutputsoftheANDgatesareappliedtoa
single OR gate to provide the single output.
singleORgatetoprovidethesingleoutput.
Amoreconvenientwaytodescribethe
operationofmultiplexersisbymeansofa
i f li l i b f
functiontable.
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4to1 line multiplexer
4to1linemultiplexer

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 FunctionTablefor
4to1LineMultiplexer

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 Registers
Initsbroadestdefinition,aregisterconsistsof
g p p p g
agroupofflipflopsandgatesthateffecttheir
transition.
Theflipflopsholdthebinaryinformationand
The flip flops hold the binary information and
thegatescontrolwhenandhownew
i f
informationistransferredintotheregister.
ti i t f d i t th it

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 4 bit Register
4bitRegister
Slidenumber23showssucharegister
lid b h h i
constructedwithfourDflipflops.
Thecommonclockinputtriggersallflipflops
g g p ,
ontherisingedgeofeachpulse,andthe
binarydataavailableatthefourinputsare
g
transferredintothe4bitregister.
Thefouroutputscanbesampledatanytime
to obtain the binary information stored in the
toobtainthebinaryinformationstoredinthe
register.

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 4 bit Register
4bitRegister
Theclearinputgoestoaspecialterminalin
p p
eachflipflop.
Whenthisinputgoesto0,allflipflopsare
reset asynchronously
resetasynchronously.
Theclearinputisusefulforclearingthe
registertoall0spriortoitsclockedoperation.

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 4bit register
4bitregister

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 Shift Registers
ShiftRegisters
Aregistercapableofshiftingitsbinary
i bl f hif i i bi
informationinoneorbothdirectionsiscalled
ashiftregister.
Thelogicalconfigurationofashiftregister
g g g
consistsofachainofflipflopsincascade,with
p p p
theoutputofoneflipflopconnectedtothe
inputofthenextflipflop.
Allflipflopreceivecommonclockpulsesthat
All flipflop receive common clock pulses that
initiatetheshiftfromonestagetothenext.

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 4bit shift register
4bitshiftregister

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 Binary Counters
BinaryCounters
Acounterthatfollowsthebinarynumber
q y
sequenceiscalledabinarycounter.
Annbitbinarycounterisaregisterofnflip
flops and associated gates that follows a
flopsandassociatedgatesthatfollowsa
sequenceofstatedaccordingtothebinary
countofnbits,from0to2
f b f n1.

204231:ComputerOrganizationandArchitecture 26
 Binary Counter
BinaryCounter
Goingthroughasequenceofbinarynumbers
suchas0000,0001,0010,0011,andsoon,we
notethatthelowerorderbitis
complemented after every count and every
complementedaftereverycountandevery
otherbitiscomplementedfromonecountto
the next if and only if all its lower order bits
thenextifandonlyifallitslowerorderbits
areequalto1.

204231:ComputerOrganizationandArchitecture 27
 Binary Counter
BinaryCounter
RememberthataJKflipflopiscomplemented
b h fli fl i l d
ifbothitsJandKinputsare1andtheclock
goesthroughapositivetransition.
TheoutputoftheflipflopdoesnotchangeifJ
p p p g
=K=0.
Inaddition,thecountermaybecontrolled
In addition the counter may be controlled
withanenableinputthatturnsthecounteron
or off without removing the clock signal from
oroffwithoutremovingtheclocksignalfrom
theflipflops.

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4bit synchronous binary counter
4bitsynchronousbinarycounter

204231:ComputerOrganizationandArchitecture 29
 Random Access Memory
RandomAccessMemory
Thendatainputlinesprovidetheinformation
h d i li id h i f i
tobestoredinmemory,andthendataoutput
linessupplytheinformationcomingoutof
memory.
Thekaddresslinesprovideabinarynumber
p y p
ofkbitsthatspecifyaparticularwordchosen
amongthe2k availableinsidethememory.
Thetwocontrolinputsspecifythedirectionof
The two control inputs specify the direction of
transferdesired.

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 Blockdiagramof
randomaccessmemory(RAM)

204231:ComputerOrganizationandArchitecture 31
 Transferringanewwordtobestored
intomemory
1. Applythebinaryaddressofthedesiredword
intotheaddresslines.
2. Applythedatabitsthatmustbestoredin
memory into the data input lines
memoryintothedatainputlines.
3. Activatethewrite input.

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 Transferringastoredword
outofmemory
1. Applythebinaryaddressofthedesiredword
intotheaddresslines.
2. Activatetheread input.

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 Read Only Memory
ReadOnlyMemory
AnmxnROMisanarrayofbinarycells
i f bi ll
organizedintomwordsofnbitseach.
AROMhaskaddressinputlinestoselectone
of2k =mwordsofmemory,andnoutput
y, p
lines,oneforeachbitoftheword.
TheROMdoesnotneedaread
The ROM does not need a readcontrol
controlline
line
sinceatanygiventime,theoutputlines
automatically provide the n bits of the word
automaticallyprovidethenbitsoftheword
selectedbytheaddressvalue.

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 Blockdiagramof
readonlymemory(ROM)

204231:ComputerOrganizationandArchitecture 35
 Reference
M.Moris Mano,ComputerSystem
Architecture,3rd ed.NJ:PrenticeHall,1992.

204231:ComputerOrganizationandArchitecture 36