IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO.
4, AUGUST 2002
Performance Analysis of an ADC Histogram Test
Using Small Triangular Waves
Francisco Alegria, Pasquale Arpaia, António M. da Cruz Serra, and Pasquale Daponte
Abstract—The histogram method using small-amplitude trian-
gular waves for the quasi-static test of analog-to-digital converters
has been proposed for standardization aims. In this paper, after
a brief description of the test procedure, analytical closed-form
relations for designing the test, as well as for its characterization
in terms of efficiency and uncertainty, are provided. Numerical
and experimental results of a comparative analysis with the IEEE
1057-standard static test highlight its better performance in terms
of efficiency and accuracy.
Index Terms—ADC testing, histogram method, small/waves,
static test, triangular waves.
I. INTRODUCTION
I N standard static testing of analog-to-digital converters
(ADCs), code transition levels are determined according
to a step-wise statistical algorithm [1]. The necessity for each
transition level of about five input changes, and, for each of
them, of a significant calibrator settling time, makes the test
duration prohibitive for high-resolution ADCs.
Possible solutions are to reduce the number of transition
levels or applied voltage changes. In the former case, a
model-based approach allows all-codes transition levels to
be computed [2] for the servo-loop test [3], [4]. In the latter
case, a method based on a variable step size calculated with
an extrapolated convergence factor technique was proposed
[5]. A further histogram-based alternative approach [6] using
small-amplitude triangular waves, capable of reducing the
test duration more significantly, has been proposed [7], [8].
The converter input range is stimulated by small-amplitude
triangular waves superimposed to a progressively increased dc
level. The test allows linearity constraints of function genera-
tors to be relaxed and the experimental burden to be reduced.
Although from preliminary experiments the test duration
appeared to decrease remarkably, a systematic investigation of
its performance was still necessary.
In this paper, a comprehensive analytical characterization of
test efficiency and accuracy is carried out. In Section II, after
a brief description of the basic idea underlying the proposed
method, the test procedure is illustrated. In Section III, analyt-
ical relations for designing the test are provided. In Sections IV
Manuscript received May 29, 2001; revised April 23, 2002.
F. Alegria and A. M. da Cruz Serra are with the Telecommunication
Institute and Instituto Superior Técnico, Technical University of Lisbon,
Lisbon, Portugal (e-mail: falegria@lx.it.pt; acserra@alfa.ist.utl.pt; WWW:
http://www.lx.it.pt/falegria).
P. Arpaia and P. Daponte are with the Dipartimento di Ingegneria,
Università del Sannio, Benevento, Italy (e-mail: arpaia@unisannio.it;
daponte@unisannio.it, http://lesim1.ing.unisannio.it).
Digital Object Identifier 10.1109/TIM.2002.803292
0018-9456/02$17.00 © 2002 IEEE
723
and V, efficiency and uncertainty of the test are analyzed. Fi-
nally, in Section VI, experimental results aimed at comparing
the proposed technique with the IEEE 1057/94 standard static
test [1] are presented.
II. THE PROPOSED TEST
The basic idea lies on the use of small-amplitude triangular
waves, superimposed to increasing dc offset levels, as a test
signal, and on the use of the histogram procedure [6]–[8]. The
input range is scanned by progressively increasing the offset
level step by step (Fig. 1). Small amplitude and slope in
comparison to the converter range and slew rate, respectively,
lead to quasi-static test conditions.
The histogram procedure [1], [3], [9]–[11] is adopted in order
to reduce the sample number and the test duration in compar-
ison to the standard static test [1]. The number of samples to be
acquired for the same uncertainty is much lower than the tradi-
tional static test. Furthermore, the number of changes in the dc
level of the calibrator is reduced by several orders of magnitude.
Consequently, the test duration will be greatly reduced owing to
the corresponding decrease of the total waiting time for the cal-
ibrator settling.
A calibrating linear signal (triangular wave) is used for
achieving a uniform stimulus condition over the ADC range
[11]–[13]. Conversely, the standard histogram test exploits a
sinusoidal stimulus signal, because it is easier to generate with
sufficiently low distortion than a triangular one [1], [9]. In the
proposed test, the constraint on the linearity distortion of the
triangular generator is relaxed by using a signal of amplitude
much lower than the ADC full scale. The input range is stimu-
lated entirely by acquiring the samples for the histogram in
steps, with the same small-amplitude triangular wave, but with
different offset levels (Fig. 1).
The procedure of the proposed test is reported in Fig. 2.
First, the instruments are set. In each of the steps, the
ADC acquires records of samples of the small wave
with amplitude [8]. The sampling frequency and the
small-wave frequency are selected according to the standard
histogram procedure [1]. The data acquisition is repeated
times for values of the offset successively increasing. From
the samples acquired in each step, a cumulative histogram
is built [11]. All the transition levels for each step are
computed from the cumulative histogram [7], [8]. An example
is presented in Fig. 3 for a five-bit ADC and a test with four
steps.
After all the steps, the obtained transition level arrays have
to be combined into a single one. However, the need for over-
drive [8], [11] in each of the steps, and the inaccuracy of the
724 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO. 4, AUGUST 2002

Fig. 3. Representation of the cumulative histograms (different gray levels)

computed in each step for a five-bit converter and a four-step test.

III. PROCEDURE DESIGN

In the test design, the values of its main parameters have
to be defined: i) the amplitude of the small wave, ii) the
offset in the -th step, iii) the number of samples in
each record, and iv) the frequency of the small wave. In the
following, analytical relations for selecting these parameters
are provided.

A. Small-Wave Amplitude
The amplitude of the small wave i) has to be sufficiently
small, in order to permit a low linearity for the function gen-
Fig. 1. Signals applied to the ADC.
erator, and ii) has to include an overdrive, in order to increase
accuracy and to stimulate all the codes in the th step.
As far as the linearity requirement is concerned, the non-
linearity NL of a triangular generator can be defined as the
maximum difference between the actual and the ideal waves,
normalized to the ideal wave amplitude. This NL causes an
error on the measured transition level. Once a maximum value
is defined for this error, by considering the -bit ADC
resolution, a corresponding boundary for the wave amplitude
can be obtained

(1)

where is the ADC reduced full-scale

voltage [11].
As far as the overdrive is concerned, analogous to the tradi-
tional sinusoidal histogram test [11], the overdrive necessary for
the proposed test is derived

(2)

where is expressed in least significant bit (LSB), is the

standard deviation of the input-equivalent noise, and the ideal
Fig. 2. Proposed test procedure.
code bin width.
On this basis, the amplitude of the small wave can be obtained
stimulus signal, give rise to some transition levels having two as equal to half of the range stimulated in each step , plus
values computed in two successive steps (Fig. 3). The value far- the amount of overdrive
ther from the step limit is selected, since the triangular wave is
more distorted near the peaks owing to the discontinuity of the
derivative [8]. (3)
ALEGRIA et al.: PERFORMANCE ANALYSIS OF AN ADC HISTOGRAM TEST USING SMALL TRIANGULAR WAVES 725

The maximum value of is , and random phase shift between the test signal and the
sampling clock. The minimum number of records to achieve a
(4) given uncertainty boundary on the transition levels for the
sinusoidal histogram can be determined [15]
For equal steps, the number of steps results

(5)
(11)
where the symbol denotes the integer part of . Conse-
quently, the exact range to be stimulated in each step is where is the confidence level and is the percentage of
overdrive used. Equation (11) has to be adapted to the case of a
(6) triangular stimulus by substituting the coefficient
by the corresponding . Moreover, in [11], the test signal am-
plitude was considered to be equal to half of the reduced full
Note that, since must be an integer number, the range
scale, times the overdrive . Here, the case of the amplitude
stimulated by each step will be, generally, smaller than the limit
lower than the full-scale voltage is considered
.

B. Offset
The offset to apply in the -th step is just the middle point (12)
of the stimulated range
IV. EFFICIENCY ANALYSIS
(7)
In this section, the proposed test efficiency in terms of time
duration is investigated analytically and compared to the one
where is the lowest transition level.
of the standard static test, at varying main test parameters: i)
C. Number of Samples number of bits, ii) input equivalent noise, iii) phase noise, and
iv) required uncertainty. With this aim, at first analytical expres-
The number of samples has to be i) sufficiently low in sions of are derived for both the tests, and the analysis con-
order to limit the influence of the uncertainty of the input and ditions are defined.
sampling frequencies, and ii) sufficiently high, in order to limit For the proposed test, depends on the step number , and
the influence of random noise. on the time taken by each step
As far as the first uncertainty source is concerned, a higher
boundary for has to be determined. depends
on the input frequency , the sampling frequency , and their (13)
accuracies and . The following expression sets a boundary
for the relative error of the ratio between these two where is the generator settling time, and the communi-
frequencies [14] cation time accounting for the time taken by a sample code to
be transferred from the ADC output to the computer memory.
(8) For the standard static test, depends on: the ADC number
of transition levels , the number of input voltages
where is the acquired number of signal periods. From (8), by used for each transition level determination, and the time nec-
substituting the explicit expression of , the maximum number essary for the acquisition [1]
of samples is derived:

(14)
(9)
The efficiency comparative analysis was carried out in the fol-
Since this test should be performed in quasi-static conditions, lowing conditions: i) a reduced full-scale voltage of 1 V; ii)
the acquisition should be performed during only one period of an accuracy of 0.001 LSB on the measured transition levels;
the stimulus signal . The frequency of the test signal iii) a small-wave frequency of 10 Hz; iv) a sampling frequency
can thus be calculated as of 10 Sample/s; v) accuracies and of ppm; vi)
a communication time of 100 s per sample; vii) a settling
(10) time of 0.1 s; viii) number equal to five input levels
for the determination of each transition level, as required on av-
As far as the second uncertainty source is concerned, three main erage by the standard static test [1]; and ix) a sample number
factors have to be considered for the transition levels derived , derived from [1] for a confidence
from the cumulative histogram: additive noise , phase noise level equal to .
726 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO. 4, AUGUST 2002
Fig. 4. Test duration t versus ADC bit number n , for the standard (thin line)
and the proposed test (solid thick line: 1 step, dashed line: 100 steps).
In the following, the influence on of i) the number of bits
, ii) the input-equivalent noise standard deviation , iii) the
phase noise standard deviation , and iv) the required uncer-
tainty is analyzed for both the tests.
A. Number of Bits
For the analysis on the ADC number of bits , and
were set to 1 LSB and rad, respectively, and a required
uncertainty of LSB was defined.
In Fig. 4, the durations of the two tests are compared when
varying . The semi-logarithmic scale highlights their quasi-
exponential trend. In particular, the duration of the standard
static test doubles with each added bit according to (14), and
becomes prohibitive for high-resolution converters . The analysis of the influence of the required uncertainty
The duration of the proposed test is generally 10 times lower
than that of the standard test. Furthermore, in Fig. 4, also the
impact of the step number on the proposed test duration is
highlighted by reporting the extreme cases of 1 (full-scale trian-
gular wave) and 100 steps (ADC input range divided into 100
steps).
B. Input-Equivalent Noise
The analysis on the input equivalent noise was carried out on
a 12-bit ADC with a phase-noise standard deviation of
rad, and a required uncertainty of LSB. In Fig. 5,
the durations of the two tests are compared when varying the
input-equivalent noise standard deviation . The duration of
the static test depends on for the required number of samples.
In the case of the proposed test, the dependence is almost
linear according to (12). Also, in this case, the duration of
the proposed test is much lower than the standard one. The
increasing impact of the step number on the proposed test
duration is highlighted in Fig. 5 (also in this case for only 1
triangular wave and for 100 small-amplitude triangular waves).
C. Phase Noise
The analysis of the phase noise influence on the test dura-
tion was carried out for a 12-bit ADC, with 2 mV input-equiva-
lent noise standard deviation, and a required uncertainty of
Fig. 5. Test duration t versus input-equivalent noise standard deviation  ,
for the standard (thin line) and the proposed test (solid thick line: 1 step, dashed
line: 100 steps).
LSB. Of course, the duration of the standard test is independent
of the phase noise, and for the above conditions of analysis, is
equal to 1.33 h. The duration trend of the proposed test with
the phase-noise standard deviation is represented in Fig. 6. The
dependence is linear, and again the impact of the step number
on the proposed test duration can be high-lighted. Also, in this
case, the duration of the proposed test is much lower than the
standard one.
D. Required Uncertainty
for the transition levels on the test duration was carried out for a
12-bit ADC, with 2 mV input-equivalent noise standard devia-
tion, and phase noise with rad of standard deviation. In
Fig. 7, the durations of the two tests are compared when varying
the required uncertainty. In particular, for both the tests, the du-
ration decreases according to the required uncertainty, but it is
always much lower for the proposed test.
V. UNCERTAINTY ANALYSIS
In this section, the uncertainty of the transition levels of
the two methods are compared for the case of one-hour test dura-
tion. With this aim, the analytical expressions of the uncertainty
are derived, and then the influences of the ADC bit number, and
of the input equivalent, are studied.
In the standard static test, the uncertainty on the transition
voltages is given by [1]
(15)
The number of samples leading to a given duration of the test
is determined from (14)
(16)
ALEGRIA et al.: PERFORMANCE ANALYSIS OF AN ADC HISTOGRAM TEST USING SMALL TRIANGULAR WAVES
Fig. 6. Test duration t versus phase-noise standard deviation
proposed test (solid line: 1 step, dashed line: 100 steps).
Fig. 7. Test duration t versus required uncertainty B , for the standard (thin
line) and the proposed test (thick line).
In the proposed test, from (12) the uncertainty of the transition
levels is
where is determined from (13)
A. Number of Bits
In Fig. 8, the uncertainty as a function of the number of
bits is plotted for a one-hour test duration. The proposed
test (thick line) is always more accurate than the standard test
(thin line). The uncertainty of the standard test is not plotted for
more than 12 bits because the test takes more than 1 h, even for
an infinite uncertainty. In the proposed test, the uncertainty is
smaller for a lower number of steps in the case of a low number
of bits.
727
 . for the Fig. 8. Uncertainty limit of the transition levels (B ) as a function of the ADC
number of bits n .: standard test (thin line) and proposed test (1 step: thick solid
line; 100 steps: thick dashed line).
Fig. 9. Uncertainty limit of the transition levels (B ) as a function of the
standard deviation of the input-equivalent noise in least-significant bit units
(LSB): Standard test (thin line): proposed test with 1 step (thick solid line) and
100 steps (thick dashed line).
B. Input-Equivalent Noise
In Fig. 9, the uncertainty is plotted as a function of the
(17)
input-equivalent noise standard deviation for both tests.
Also, here, the uncertainty of the transition levels obtained
with the standard test is greater. Furthermore, the uncertainty is
greater the higher the number of steps used.
(18) VI. EXPERIMENTAL RESULTS
The proposed and the standard tests were already compared in
experimental conditions [7], [8]. In this paper, for the sake of the
completeness, examples of new experiments specifically aimed
at i) validating the proposed test and ii) verifying its efficiency
are reported.
A triangular function generator with a nonlinearity of 0.17%
was used. The following examples were performed in the ex-
perimental conditions of Tables I and II, for the standard and
the proposed test, respectively. The input equivalent noise was
measured according to [1].
A 12-bit PC data acquisition board (Keithley DAS1601) was
used to obtain the experimental results. The board was tested in
728 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 51, NO. 4, AUGUST 2002
TABLE I
STANDARD TEST
TABLE II
PROPOSED TEST
Fig. 10. INL for the proposed test using 80 steps (solid line) and with the
standard test (dotted line).
the V range at its maximum sampling frequency of 100 k
Sample/s. In this range, is 1 s.
A. Validation
Fig. 10 shows the INL obtained by the standard (dotted
line) and the proposed (solid line) tests. (An inset plot shows
the INL detail.) Fig. 11 shows the differences in the
results obtained by using the proposed and the standard static
test. The results of the proposed test have an uncertainty of
0.05 LSB, which is sufficient for the obtained worst-case INL
value (0.46 LSB).
The uncertainty of the INL results obtained by the standard
and the proposed tests will produce an uncertainty in the differ-
ence array . This is the main source of mismatch between
the results of the two tests in Fig. 11.
B. Efficiency Comparison
Table III shows the large reduction on the number of acquired
samples and on the duration of the proposed test, in comparison
with the standard test. The inaccuracy of the results can be fur-
ther reduced by using more steps, and, eventually, more over-
drive, in order to approximate the accuracy of the standard test,
still with great improvements in test duration.
VII. CONCLUSION
In this paper, the performance analysis of a quasi-static
histogram test, based on small triangular waves, was presented.
Fig. 11. Difference 1INL between the INL obtained by the proposed (80
steps) and the standard test.
TABLE III
EFFICIENCY COMPARISON
Relations for designing the proposed test and for analyzing
its efficiency and uncertainty performance were provided with
standardization purposes.
Numerical and experimental simulation results for character-
izing the efficiency of the proposed test, and for comparing it
with the standard test were presented. They show that the new
technique can perform the test in a small time fraction of the
standard one for the same uncertainty level, by using inexpen-
sive function generators. The linearity constraint of the gener-
ator is relaxed by exploiting triangular test signals ranging only
a small fraction of the ADC full-scale.
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Pasquale Arpaia, photograph and biography not available at the time of
publication.
António M. da Cruz Serra, photograph and biography not available at the time
of publication.

Francisco Alegria, photograph and biography not available at the time of Pasquale Daponte, photograph and biography not available at the time of
publication. publication.