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Bob York
Load-Line and Q-point
Increasing Vgs
Vdd 1 Larger
Id Vout Id Vds
Rd Rd Rd Vgs= Vtn + 1.5
The points of intersection represent the allowed device voltages and drain current for the
resistor-FET combination. These are the quiescent operating conditions or Q points, i.e.
the DC bias conditions.
There are a number of possible Q-points along the load-line, depending on the gate voltage. It
is the job of the circuit designer to choose this Q-point.
The choice of Q-point will vary with the circuit application. For simple amplifier circuits a Q-
point in the middle of the saturation region is often desirable.
With a plot of the FET I-V curves we can quickly tell at a glance whether the Q-point is in the
saturation or ohmic region. Without the visual plot we could make an initial guess and then
check to see whether the answer is consistent with this assumption:
The previous design example required two DC sources: a drain supply (+10V)
and a gate supply (+3V)
A simpler solution for enhancement-mode devices is to use just a single supply
at the drain and generate the required gate voltage using a resistor divider:
+10 V
200
+10 V
Voltage divider
to set the gate +6 V Remember: no current flows
voltage required 700 k into the gate. This simplifies
for a certain Id the design and analysis of
20 mA
+3 V the gate bias circuit
300 k
In discrete circuits the gate bias resistors usually have large values. You will
learn why in ECE 2C when we discuss AC amplifiers.
In Integrated Circuit (IC) designs, large resistors take up too much space and
a different approach is taken. We will explore this later.
Increasing
determined from load-line:
Vd
Vdd I d ( Rd Rs ) Vds
Vgs
Ig = 0
Vg Vds
Vdd Vds
Rd Rs
Vgs Vs
Id Vdd Vds
Rg2
RS Often there will be constraints on Rd or Rs imposed by
the application. If Vd or Vs is specified, then
Vdd Vd Vs
Rd or Rs
Id Id
Once Rs and Rd are known we can design the gate bias Id
network. Required Vgs determined from I-V curves. In saturation: Vgs Vt
Kn
Then gate voltage and voltage-divider can be designed according to:
Rg 2 Always double-check that
Vg Vgs I d Rs Vdd Vgs I d Rs the design is consistent
Rg1 Rg 2 with assumptions!
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FET Bias Building Blocks
Vdd
A FET with drain and gate connected is a common building
block in IC bias networks
Rd
This connection forces the device into saturation such that
Vdd Vout Vout Vgs Vds
I d K n Vout Vt Id
2
Rd
W /L
Common design problems:
Find the Rd that gives a specified Vout or Id
Rd
1
or Rd
Vdd Vt 1 manipulated to vary Kn:
K n Vout Vt Id Kn Id 1 W
K n kn
2 L
Find the Vout or Id for a given Rd
1
Vout Vt 1 4 K n Rd (Vdd Vt ) 1
2 K n Rd
Vdd Vt 1
Id 2
1 1 4 K n Rd (Vdd Vt )
Rd 2 K n Rd
Bob York Back to TOC
Some Examples with Drain-Gate Connection
+5 V +5 V +5 V
4 mA 3 k
Vout Vout
Vout Vout
4 mA 3 k
Assume:
Vt 1V
+5 V +5 V K 1mA/V 2 +5 V
4 mA 3 k
Vout Vout
Vout Vout
4 mA 3 k
-5 V -5 V -5 V
Bob York Back to TOC