19/1/2017 EmbeddedSystemsArchitectureTypes

EmbeddedSystemsArchitectureTypes
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The8051microcontrollersworkwith8bitdatabus.Sotheycansupportexternaldatamemoryupto64Kand
externalprogrammemoryof64katbest.Collectively,8051microcontrollerscanaddress128kofexternal
memory.

Whendataandcodelieindifferentmemoryblocks,thenthearchitectureisreferredasHarvardarchitecture.
Incasedataandcodelieinthesamememoryblock,thenthearchitectureisreferredasVonNeumann
architecture.

VonNeumannArchitecture
TheVonNeumannarchitecturewasfirstproposedbyacomputerscientistJohnvonNeumann.Inthis
architecture,onedatapathorbusexistsforbothinstructionanddata.Asaresult,theCPUdoesoneoperationat
atime.Iteitherfetchesaninstructionfrommemory,orperformsread/writeoperationondata.Soaninstruction
fetchandadataoperationcannotoccursimultaneously,sharingacommonbus.

VonNeumannarchitecturesupportssimplehardware.Itallowstheuseofasingle,sequentialmemory.Today's
processingspeedsvastlyoutpacememoryaccesstimes,andweemployaveryfastbutsmallamountof
memorycachelocaltotheprocessor.

HarvardArchitecture

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TheHarvardarchitectureoffersseparatestorageandsignalbusesforinstructionsanddata.Thisarchitecturehas
datastorageentirelycontainedwithintheCPU,andthereisnoaccesstotheinstructionstorageasdata.
Computershaveseparatememoryareasforprograminstructionsanddatausinginternaldatabuses,allowing
simultaneousaccesstobothinstructionsanddata.

Programsneededtobeloadedbyanoperatortheprocessorcouldnotbootitself.InaHarvardarchitecture,
thereisnoneedtomakethetwomemoriesshareproperties.

VonNeumannArchitecturevsHarvardArchitecture
ThefollowingpointsdistinguishtheVonNeumannArchitecturefromtheHarvardArchitecture.

VonNeumannArchitecture HarvardArchitecture
Singlememorytobesharedbybothcodeanddata. Separatememoriesforcodeanddata.
Processorneedstofetchcodeinaseparateclockcycleanddata Singleclockcycleissufficient,asseparate
inanotherclockcycle.Soitrequirestwoclockcycles. busesareusedtoaccesscodeanddata.
Higherspeed,thuslesstimeconsuming. Slowerinspeed,thusmoretimeconsuming.
Simpleindesign. Complexindesign.

CISCandRISC
CISCisaComplexInstructionSetComputer.Itisacomputerthatcanaddressalargenumberofinstructions.

Intheearly1980s,computerdesignersrecommendedthatcomputersshouldusefewerinstructionswithsimple
constructssothattheycanbeexecutedmuchfasterwithintheCPUwithouthavingtousememory.Such
computersareclassifiedasReducedInstructionSetComputerorRISC.

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CISCvsRISC

ThefollowingpointsdifferentiateaCISCfromaRISC

CISC RISC
Largersetofinstructions.Easytoprogram SmallersetofInstructions.Difficulttoprogram.
Simplerdesignofcompiler,consideringlargersetof
Complexdesignofcompiler.
instructions.
Manyaddressingmodescausingcomplexinstruction
Fewaddressingmodes,fixinstructionformat.
formats.
Instructionlengthisvariable. Instructionlengthvaries.
Higherclockcyclespersecond. Lowclockcyclepersecond.
Emphasisisonhardware. Emphasisisonsoftware.
Controlunitimplementslargeinstructionsetusing
Eachinstructionistobeexecutedbyhardware.
microprogramunit.
Slowerexecution,asinstructionsaretobereadfrom Fasterexecution,aseachinstructionistobeexecuted
memoryanddecodedbythedecoderunit. byhardware.
Pipeliningofinstructionsispossible,considering
Pipeliningisnotpossible.
singleclockcycle.

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