EL2095 Digital System

Sequential Logic (CH8 Analysis SM)

Sekolah Teknik Elektro dan Informatika
Institut Teknologi Bandung
The Sequential Circuit Model
x1
Combinational
z1 Sequential Circuit has
xn logic zm memory elements
(a) It remembers the
x1 z1 present state (y1..yr)
xn Combinational
logic
zm
Uses the present state
to determine the next
y1 yr Yr Y1 state (Y1..Yr)
A state transition is
Memory defined as
(b)
Y = h(x, y)
The output is defined as
Z = g(x, y)
The Synchronous Sequential Circuit Model

x1 z1

...

...
xn Combinational zm
logic

y1 ... yr Yr ... Y1

Memory

Clock

Transition depends on Clock

General Architecture of Synchronous
State Machines
Moore machine outputs depend only on the state
Mealy machine outputs depend on the state and the
current inputs

M P
W Combinational N Combinational
circuit Z
circuit :

next state output logic

(excitation) logic N Flip-flops
Clock state
Mealy Machine Model

A
1/1 1/0
0/1
0/0 0/0 1/0
B C
X/Z
(a)

Present Input x
state 0 1
A B/1 C/0
B B/0 A/1
C A/0 C/0 z = f(x,y)
Next state/output
(b)
Mealy Machine Timing Diagram
A T0 T1 T2 T3 T4 T5
1/1 1/0
Clock
0/1
0/0 0/0 1/0 B A A
B C State A C A C

X/Z Input x 0 1 1 0 1 0
(a)
Output z 1 1 0 0 0 0
Present Input x
state 0 1
A B/1 C/0
B B/0 A/1
C A/0 C/0
Next state/output
(b)
Moore Machine Model

0
1
W/0 X/1

0 0
1 1
Y/0

(a)

Present Input x
state 0 1 Outputs
W Y X 0
X X Y 1 z = f(y)
Y X W 0

(b)
Moore Machine Timing Diagram
0
1
W/0 X/1
T0 T1 T2 T3 T4 T5
0 0
Clock
1 1
State W Y W X X Y X
Y/0
Input x 0 1 1 0 1 0
(a) Output z 0 0 0 1 1 0

Present Input x
state 0 1 Outputs
W Y X 0
X X Y 1
Y X W 0

(b)
State Machine Analysis Steps
1. Determine excitation eqns for flip-flop inputs
2. Substitute excitation eqns into flip-flop Characteristic
Equations
characteristic eqns to obtain transition eqns
3. Use transition eqns to create a transition table SR flip-flop
Q* = S + RQ
4. Determine output eqns
5. Add output values to the transition table for D flip-flop
each state (Moore) or state/input combination Q* = D
(Mealy) T flip-flop
6. Name the states, create a state/output table Q* = TQ + TQ
7. Draw a state diagram JK flip-flop
Q* = JQ + KQ
SR Master-Slave Flip-Flop Characteristics
S R Q C Q*
0 0 0 0 No change
0d SR d0
0 0 1 1
0 1 0 0 Reset 10
0 1 1 0 0 1
1 0 0 1 Set 01
1 0 1 1
State Diagram
1 1 0 x Not allowed
1 1 1 x
Excitation Table

Characteristic Equation
Q* = S + RQ
The same as SR Latch but changes only takes
effect during clock pulse
Master-Slave D Flip-Flop Characteristics
D Q C Q*
0 0 0 Store 0
0 D 1
0 1 0
1 0 1 Store 1 1
1 1 1 0 1

Excitation Table 0
State Diagram
Characteristic Equation
Q* = D
Enabled: M S M S M S M S M

QM

Q = QS

Timing Diagram
Pulse-Triggered JK Flip-Flop Characteristics
0d JK d0
1d
J K Q C Q* 0 1
d1
0 0 0 0 Hold
0 0 1 1 State Diagram
0 1 0 0 Reset JK J
0 1 1 0
Q 00 01 11 10
1 0 0 1 Set
1 0 1 1 0 0 0 1 1
1 1 0 1 Toggle
1 1 1 0
Q 1 1 0 0 1
Excitation Table

Characteristic Equation K
Q* = KQ + JQ K-map for Q*
Example 1

wy1 + wy2
D1 y1
D Q
z

Q y1 y2
w

wy1 + wy2
D2 y2
D Q

Clock Q

Resetn
Example 1 (continued)

1. Excitation equations for flip-flop inputs:

D1 = w y1 + w y2
D2 = w y1 + w y2

2. Transition equations:
Y1 = w y1 + w y2 Present Next State
State w=0 w=1
Y2 = w y1 + w y2
y2 y1 Y2 Y1 Y2 Y1
0 0 0 0 0 1
3. Transition table:
0 1 0 0 1 0
1 0 0 0 1 1
1 1 0 0 1 1
 Example 1 (continued)
Present Next State
4. Output equations: State w=0 w=1
Output
z = y1 y2
y2 y1 Y2 Y1 Y2 Y1 Z
0 0 0 0 0 1 0
5. Transition/output table: 0 1 0 0 1 0 0
1 0 0 0 1 1 0
6. Name states: 1 1 0 0 1 1 1

y2 y1 State
0 0 A
0 1 B
1 0 C
1 1 D
 Example 1 (continued)
Present Next State Output
State/output table: State w=0 w=1 Z
A A B 0
B A C 0
C A D 0
D A D 1
State diagram:

w=0 w=1
w=1

w=1 w=1 D
A B C
w=0
(z=1)
w=0 w=0
 Timing Diagram

CLK

y1

y2

A A B C D D A
Example 2

D1 y1
D Q
z

Clock Q

X D2 y2
D Q

Clock Q
Example 2 (continued)
Present Next State
1. Excitation equations for flip-flop State x=0 x=1
inputs: D1= y1+ y2 y2 y1 Y2 Y1 Y2 Y1
D2= xy2 0 0 0 1 1 1
2. Transition equations: 0 1 0 0 1 0
Y1= y1+ y2 1 0 0 1 0 1
Y2= xy2 1 1 0 1 0 1
3. Transition table:
Present Next State
Output
State x=0 x=1
4. Output equations: y2 y1 Y2 Y1 Y2 Y1 z
z = y1+y2 0 0 0 1 1 1 1
5. Transition/output table: 0 1 0 0 1 0 1
1 0 0 1 0 1 0
1 1 0 1 0 1 1
Example 2 (continued)
Present Next State Output
6. Define states, create State x=0 x=1 z
state/output table A B D 1
B A C 1
C B B 0
D B B 1
7. State diagram
A X=0
B
z =1 X=0 z =1

X =1 X=1

D C
z =1 z =0
 Timing diagram for Example 2

CLK

y1

y2

Z
A B C B A
Example 3
Combinational logic
Dt
z

D
x

C

Q
y Y
Q D
Q
y
Q C Clock 0 1 2 3 4 t/Dt
(b)
Memory
(a)
Example 3 (continued)
Present Next State
1. Excitation equations for flip-flop State x=0 x=1
inputs: D = xy + xy y Y Y
0 0 1
2. Transition equations: 1 1 0
Y = xy + xy

3. Transition table:
Next
Present State/Output
State
4. Output equations: x=0 x=1
z = xy y Y Y
5. Transition/output table: 0 0/0 1/0
1 1/0 0/1
Timing Diagram

Clock

x 0 1 1 0 1 0 0 0

y 0 0 1 0 0 1 1 1

Y=D 0 1 0 0 1 1 1 1

z 0 0 1 0 0 0 0 0
0 1 2 3 4 5 6 7 8 t/Dt
Glitch
Example 4

Q1Q2 T1 Q1
T Q
z
Q1Q2
Clock Q

X
XQ2 T2 Q2
T Q

Clock Q Q* = T Q + T Q
Example 4 (continued)
Excitation equations for flip-flop inputs:
T1 = Q1 Q2
T2 = X Q2
Transition equations:
For a T F/F: Q* = T Q + T Q
Q1* = T1 Q1 + T1 Q1
= (Q1 Q2) Q1 + (Q1 Q2) Q1 = Q1 Q2 + (Q1 + Q2) Q1
= Q1 Q2 + Q1
= Q1 + Q2
Q2* = T2 Q2 + T2 Q2
= X Q2 Q2 + (X Q2) Q2 = X Q2 + (X + Q2) Q2 = X Q2 + Q2
= X + Q2
Example 4 (continued) Next State
Present
Transition table: State x=0 x=1
Q2 Q1 Q*2 Q*1 Q*2 Q*1
0 0 0 0 1 0
0 1 0 1 1 1
1 0 1 1 1 1
1 1 1 1 1 1

Output equations: Z = Q1 Q2
Present Next State
Output
State x=0 x=1
Transition/output table:
Q2 Q1 Q*2 Q*1 Q*2 Q*1 z
0 0 0 0 1 0 0
0 1 0 1 1 1 0
1 0 1 1 1 1 0
1 1 1 1 1 1 1
Example 4 (continued)
Present Next State Output
6. Define states, create State x=0 x=1 Z
state/output table S0 S0 S2 0
S1 S1 S3 0
S2 S3 S3 0
S3 S3 S3 1
7. State diagram
reset

X X 1 S3 X
S0 S2 z=1
S1 X

1
Cant ever get
This machine waits until a 1 is input it then to state S1
waits one cycle and then outputs a 1 forever
Example 5
Mealy Machine
X

Y T Q T Q
Q1 Q2
z
Q Q

Clk z = XQ2
T1 = Y =
Q*
1 YQ1 + YQ1
T2 = XYQ1 =Q2* XYQ1Q2 + ( XYQ1 )Q2

Q=
*
TQ + TQ
Example 5
Present Next State Q*2Q*1,z
State XY
Q2 Q1 00 01 10 11
0 0 00,1 01,1 00,0 01,0
0 1 11,1 00,1 01,0 00,0
1 0 10,0 11,0 10,0 11,0
1 1 01,0 10,0 11,0 10,0

Present Next State Q*2Q*1,z

State XY
00 01 10 11
A A,1 B,1 A,0 B,0
B D,1 A,1 B,0 A,0
C C,0 D,0 C,0 D,0
D B,0 C,0 D,0 C,0
Example 5
Present Next State Q*2Q*1,z
Y (Z=1)
State XY
00 01 10 11

A Y A A,1 B,1 A,0 B,0

B D,1 A,1 B,0 A,0
XY
XY C C C,0 D,0 C,0 D,0
(Z=1)
Y D B,0 C,0 D,0 C,0

XY
(Z=1)
XY Y

Note: Z=0 on all transitions

B except where indicated
X Y D otherwise

X Y
X Y
XY (Z=1)
Example 6

Q0
D Q D0 = Q2 D1 = Q0 D2 = Q1
Since Q* = D for a D flip-flop, we get
Clk Q Q0* = Q2 Q1* = Q0 Q2* = Q1

Q1 Q2 Q1 Q0 Q2* Q1* Q0*

D Q
000 001

Clk 001 011

Q
010 101
011 111
Q2
D Q 100 000
101 010
Clk Q
110 100
111 110
Example 6
reset

Q2 Q1 Q0 Q2* Q1* Q0*

000
000 001
100 001 001 011
010 101
011 111

110 011 100 000

101 010
111 110 100
Johnson counter 111 110

010 101

should never get into these states

State Machines in VHDL
No special method to describe state machines in VHDL
Instead, declare a signal vector to represent state value
Then use CASE statement to assign next state
Example 1 (fig 8.3)
Reset

w = 1
w
State w = 0 Az= 0 Bz= 0
machine z
w = 0
simple
Clock w = 0 w = 1

Resetn
Cz = 1

LIBRARY ieee ; w = 1
USE ieee.std_logic_1164.all ;

ENTITY simple IS Present Next state Output

PORT ( Clock, Resetn, w : IN STD_LOGIC ; state w = 0 w = 1 z
z : OUT STD_LOGIC ) ;
END simple ; A A B 0
B A C 0
C A C 1
7 ARCHITECTURE Behavior OF simple IS
8 TYPE State_type IS (A, B, C) ; Instead of explicitly declaring the flip-
9 SIGNAL y : State_type ; flop values for the states (e.g., state A
10 BEGIN is Q1 Q0 = 0 0, etc), use TYPE
11 PROCESS ( Resetn, Clock ) statement to define names
12 BEGIN
Then you can use those names in the
13 IF Resetn = '0' THEN
14 y <= A ; code
15 ELSIF (Clock'EVENT AND Clock = '1') THEN The compiler will assign Q values
16 CASE y IS
17 WHEN A =>
18 IF w = '0' THEN
19 y <= A ; Next state assignment simply
20 ELSE follows state transition table
21 y <= B ;
22 END IF ;
Present Next state Output
23 WHEN B =>
24 IF w = '0' THEN state w = 0 w = 1 z
25 y <= A ;
26 ELSE A A B 0
27 y <= C ; B A C 0
28 END IF ; C A C 1
29 WHEN C =>
30 IF w = '0' THEN
31 y <= A ;
32 ELSE
33 y <= C ;
34 END IF ;
35 END CASE ;
36 END IF ; For a Moore machine, output
37 END PROCESS ; depends only on state value
38 z <= '1' WHEN y = C ELSE '0' ;
39 END Behavior ;
Example 2 (fig 8.23)
Reset
w = 1z= 0

w = 0z= 0 A B w = 1z= 1

w = 0z= 0

Present Next state Output z

state w= 0 w= 1 w= 0 w= 1
LIBRARY ieee ;
USE ieee.std_logic_1164.all ; A A B 0 0
B A B 0 1
ENTITY mealy IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END mealy ;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS (A, B) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ;
WHEN B =>
IF w = '0' THEN y <= A ;
ELSE y <= B ;
END IF ; Present Next state Output z
END CASE ; state w= 0 w= 1 w= 0 w= 1
END IF ;
END PROCESS ; A A B 0 0
B A B 0 1
PROCESS ( y, w )
BEGIN
CASE y IS
WHEN A => For Mealy machine,
z <= '0' ;
WHEN B => outputs may change
z <= w ;
END CASE ; whenever inputs (w) or
END PROCESS ;
END Behavior ;
state (y) changes
Example 3 (fig 8.91)

State/output table
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY sequence IS
PORT ( Clock, Resetn, w : IN STD_LOGIC ;
z : OUT STD_LOGIC ) ;
END sequence ;

ARCHITECTURE Behavior OF sequence IS

TYPE State_type IS (A, B, C, D, E) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN y <= B ;
ELSE y <= D ;
END IF ;

-- skip some for brevity

WHEN E =>
IF w = '0' THEN y <= B ;
ELSE y <= E ;
END IF ;
END CASE ;
END IF ;
END PROCESS ;
z <= '1' WHEN (y = C OR y = E) ELSE '0' ;
END Behavior ;
Example 4 (fig 8.96)

w
State
machine z

Clock

Resetn

State/output table
Example 4 (fig 8.96)

w
State
machine z

Clock

Resetn

State/output table
 State/output table
ARCHITECTURE Behavior OF seqmealy IS
TYPE State_type IS (A, B, C) ;
SIGNAL y : State_type ;
BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN y <= A ;
ELSIF (Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A =>
IF w = '0' THEN y <= B ;
ELSE y <= C ;
END IF ;
WHEN B => PROCESS ( y, w )
IF w = '0' THEN y <= B ; BEGIN
ELSE y <= C ; CASE y IS
END IF ; WHEN A =>
WHEN C => z <= '0' ;
IF w = '0' THEN y <= B ; WHEN B =>
ELSE y <= C ; z <= NOT w ;
END IF ; WHEN C =>
END CASE ; z <= w ;
END IF ; END CASE ;
END PROCESS ; END PROCESS ;
END Behavior ;