Analog to Digital Converters & Digital to

Analog Converters (ADCs and DACs)

Definitions:
String of bits: b1 b2 b3 bn
MSB LSB

MSB =Most significant bit

LSB =Least significant bit
FS =Full scale

D b1 2 1 b2 2 2 b3 2 3 ... bn 2 n
where bi 0 or 1 based on some " switch"
position in the circuit

D = Fractional Binary Value

2n equally spaced values from 0 (all 0s) to
12n (all 1s) with spacing 2n

e.g. DAC:
vO kVREF D1
where k scale factor
b1 and VREF Reference voltage
b2 vO
D1 . DAC
b3
.
.
bn VFSR kVREF Full Scale Factor/Range
vO VFSR D1

VREF
VFSV 1 2 n VFSR vO MAX
Full Scale Value/Outp ut
 MSB contribution to vO is VFSR/2
LSB contribution to vO is VFSR/2n
DR Dynamic Range 20 log10 2 n 20n log10 2 6n dB

Example
Consider n=3, VREF=1 and k=1.
Vomin= 0 2 0 2 0 2 0
1 2 3

7
Vomax= 1 2 1 1 2 2 1 2 3
8
Converters:Factors to consider
Speed
Accuracy
Resolution
Noise
Cost
Size

Specifications/Parameters:
Absolute (and relative) accuracy
Offset and gain errors
(non-)Linearity
Differential (non-)Linearity
Monotonicity (DAC) / Missing codes (ADC)
Conversion time & sampling rate (ADC)
Settling time & sampling rate (DAC)
Dynamic range

Ideal characteristics

vO

0.5 VFSR

000 010 100 110

001 011 101 0 111

Ideal DAC Characteristic

111

110

101
100

011

010

001
vi
000
0.5 VFSR

Ideal ADC Characteristic

Absolute accuracy:
 refers to the inaccuracy due to all sources of error
maximum deviation of actual output from ideal
(design) output, consisting of,
Zero (Offset) error
Gain error
Linearity errors
Hysteresis errors ( usually small and due to
comparators)
Most easily expressed in fractions of 1 LSB
sometimes in terms of the LSB voltage output
(for DAC) or LSB voltage input (for ADC)

Zero error or offset:

 DAC: Output voltage of DAC when there is zero
code in
ADC: Mean Value of ADC input voltage that is
necessary to produce zero output code

100

011

Zero 010

Error 001

000
000 010 100
001 011
Zero
Error
 The Zero error is nulled by adjustment then gain
error is assessed.

DAC
Gain error: Deviation from design output voltage
for full-scale (FS) input code

ADC:
Gain error: Deviation from design input voltage
for FS output code
due to errors in reference voltage, resistors,
amplifier gains etc.

Gain
Gain error
error
111

110

101
100

011

010

001

000
000 010 100 110
001 011 101 0 111
Gain error is nulled by adjustment then:

Linearity: (Actually the NON-LINEARITY is

specified)
Non-linearity: Deviation (usually the max dev.)
of the characteristic from the ideal
straight line

Differential non-linearity:
DAC: Difference between actual output change
and ideal output voltage ( i.e. 1 LSB voltage)
change for a 1 LSB input code change.
Non-monotonicity occurs Vo starts to decrease
rather than increase with the increasing input code
transitions .
ADC: Difference between actual input voltage
change and ideal input voltage change ( 1LSB
voltage) for a 1 LSB output code change. If greater
than 1 LSB (+ or ) missing codes occur

Non-
monotonic
100

011
Missing
010
code
001

000

000 010 100

001 011
Example:
A 3-bit DAC designed for VFSR = 3.2 V is sequenced
through all input codes from 000 to 111, and the
actual out values are found to be as follows:

Code 000 001 010 011 100 101 110 111

Output, V 0.2 0.5 1.1 1.4 1.7 2.0 2.6 2.9

Find the offset error, the gain error, the integral

nonlinearity (INL) and the differential nonlinearity,
in fractions of 1 LSB

Solution:
VFSR 3.2
Ideally: 1 LSB = 3 0 .4 V
2n 2
1
Offset Error = v O (000) 0.2 V = +
2
LSB

Eliminate offset error by decreasing each output value by 0.2 V

vO(111) = 2.9 0.2 = 2.7 V
Ideally,

V FSV v O (111) V FSR 1 2 3 3.2 1 2 3 = 2.8 V

1
Gain Error = 0.1 V =
4
LSB

Eliminate gain error by using scale factor: multiply all new values of vO by
2.8/2.7 (see table below)
Calculate INLk and DNLk for each value of code k
Note:
INLk = (Vk)actual (Vk)ideal where (Vk)actual is the
corrected(for zero and gain) output voltage at code
k, k = 0, 1, , 2n1 (in binary)

Obviously: INL0 = INL 2n1 = 0

DNLk = INLk INLk1
DNL0 is not defined
k
Obviously: DNL
i 1
i INLk

Code, k 000 001 010 011 100 101 110 111

Corrected 0.0 0.31 0.93 1.24 1.56 1.87 2.49 2.8
Output, Vk [V]
Ideal Vk [V] 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
INLk 0.0 0.09 0.13 0.04 0.04 0.13 0.09 0.0

DNLk 0.09 0.22 0.09 0.08 0.09 0.22 0.09

Look for max values:

1
INL = 0.13 V +
3
LSB
1
and DNL = 0.22 V + LSB
2
Quantization: inherent in ADC and DAC

Signal voltage (or current) range divided into M =

2n levels and sampled values rounded to one of
these.
v FSR
Typically: v
M
Q

= Quantization interval

Model:
Quantizer
v(kT) vQ(kT)

vQ

Q
Q/2 Q/2 v

Quantizer characteristic
 Q = vQ v
Q/2

Q/2 Q v
Q Q/2 3Q/2

Q/2
Quantization error

Can regard this error signal as superimposed noise

Q Q
Q
2 2
Mean 0
Q2
Variance 2
12
Mean squared error
Mean squared noise
Q
RMS noise
12

Mean and RMS often expressed as %FS

D/A Converters DAC
Summing Amp binary-weighted DAC
VREF
S4 R

0.5R R
S3
vo
S2 0.25R

0.125R

S1

S S2 S 3 S 4
vo R 1
VREF where S i is up or down
R R R R
8 4 2
or in general

vO kV REF b1 2 1 b2 2 2 b3 2 3 b4 2 4 kVREF D
where bi 0 or 1 based on " switch" position
D b1 2 1 b2 2 2 b3 2 3 b4 2 4
and k 16

In the above figure:

D 2 1 2 2 2 4 13 16
vO 13VREF

4 switches 16 different levels (0V to 15VREF)

8 switches 256 different levels (0V to 255VREF)
A wide accurate range of resistors required
 R-2R ladder:

2R

2R
2R

2R

2R
v1

vk+1
R

R
vk
v2

vn
i1 i1

ik

ik+1
ik

in
i2

in
2R
VREF

2R
2R

2R
2R

2R

RHS LHS:
The equivalent resistance to the right of each
labelled node equals 2R
the current downward from each node = the
current to the right of the same node
twice that current enters node from the left
currents and node voltages are binary-weighted
1 1
i k 1 i v k 1 v k 1,2 ,... , n 1
2 k 2 k

Resistance spread is only 2-to-1

 4-bit current-mode R-2R ladder DAC:

operates on ladder currents

2R
R

R
2 iS

i2

2 i3
2 i1

i4
i4
i1

i2
R

R
R

R
2

i3
VREF

RF
SW1

SW4
SW3
SW2

iO
vo
b3

b4
b1

b2

VREF 1 1 V REF VREF 1 1 V REF 2

iS ; i1 iS 2 , i2 i1 2
2R 2 2 2R 2R 2 2R
Similarly
V REF 3 VREF 4
i3 2 , i4 2
2R 2R

all currents are directed to ground or virtual

ground by the status of switches SW1 through SW4
(controlled by bits b1 through b4 respectively)
Only 2 values of resistor required easily
implemented in IC form
v0 RF i0
4-bit voltage-mode R-2R ladder DAC:
The 2R resistances are switched between VL and
VH and the ladder output is v1
As the input code is sequenced from 0000 to
1111, v1 changes in steps of 2n(VH VL) from VL
to VH 2n(VH VL).
v1 is buffered with a scale factor K = 1 + RF/R1 to
produce the output vO. I.e.
R
v0 1 F v1
R1

R1 RF

vo
2R
R

R
v1
2R

2R
2R

2R
W1

W4
W3
W2
S

S
S
S

VL
VH

b3

b4
b1

b2
 2R
R

R
v1

R
2
R
2
R
2
R
2

VL
u1

u2

u4
u3
Thevenin Equiv.

R
R

R
v1

R
2
R
2
R
2
1
u 4 VL
u1

u2

u3
2

V L , when bi 0
ui
V H , when bi 1
bi V H V L V L

Open - circuit voltage voc

1
voc voc 1 if VL were removed, and voc 1 u4
2

2R
1
voc voc 2 if u4 were removed, and voc 2 VL
2
By Superposition Principle :

R
2
1
voc voc 1 voc 2 u4 VL
2

VL
u4
2R
R

R
v1

R
2
R
2
R
2

1
u4 VL
u1

u2

u3

2
Similarly:
1 1
u1 u 2 u 3 u 4 V L
1 1
v1
2 2 2 2
1 2 3 4
u1 2 u 2 2 u3 2 u 4 2 VL 2 4

v1 (0000) 2 2 2 2 3 2 4 2 4 V L V L
1

v (0001) 2
1
1
2 2
2 3
2 4
V V
L H V L V L 2 4 V L V H V L 2 4
And so on
Scaled current source D/A

In ICs , current sources are easier to make than

resistors
The emitter areas determine the current levels.
Iout

VCC

RREF S1 S2 S3
IREF
I1 I2 I3
Q1 Q2 Q3
QD
VBE

Area=4 Area=2 Area=1

I out kI REF b1 2 1 b2 2 2 b3 2 3
For example :

I out kI REF
4 0 1 5 kI
REF
16 16
Types of A/D Converter (ADC)
Several types but we shall look at three
DAC-Based ADC

Dual slope integrating ADCs

Flash converters
 DAC-Based ADC

vi
CMP

vD/A
Osc/ Up-down
Clock Counter

D/A

VREF
Worst-case conversion time = (V) S1
where V is the voltage increment of the D/A and S
is the maximum slew rate of the input voltage
 Dual-slope ADC inherently slow

R C

S1 OA1 OA2 CMP

vi v2
S2
VREF CAZ

b1
b2 Counter Control Clock
Logic
bn

START EOC
A1 : unity gain buffer
A2 & RC : precision integrator
CMP : voltage comparator

AUTOZERO PHASE (before START command)

S1 switched to ground & S2 closed
Nonlinear FeedBack around the A2 and CMP
combination
voltage on autozero capacitor (CAZ) forced to voltage
required to bring v2 right to CMP threshold voltage and
hold it there.
overall compensation for input offset voltages of all
three devices
 vx
START
2n N
Autozero counts Autozero
counts

v x Slope Slope
= vi /RC =VREF/RC

Integrate Integrate
vi VREF

SIGNAL INTEGRATION PHASE

START command begins signal integration phase,
Control Logic
opens S2
connects S1 to vi (assumed >0)
enables Counter (starting from zero)

As integrator ramps down counter counts to overflow (2n

clocks periods)
v 2
RC

vi n
2 TCLK where TCLK
1
f CLK
DEINTEGRATE PHASE
At overflow
Counter
resets automatically to zero
signals Control Logic to connect S1 to VREF
integrator ramps up (known as deintegrate
phase) until v2 again reaches CMP threshold
CMP output toggles and signals Control Logic
to stop Counter
issue EOC (end-of-conversion) command

Accumulated count, N
VREF 2n
v 2 NTCLK N bn ...b2 b1 vi

RC V REF

Conversion accuracy independent of R, C, fCLK and

input offsets of three devices. As long as these
parameters remain stable over the conversion period,
they affect both integration phases equally. Hence,
long-term drifts are automatically eliminated
Good linearity and resolution possible. Virtually zero
differential nonlinearity.
Rejects mains noise.
No sample-and hold (SHA) required as vi is simply
averaged over the signal integration phase
Long conversion times, e.g. for mains noise rejection
might chose signal integration time equal to 20ms
(period of 50Hz mains). Worst case conversion time is
then 40ms so rate is 25 samples per sec
Mains Noise Rejection

Assume input is corrupted with mains noise at 50 Hz

vi corrupted vi v n vi Vn cos 2ft where f = 50Hz
t
v2 K
v
0

i corrupted dt where K is a constant

During signal integration phase

T1
vo (T1 ) Kvi T1 K
V
0
n cos 2ftdt

Choose T1 = integral multiple of mains period (20 ms),

say 40 ms or 60 ms, etc., then 2nd term = 0

mains interference rejected

Parallel-comparator or Flash ADC
2-bit shown
VREF

0.5R

CMP1

B0
R

CMP2

vi Logic
Control
R B1

CMP3

CMP4

0.5R

Very fast [10-20 ns] - suitable for video signals

High specification comparators & resistors
required
N-bit requires 2N comparators ! (one for each
level of quantization)