DOI 10.4010/2016.

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ISSN 2321 3361 2016 IJESC

Research Article Volume 6 Issue No. 6

Design of Low Power and Area Efficient Pulsed Latch Based Shift
Register
Athira. B1, Dr. B. Jai Shankar 2
PG Scholar1, Associate Professor 2
KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India

Abstract:
The power consumption and area reduction are the key challenges in the Very Large Scale Integration (VLSI) circuit design. Shift
register is the main building block in the VLSI circuits. The shift register is composed of clock inter connection network and
timing elements such as flip-Flops and latches. This clock inter connection network and timing element is the main power and area
consuming element in the shift register. This project introduces a low power and area efficient shift register using pulsed latch and
pulse generation circuit. If the Flip-Flop is replaced with the pulsed latch the area and power consumption can be reduced to 50%
in the shift register. Different stages of flip-flops and pulsed latches such as SSASPL (Static differential sense amplifier shared
pulsed latch), HLFF (Hybrid latch flip flop), MHLFF (modified Hybrid latch flip flop), ACFF (Adaptive coupling flip flop), TGFF
(transmission gate flip flop), EP-DCO (Explicit pulse data close to output flip flop), CCFF (conditional capture flip flop) are
compared for analyzing the area and power consumption. The SSASPL is more area and power efficient than the other types. The
shift register is designed by using SSASPL combined with pulse generation circuit. All the circuit designs are made by using 90nm
technology in DSCH2 schematic tool and MICROWIND design tool.

Keywords: area-efficient, flip-flop, pulsed cloch. Shift register

1. INTRODUCTION
Low power consumption and area reduction is one of the main
objectives in the designing of VLSI design. The Shift register
is the basic building block in VLSI circuits. It is commonly
used in many applications. The architecture of shift register is
quite simple. The M bit shift register can be is composed of M
data flip-flops. The smallest flip-flops is suitable for designing
of shift register to reduce the area and power consumption.
The Flip-flops is a data storage element. The operation of the
flip-flops is done by its clock frequency. When multistage
Flip-Flop is operated with respect to clock frequency, it
processes with high clock switching activity and then
increases time latency. Therefore it affects the speed and
energy performance of the circuit. Various classes of flip-flops
have been proposed to achieve high-speed and low-energy
operation. In the past decades, many works has been dedicated
to improve the performance of the flip-flops.
Latches and flip-flops are the basic elements for storing
information. The flip-flops and latches could be grouped under
the static and dynamic design styles. One latch or flip- flop
can store one bit of information. The main difference between
latches and flip-flops is that forlatches, their outputs are
constantly affected by their inputs as long as the enable signal
is asserted. In other words, when they are enabled, their
content changes immediately when their inputs change. Flip-
flops, on the other hand, have their content change only either
at the rising or falling edge of the enable signal. This enable
signal is usually the controlling clock signal. After the rising
or falling edge of the clock, the flip-flop content remains
constant even if the input changes.
A methodology has been developed which uses latches
triggered with pulse clock waveforms. With this methodology,
timing analysis and timing optimization to a latch design while
reducing the power of the clock networks can obtain. A latch
can capture data during the sensitive time determined by the
width of clock waveform. If the pulse clock waveform triggers
a latch, the latch is synchronized with the clock similarly to
edge-triggered flip-flop because the rising and falling edges of
the pulse clock are almost identical in terms of timing. With
this approach, the characterization of the setup times of pulsed
latch are expressed with respect to the rising edge of the pulse
clock, and hold times are expressed with respect to the falling
edge of the pulse clock. This means that the representation of
timing models of pulsed latches is similar to that of the edge-
triggered flip-flop.
If the pulsed latch have been replaced with flip-flops in
the designing of shift register the area and power
consumption can be reduced to 50% .Thus the shift register
can solve timing problem by the use of multiple non-overlap
delayed pulsed clock signals instead of the conventional single
pulsed clock signal. These latches and flip flop designs are
made by using 90nm technology in DSCH2 schematic tool
and MICROWIND design tool.
ii PROPOSED METHOD
A master slave flip-flop using two latches can be replaced by a
pulsed latch consisting a latch and a pulsed clock signal. In
this all the pulse latches share pulse generation circuit for the
pulsed clock signal. As a result, the area and power
consumption of the pulsed latch become almost half of those
of the master-slave flip-flop. The pulsed latch is an attractive
solution for small area and low power consumption.
The shift register is designed by consisting of several latches
and pulsed clock signal there will be a timing problem occur.
The schematic diagram shows in Fig 1 consist of several
latches and a pulsed clock signal. The operation wave form

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shows the timing problem in the shift register. The output
signal of the first latch (Q1) changes correctly because the
input signal of the first latch (IN) is constant during the clock
pulse width .But the second latch has an uncertain output
signal (Q2) because its input signal (Q1) changes during the
clock pulse width.
Fig 1.Shift register with latches and pulsed clock signal
(a)Schematic. (b) wave form
The shift register with latches and pulsed clock signal
designed by using DSCH2 tool is shown in Fig 2(a) and its
timing response is shown in Fig .2(b). From this we can
analyze the timing problem of the shift register.
(a)
(b)
Fig 2.simulation of shift register with latches(a) and its timing
diagram(b)
One solution for the timing problem is to add delay circuits
between latches. The output signal of the latch is delayed and
reaches the next latch after the clock pulse. As shown in Fig.3
the output signals of the first and second latches (Q1 and Q2)
change during the clock pulse width , but the input signals of
International Journal of Engineering Science and Computing, June 2016
the second and third latches (D2 and D3) become the same as
the output signals of the first and second latches (Q1 and Q2)
after the clock pulse. As a result, all latches have constant
input signals during the clock pulse and no timing problem
will occur , however the delay of the circuit cause large area
and power consumption.
Fig3. Shift register with latches, delay circuits and a pulse
clock signal (a) schematic and (b) waveform.
The shift register with latches and pulsed clock signal
designed by using DSCH2 tool is shown in Fig4 and its timing
response is shown in Fig 5. From this we can analyze the
timing problem of the shift register is solved. But the delay
circuits cause large area and power consumption. The area and
power estimation of the shift register is shown in the Fig.6 and
Fig.7
Fig 4.shift registers with latches and delay elements.
Fig 5.Timing response of the shift register with delay
elements.
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Fig 6.Area estimation of the shift register with latches and
pulsed elements.
The area of the shift register is large when the delay
components are added between the latches this can be reduced
by using the multiple non-overlap delayed pulsed clock signal.
The delayed pulsed clock signals are generated when a pulsed
clock signal goes through delay circuits. Each latch uses a
pulsed clock signal which is delayed from the pulsed clock
signal used in its next latch. Therefore, each latch updates the
data after its next latch updates the data. As a result, each latch
has a constant input during its clock pulse and no timing
problem occurs between latches. However, this solution also
requires many delay circuits. The schematic representation of
the shift register with latches and delayed pulsed clock and its
waveform is shown in Fig7(a) and Fig7(b).
Fig 7.Shift register with latches and delayed pulsed clock
signals. (a)Schematic. (b) Waveforms.
The shift register with latches and pulsed clock signal
designed by using DSCH2 tool is shown in Fig 8. The area
and power estimation is shown in the Fig 9 and Fig 10.
International Journal of Engineering Science and Computing, June 2016
.
Fig 8.shift register with delayed pulse signal.
Fig 8. Area estimation of the shift register with delayed pulse
signal.
The proposed shift register is divided into M sub shift registers
for reduce the number of delayed pulsed clock signal. The
schematic for proposed shift register is shown in Fig.9 (a) and
its operating wave form is shown in Fig.9 (b). A 4-bit sub
shifter register consists of five latches and it performs shift
operations with five non-overlap delayed pulsed clock signals.
In the 4-bit sub shift register #1, four latches store 4-bit data
and the last latch stores 1-bit temporary data which will be
stored in the first latch of the 4-bit sub shift register. The
proposed shift register reduces number of delayed pulsed
clock signals significant
The maximum clock frequency in the conventional shift
register is limited to only the delay of flip-flops because there
is no delay between flip-flips. Therefore, the area and power
consumption are more important than the speed for selecting
the flip-flop. The proposed shift register uses latches instead
of flip-flops to reduce the area and power consumption.
The pulse generation circuit used in the proposed shift register
has a serially connected chain of delay elements, the first
delay element for receiving an input pulse. It has a plurality of
logic gates with each logic gate having one input coupled to
the output of one delay element in the chain. The other input is
coupled to the output of the next delay element in the chain.
When the input pulse is received, the outputs of the logic gates
form a plurality of non-overlapping pulses.
A pulse generator circuit includes a delay circuit responsive
to an input signal for producing an output signal after a
predetermined delay time, a first logic circuit responsive to
the input signal and this output signal for producing an output
signal having a first logic state when both of the input signal
and the output signal from the delay circuit are concurrently of
a second logic value, a second logic circuit
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responsive to the input signal and the output signal from the
delay circuit for producing an output signal having the first
logic state when both the input signal and the output signal
from the delay circuit are of the first logic value, and a third
logic circuit responsive to the output signal from the first logic
circuit and to the output signal from the second logic circuit
for producing an output signal having a first logic state when
both of the output signal from the first logic circuit and the
output signal from the second logic circuit are concurrently of
the second logic value.

Fig 11.Timing diagram of the pulse generation circuit.

The proposed shift register uses latches instead of Flip-flops

to reduce the area and power consumption Different types of
latches and flip-flops are compared and SSASPL is selected
because of the less consumption of area and power. The
schematic of the SSASPL is shown in the Fig 12. The. area
and power estimation of the SSASPL is shown in the Fig 13
and Fig 14.
The SSASPL updates the data with three NMOS transistors
and it holds the data with four transistors in two cross-coupled
inverters. It requires two differential data inputs and a pulsed
clock signal. When the pulsed clock signal is high, its data is
updated. The node Q or Qb is pulled down to ground
according to the input data. The pull-down current of the
NMOS transistors must be larger than the pull-up current of
the PMOS transistors in the inverters.

Fig 9 Proposed shift register. (a) Schematic. (b) Waveforms.

The circuit for the pulse generation circuit and its timing
diagram is shown in the Fig.10 and Fig 11.
.
Fig 12.Schematic of SSASPL.

Fig 10 Circuit diagram of pulse generation circuit

Fig 13.power estimation of SSASPL.

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 Fig 16.power estimation of proposed shift register.

Fig 14. Area estimation of SSASPL.

There are many other latches and flip-flops are analysed

for the designing of the shift register from that SSASPL is
considered small in size and less power consumption.
HLFF,EP-DCO,TGFF CCFF and ACFF are some of them.
The performance comparison of those latches and flip-flops
are shown in the table 1.
Total Power Area required Fig 17.Area estimation of the proposed shift register.
number of consumed
transistors The layout diagram of the proposed shift register is
constructed by using MICROWIND and it is shown in the Fig
18.
SSASPL 21 10.137W 65.5m
HLFF 20 32.113W 205 m

Pulsed EP-DCO 28 27.966W 441.2m

latch
Flip- CCFF 28 11.195W 92.4 m
flop

ACFF 22 18.781W 210.7m

Table 1. Performance comparison of latches and flip-flops.

From the above table we can analyze that the SSASPL is
more efficient. The proposed shift register designed by using
SSASPL is shown the Fig 18.Layout diagram of proposed shift register.
fig 15. The power and area estimation of the shift register is
shown in Fig 16 and Fig 17. iii. PERFORMANCE COMPARISON

POWER DELAY AREA POWER

DELAY
PRODUCT
1 51.977W 43psec 425.7m^2 223.5011

2 57.357 58psec 510.6 332.6706

W m^2
3 43.103 24psec 489.7 103.447
W m^2
4 10.923 2.14psec 263.7 23,375
W m^2
Table2.performance comparison of the shift registers.
The performance comparison of different shift register design
Fig 15. Proposed shift register using pulsed latch. is shown in the table 2, in the terms of area, power, delay and
power delay product. From the analysis the shift register

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designed by using pulsed latch and pulse generation circuit is
more efficient in terms of area and power.

iv. CONCLUSION
This paper proposes a low power and area efficient shift
register using pulsed latch. The shift register reduces area and
power consumption by replacing flip-flops with pulsed latch.
The pulse Triggered concept is implemented in the shift
register using SSASPL (Static differential Sense Amplifier
Shared Pulsed Latch) and pulse generation circuit.. The area,
power and power delay product of the pulsed latch and Flip-
Flop is initially identified and the SSASPL is selected to
design the shift register which consume less area and power.
The shift registers designed by using static differential sense
amplifier shared pulse latch(SSASPL) design, and is then
compared with the shift register designed with multiple non-
overlapped delayed pulsed clock then observed and verified
the parameters and analyze that the proposed shift register is
more power and area efficient.

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